CN103295950A - Shallow groove isolating structure manufacturing method - Google Patents
Shallow groove isolating structure manufacturing method Download PDFInfo
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- CN103295950A CN103295950A CN2012100453996A CN201210045399A CN103295950A CN 103295950 A CN103295950 A CN 103295950A CN 2012100453996 A CN2012100453996 A CN 2012100453996A CN 201210045399 A CN201210045399 A CN 201210045399A CN 103295950 A CN103295950 A CN 103295950A
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- isolation structure
- etching
- fleet plough
- groove isolation
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Abstract
The invention provides a shallow groove isolating structure manufacturing method which comprises the steps that an oxidation layer and an etching blocking layer are formed on a semiconductor substrate in sequence; a groove is formed by etching; a liner layer with silicon nitride materials mixed with carbon deposited covers the bottom face and the side wall of the groove; a thermal oxidation process and an annealing process are carried out; isolating materials are deposited to fill the groove; chemical mechanical lapping is carried out; the liner layer outside the groove, the etching blocking layer, the oxidation layer and partial isolating materials are removed by etching, and a shallow groove isolating structure is formed. After the groove is formed by etching, the liner layer with the silicon nitride materials mixed with the carbon deposited is covered, the thermal oxidation process and the annealing process are carried out, so that part of the silicon nitride materials mixed with the carbon is changed to silicon oxynitride, the carbon in the silicon nitride materials mixed with the carbon enters the connecting interface of the liner layer and the groove, and accordingly boron mixing diffusion is prevented from entering the shallow groove isolating structure, boron mixing concentration lowering is avoided, and therefore the mixing zone concentration of a semiconductor part is protected, and the performance of the semiconductor part is improved.
Description
Technical field
The present invention relates to the manufacture method of semiconductor device structure, relate in particular to a kind of manufacture method of fleet plough groove isolation structure.
Background technology
Along with the integrated level of semiconductor device is more and more higher, process for fabrication of semiconductor device enters the deep-submicron epoch, 0.13um following element, for example the isolation between the nmos pass transistor in the cmos device and the PMOS transistor all adopts STI (shallow trench isolation from) technology to form.
The formation method of traditional fleet plough groove isolation structure generally includes following steps: at first, provide Semiconductor substrate, form oxide layer and etching barrier layer successively on described Semiconductor substrate; Then, form the photoresist layer of patterning at described etching barrier layer, make described etching barrier layer the subregion be exposed; Then the photoresist layer with patterning is mask, the described etching barrier layer of etching, oxide layer and Semiconductor substrate, thus in Semiconductor substrate, forming groove, the shape of this trench cross section can be rectangle or trapezoidal; Then in groove, deposit isolated material, and carry out cmp and etching technics, finally form fleet plough groove isolation structure.
In the transistorized semiconductor device of for example PMOS; in the Semiconductor substrate between fleet plough groove isolation structure; usually can form P type doped region by the method for injecting; claim the P trap again; injecting ion for example is boron, because the atomic radius of boron is very little, very easily forms interstitial diffusion and enters in the fleet plough groove isolation structure; diffusion has reduced the concentration of doping ion in the P trap, and then influences the cut-in voltage of semiconductor device.Because diffusion is restive, causes that the cut-in voltage of a plurality of semiconductor device has nothing in common with each other in the integrated circuit, causes the time started difference, job insecurity, and then influence yield and the stability of integrated circuit.
For solving the problems of the technologies described above, usually after forming groove, at first deposit the bottom surface of laying covering groove of one deck silicon nitride material and sidewall to reduce boron doped diffusion effect in the prior art.Yet said method is limited to the control ability of diffusion, and under the condition that dimensions of semiconductor devices constantly descends, diffusion phenomena still are difficult to control.
Summary of the invention
The purpose of this invention is to provide a kind of can reduce better mix diffuse into fleet plough groove isolation structure, keeping the concentration of doped region in the semiconductor device, and then improve the manufacture method of fleet plough groove isolation structure of the service behaviour of semiconductor device.
For addressing the above problem, the invention provides a kind of manufacture method of fleet plough groove isolation structure, comprising: Semiconductor substrate is provided, on described Semiconductor substrate, forms oxide layer and etching barrier layer successively; Utilize photoetching and etching technics, etched portions etching barrier layer, oxide layer and Semiconductor substrate are to form groove; The deposit liner layer covers bottom surface and the sidewall of described groove, and the material of described laying is the carbon dope silicon nitride; Carry out thermal oxidation technology and annealing process; The deposition isolated material is to fill described groove; Carry out cmp until exposing described laying; Etching is removed shallow trench outer laying, described etching barrier layer, described oxide layer and part isolated material, until exposing described Semiconductor substrate, forms fleet plough groove isolation structure.
Further, the material of described etching barrier layer is silicon nitride.
Optionally, described laying adopts Low Pressure Chemical Vapor Deposition to form, and reactant comprises ammonia, ethene and dichlorosilane, and reaction temperature is 450 ℃～600 ℃.
Optionally, described laying adopts Low Pressure Chemical Vapor Deposition to form, and reactant comprises ammonia, ethene and disilicone hexachloride, and reaction temperature is 450 ℃～600 ℃.
Further, the thickness of described laying is 1nm～10nm.
Further, the molar concentration content of carbon is 1%～10% in the described laying.
Further, described thermal oxidation technology adopts boiler tube thermal oxidation method or original position steam method of formation.
Further, the annealing temperature of described annealing process is 900 ℃～1150 ℃.
Further, the material of the described etching barrier layer of etching comprises phosphoric acid.
Further, the material of the described oxide layer of etching and isolated material comprises the hydrofluoric acid of dilution.
In sum; the manufacture method of fleet plough groove isolation structure of the present invention is by after forming groove in etching; cover the laying of carbon dope silicon nitride material; and carry out thermal oxidation technology and annealing process; make that the part silicon nitride becomes silicon oxynitride in the carbon dope silicon nitride; and the carbon in the carbon dope silicon nitride enters laying and groove joins at the interface; thereby suppress the boron doped fleet plough groove isolation structure that diffuses into; avoid the minimizing of boron doping concentration in the doped region; thereby the doped region concentration of protection semiconductor device, the performance of raising semiconductor device.
Description of drawings
Fig. 1 is the schematic flow sheet of the manufacture method of fleet plough groove isolation structure in one embodiment of the invention.
Fig. 2～Fig. 7 is the structural representation in the manufacturing process of fleet plough groove isolation structure in one embodiment of the invention.
Embodiment
For making content of the present invention clear more understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art also is encompassed in protection scope of the present invention.
Secondly, the present invention utilizes schematic diagram to carry out detailed statement, and when example of the present invention was described in detail in detail, for convenience of explanation, schematic diagram did not amplify according to general ratio is local, should be with this as limitation of the invention.
Fig. 1 is the schematic flow sheet of the manufacture method of fleet plough groove isolation structure in one embodiment of the invention.As shown in Figure 1, the invention provides a kind of manufacture method of fleet plough groove isolation structure, may further comprise the steps:
Step S01: Semiconductor substrate is provided, on described Semiconductor substrate, forms oxide layer and etching barrier layer successively;
Step S02: utilize photoetching and etching technics, the described etching barrier layer of etching, oxide layer and Semiconductor substrate are to form groove;
Step S03: the deposit liner layer covers bottom surface and the sidewall of described groove, and the material of described laying is the carbon dope silicon nitride;
Step S04: carry out thermal oxidation technology and annealing process;
Step S05: the deposition isolated material is to fill described groove;
Step S06: carry out cmp until exposing described laying;
Step S07: etching is removed shallow trench outer laying, described etching barrier layer, described oxide layer and part isolated material, until exposing described Semiconductor substrate, forms fleet plough groove isolation structure.
Fig. 2～Fig. 7 is the structural representation in the manufacturing process of fleet plough groove isolation structure in one embodiment of the invention.In conjunction with Fig. 1～Fig. 7, below describe the manufacture method of fleet plough groove isolation structure of the present invention in detail.
As shown in Figure 2, in step S01, provide Semiconductor substrate 100, on described Semiconductor substrate 100, form oxide layer 101 and etching barrier layer 103 successively; The material of described Semiconductor substrate 100 can be monocrystalline silicon, polysilicon, amorphous silicon, silicon Germanium compound or silicon-on-insulator (SOI) etc., in Semiconductor substrate 100, can form doped region, for example for forming boron doped P well region in the transistorized Semiconductor substrate of PMOS.The material of described oxide layer 101 is silicon dioxide, can adopt thermal oxide growth method or chemical vapour deposition technique to form, and wherein preferred methods is the thermal oxide growth method, and the oxide layer 101 that adopts the thermal oxide growth method to form has better compact texture; The material of described etching barrier layer 103 is silicon nitride, can adopt thermal oxide growth method, chemical vapour deposition technique or physical vaporous deposition to form, for example formation method is under 400 ℃～600 ℃ reaction temperature, feed the reactant of dichlorosilane and ammonia, form the etching barrier layer 103 of silicon nitride material, the preferable thickness of described etching barrier layer is 80nm～150nm.Described etching barrier layer 103 is as the layer that stops that carrying out cmp, and described oxide layer 101 can be protected Semiconductor substrate 100 when forming etching barrier layer 103, and removes the etching stop layer of etching barrier layer 103 as subsequent etching.
As shown in Figure 3, in step S02, utilize photoetching and etching technics, the described etching barrier layer 103 of etching, oxide layer 101 and Semiconductor substrate 100 are to form groove 200; Adopt photoetching process, at first apply photoresist layer at etching barrier layer 103, utilize exposure imaging patterning photoresist layer, photoresist layer with patterning is mask then, the described etching barrier layer 103 of etching, oxide layer 101 and Semiconductor substrate 100, thereby form groove 200, the degree of depth of this groove 200 in Semiconductor substrate 100 is the degree of depth of follow-up fleet plough groove isolation structure.
Key of the present invention is step S03 and step S04, and as shown in Figure 4, in step S03, deposit liner layer 105 covers bottom surface and the sidewall of described groove 200, and the material of described laying 105 is the carbon dope silicon nitride; The carbon dope silicon nitride can adopt Low Pressure Chemical Vapor Deposition to form, and reactant comprises ammonia (NH
3), ethene (C
2H
4) and dichlorosilane (SiH
2Cl
2), perhaps reactant comprises ammonia, ethene and disilicone hexachloride (Si
2Cl
6), preferable reaction temperature is 450 ℃～600 ℃.The thickness of described laying 105 is 1nm～10nm, wherein the molar concentration content of carbon is 1%～10% in the laying 105, in this concentration range, carbon is easy to dissociate in subsequent anneal technology from the carbon dope silicon nitride structure, enter laying 105 and groove 200 intersection interface places, thereby stop that the boron diffusion of plasma enters in the fleet plough groove isolation structure in the doped region of semiconductor device, reduce the concentration in the doped region.
Then, in step S04, carry out thermal oxidation technology and annealing process, described thermal oxidation technology adopts boiler tube thermal oxidation method or original position steam method of formation (ISSG), adopts original position steam method of formation in preferred embodiment, and oxidization time is short, the process efficiency height damages little.The annealing temperature of described annealing process is 900 ℃～1150 ℃.In thermal oxidation technology; make that the part silicon nitride becomes silicon oxynitride in the carbon dope silicon nitride material of laying 105; can form contact interface better with the isolated material 107 of follow-up formation; reduce the generation of defective; and then reduce boron doped diffusion; in annealing process; carbon in the described carbon dope silicon nitride dissociates to enter with groove from the carbon dope silicon nitride structure and joins at the interface; further suppress the boron doped fleet plough groove isolation structure that diffuses into; avoid the minimizing of boron doping concentration in the doped region; thereby the doped region concentration of protection semiconductor device, the performance of raising semiconductor device.
In step S05, deposition isolated material 107 is to fill described groove 200; Can adopt HDPCVD (high density plasma enhanced chemical vapor deposition) method deposition isolated material, described isolated material can be in silicon dioxide, fluorine silex glass, unadulterated silicate glass (USG) or the positive tetraethyl orthosilicate one or more, forms structure as shown in Figure 4.
As shown in Figure 5, in step S06, carry out cmp until exposing described laying 105.
As shown in Figure 6 and Figure 7, in step S07, etching is removed shallow trench outer laying 105, described etching barrier layer 103, described oxide layer 101 and part isolated material 107, until exposing described Semiconductor substrate 100, forms fleet plough groove isolation structure 109.In this step, at first utilize etching material etching laying 105 and the etching barrier layer 103 that comprises phosphoric acid, phosphoric acid to the etching speed of laying 105 and etching barrier layer 103 much larger than the etching speed to oxide layer 101 and isolated material 107, form structure as shown in Figure 6, then, utilization comprises etching material etching oxidation layer 101 and the part isolated material 107 of hydrofluoric acid, and the material of the described etching barrier layer 103 of etching comprises phosphoric acid.The material of the described oxide layer 101 of etching and isolated material 107 comprises the hydrofluoric acid of dilution, forms structure as shown in Figure 7.In preferred embodiment, the height of remaining isolated material is higher than Semiconductor substrate 100 in the fleet plough groove isolation structure 109 that forms, avoid the subsequent etching step further to damage and reduce fleet plough groove isolation structure 109, thus the isolating power of raising fleet plough groove isolation structure.
In sum; the invention provides a kind of manufacture method of fleet plough groove isolation structure; after etching forms groove; at the bottom surface of described groove structure and the laying of sidewall covering carbon dope silicon nitride material; and carry out thermal oxidation technology and annealing process; make that the part silicon nitride becomes silicon oxynitride in the carbon dope silicon nitride; and the carbon in the carbon dope silicon nitride enters laying and groove joint at the interface; thereby suppressing boron doped diffuses in the fleet plough groove isolation structure; avoid the minimizing of boron doping concentration in the doped region; thereby protect the doped region concentration of semiconductor device, keep the performance of semiconductor device.
Though the present invention discloses as above with preferred embodiment; so it is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (10)
1. the manufacture method of a fleet plough groove isolation structure comprises:
Semiconductor substrate is provided, on described Semiconductor substrate, forms oxide layer and etching barrier layer successively;
Etched portions etching barrier layer, oxide layer and Semiconductor substrate are to form groove;
The deposit liner layer covers bottom surface and the sidewall of described groove, and the material of described laying is the carbon dope silicon nitride;
Carry out thermal oxidation technology and annealing process;
The deposition isolated material is to fill described groove;
Carry out cmp until exposing described laying;
Etching is removed shallow trench outer laying, described etching barrier layer, described oxide layer and part isolated material, until exposing described Semiconductor substrate, forms fleet plough groove isolation structure.
2. the manufacture method of fleet plough groove isolation structure as claimed in claim 1 is characterized in that, the material of described etching barrier layer is silicon nitride.
3. the manufacture method of fleet plough groove isolation structure as claimed in claim 2 is characterized in that, described laying adopts Low Pressure Chemical Vapor Deposition to form, and reactant comprises ammonia, ethene and dichlorosilane, and reaction temperature is 450 ℃～600 ℃.
4. the manufacture method of fleet plough groove isolation structure as claimed in claim 2 is characterized in that, described laying adopts Low Pressure Chemical Vapor Deposition to form, and reactant comprises ammonia, ethene and disilicone hexachloride, and reaction temperature is 450 ℃～600 ℃.
5. the manufacture method of fleet plough groove isolation structure as claimed in claim 1 is characterized in that, the thickness of described laying is 1nm～10nm.
6. the manufacture method of fleet plough groove isolation structure as claimed in claim 1 is characterized in that, the molar concentration content of carbon is 1%～10% in the described laying.
7. the manufacture method of fleet plough groove isolation structure as claimed in claim 1 is characterized in that, described thermal oxidation technology is boiler tube thermal oxidation method or original position steam method of formation.
8. the manufacture method of fleet plough groove isolation structure as claimed in claim 1 is characterized in that, the annealing temperature of described annealing process is 900 ℃～1150 ℃.
9. the manufacture method of fleet plough groove isolation structure as claimed in claim 1 is characterized in that, the material of the described etching barrier layer of etching comprises phosphoric acid.
10. the manufacture method of fleet plough groove isolation structure as claimed in claim 1 is characterized in that, the material of the described oxide layer of etching and isolated material comprises the hydrofluoric acid of dilution.
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104157602A (en) * | 2014-08-27 | 2014-11-19 | 上海华力微电子有限公司 | Preparation method for shallow trench isolation structure |
| CN106158610A (en) * | 2015-04-03 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | FGS floating gate structure, its manufacture method and include its flash memory |
| CN106158720A (en) * | 2015-04-03 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of semiconductor device |
| CN107993975A (en) * | 2017-11-27 | 2018-05-04 | 长江存储科技有限责任公司 | Semiconductor making method |
| CN108649013A (en) * | 2018-04-25 | 2018-10-12 | 睿力集成电路有限公司 | The forming method of active area |
| CN111106057A (en) * | 2019-11-18 | 2020-05-05 | 华虹半导体(无锡)有限公司 | Method for manufacturing STI (shallow trench isolation) structure of flash memory device and flash memory device |
| CN111430293A (en) * | 2020-04-28 | 2020-07-17 | 长江存储科技有限责任公司 | Method for manufacturing shallow trench isolation structure |
| CN112680715A (en) * | 2020-11-12 | 2021-04-20 | 中国科学院微电子研究所 | Growth method of silicon nitride film and preparation method of thick film silicon nitride waveguide device |
| CN115424977A (en) * | 2022-11-03 | 2022-12-02 | 广州粤芯半导体技术有限公司 | Preparation method of shallow trench isolation structure and preparation method of semiconductor structure |
| CN116525536A (en) * | 2023-06-30 | 2023-08-01 | 合肥晶合集成电路股份有限公司 | Shallow trench isolation structure for semiconductor device and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104157602A (en) * | 2014-08-27 | 2014-11-19 | 上海华力微电子有限公司 | Preparation method for shallow trench isolation structure |
| CN104157602B (en) * | 2014-08-27 | 2019-11-22 | 上海华力微电子有限公司 | The preparation method of fleet plough groove isolation structure |
| CN106158610B (en) * | 2015-04-03 | 2019-07-16 | 中芯国际集成电路制造(上海)有限公司 | FGS floating gate structure, its production method and the flash memory including it |
| CN106158610A (en) * | 2015-04-03 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | FGS floating gate structure, its manufacture method and include its flash memory |
| CN106158720A (en) * | 2015-04-03 | 2016-11-23 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of semiconductor device |
| CN107993975A (en) * | 2017-11-27 | 2018-05-04 | 长江存储科技有限责任公司 | Semiconductor making method |
| CN107993975B (en) * | 2017-11-27 | 2019-01-29 | 长江存储科技有限责任公司 | Semiconductor making method |
| CN108649013A (en) * | 2018-04-25 | 2018-10-12 | 睿力集成电路有限公司 | The forming method of active area |
| CN111106057A (en) * | 2019-11-18 | 2020-05-05 | 华虹半导体(无锡)有限公司 | Method for manufacturing STI (shallow trench isolation) structure of flash memory device and flash memory device |
| CN111430293A (en) * | 2020-04-28 | 2020-07-17 | 长江存储科技有限责任公司 | Method for manufacturing shallow trench isolation structure |
| CN112680715A (en) * | 2020-11-12 | 2021-04-20 | 中国科学院微电子研究所 | Growth method of silicon nitride film and preparation method of thick film silicon nitride waveguide device |
| CN115424977A (en) * | 2022-11-03 | 2022-12-02 | 广州粤芯半导体技术有限公司 | Preparation method of shallow trench isolation structure and preparation method of semiconductor structure |
| CN116525536A (en) * | 2023-06-30 | 2023-08-01 | 合肥晶合集成电路股份有限公司 | Shallow trench isolation structure for semiconductor device and preparation method thereof |
| CN116525536B (en) * | 2023-06-30 | 2023-10-03 | 合肥晶合集成电路股份有限公司 | Shallow trench isolation structure for semiconductor device and preparation method thereof |
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