CN103283007B - 不流动底充胶 - Google Patents
不流动底充胶 Download PDFInfo
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- CN103283007B CN103283007B CN201180063433.6A CN201180063433A CN103283007B CN 103283007 B CN103283007 B CN 103283007B CN 201180063433 A CN201180063433 A CN 201180063433A CN 103283007 B CN103283007 B CN 103283007B
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Abstract
制造微电子组件的方法包括,提供具有第一导电元件的微电子元件(30)和具有第二导电元件的介电元件(50)。第一导电元件或第二导电元件中至少一些可为导电柱(40),而其他的第一导电元件或第二导电元件可包括位于一些导电柱(40)之间的结合金属(10)。底充胶层(60)可覆盖一些第一导电元件或第二导电元件。至少一个第一导电元件可朝另一第二导电元件移动,使得柱刺穿底充胶层(60)并至少使结合金属(10)变形。可加热微电子元件(30)和介电元件(50),以使其接合在一起。柱(40)在表面上方的高度可为微电子元件(30)与介电元件(50)的表面之间距离的至少百分至四十。
Description
相关申请的交叉引用
本申请是申请号为12/938068、申请日为2010年11月2日的美国专利申请的继续申请,其公开的内容以引用的方式并入本文。
背景技术
在半导体芯片封装组件的结构中,已发现,半导体封装的各元件之间和/或围绕各元件填充密封剂材料或底充胶是非常可取的,在芯片工作过程中,能使半导体芯片与支撑电路基板或介电元件之间连接处的应变及应力降低和/或再分布,且可使各元件密封以防止腐蚀,同时可确保芯片封装中密封剂、半导体裸片及其他元件之间的紧密接触。
为密封半导体芯片封装组件及类似物,已设计出各种方法。尽管致力于微电子密封技术的发展,已进行了很多努力,但仍需要进一步改进。
发明内容
用于制造微电子组件的方法,可包括:提供第一元器件和第二元器件,第一元器件具有第一表面和在第一表面上突出的第一导电元件,第二元器件具有第二表面和在第二表面上突出的第二导电元件。第一元器件和第二元器件中至少一个可为微电子元件,至少一些第一导电元件或至少一些第二导电元件可为基本刚性的导电柱,这些柱可具有在其突出的相应表面上方的高度,该高度至少为第一表面和第二表面之间距离的百分之四十。结合金属可至少设置在至少一些第一导电元件上、或者至少一些第二导电元件上,底充胶层可至少覆盖至少一些第一导电元件或至少一些第二导电元件。该方法可包括,使至少一个第一导电元件朝另一个第二导电元件移动,使得基本刚性的柱剌穿底充胶层,并至少使结合金属变形。该方法可包括,加热第一元器件及第二元器件至接合温度,直至结合金属沿柱的边缘流动,并使第一元器件与第二元器件电连接。结合金属可沿柱高度的至少一半与边缘接触。
根据本发明的另一方面,用于制造微电子组件的方法,可包括:提供微电子元件和介电元件,微电子元件具有第一表面和在第一表面上突出的第一导电元件,介电元件具有第二表面和在第二表面上突出的第二导电元件。至少一些第一导电元件或至少一些第二导电元件可为基本刚性的导电柱,其他的第一导电元件或第二导电元件可包括与至少一些导电柱并置的结合金属。各柱可具有在其突出的相应表面上方的高度,底充胶层覆盖至少一些第一导电元件或至少一些第二导电元件。该方法可包括,使至少一个第一导电元件朝另一第二导电元件移动,使得基本刚性的柱刺穿底充胶层,并至少使结合金属变形。该方法可包括加热微电子元件和介电元件至接合温度,直至结合金属沿柱的边缘流动,并沿柱高度的至少一半与边缘接触,及使微电子元件与介电元件电连接。这些柱在其突出的相应表面上方的高度,可至少为第一表面和第二表面之间距离的百分之四十。
在一个实施例中,第一导电元件包括结合金属,且至少一些导电柱为介电元件的第二导电元件。
在一个实施例中,至少一些柱为微电子元件的第一导电元件,且第二导电元件包括结合金属。
在一个实施例中,使至少一个第一导电柱朝另一个第二导电元件移动的步骤包括,基本刚性的柱剌入结合金属。
在一个实施例中,使至少一个第一导电元件朝另一导电元件移动的步骤包括,穿过结合金属的深度为,第一表面或第二表面中相应一个上方的焊料高度的至少25%。
在一个实施例中,在使结合金属变形的步骤之前,微量的底充胶层被导电柱推入结合金属内。
在一个实施例中,第一元器件可为芯片或互连元件。
在一个实施例中,第一元器件和第二元器件可都为芯片,或第二元器件可为互连元件。
在一个实施例中,至少一些第一导电元件可为基本刚性的柱;或至少一些第一导电元件可为导电垫;或至少一些第二导电元件可为基本刚性的柱;或至少一些第二导电元件可为导电垫。
在一个实施例中,底充胶可覆盖第一导电元件;或底充胶可覆盖第二导电元件;或底充胶可覆盖第一导电元件及第二导电元件。
在一个实施例中,第一元器件可为微电子元件,至少一些第一导电元件可为接触垫,且至少一些第二导电元件为基本刚性的柱。替代地,第二元器件可为互连元件或微电子元件。在另一替代实施例中,提供步骤可包括,在至少一些基本刚性的柱上提供结合金属,或在至少一些接触垫上提供结合金属。
在一个实施例中,第一元器件可为微电子元件,至少一些第一导电元件可为基本刚性的柱,且至少一些第二导电元件可为接触垫。替代地,第二元器件可为互连元件或微电子元件。
在一个实施例中,第一元器件可为微电子元件,至少一些第一导电元件可为基本刚性的柱,且至少一些第二导电元件可为基本刚性的柱。替代地,第二元器件可为互连元件或微电子元件。
根据本发明另一方面,微电子组件包括,第一元器件、第二元器件、结合金属及底充胶层。第一元器件可具有第一表面和在第一表面上突出的第一导电元件。第二元器件可具有第二表面和在第二表面上突出的第二导电元件。第一元器件或第二元器件中至少一个可为微电子元件,至少一些第一导电元件或至少一些第二导电元件可为基本刚性的导电柱,且可具有在柱从其上突出的相应表面上方的高度。结合金属可设置在各成对的导电元件之间,各成对导电元件中每个都包括至少一个柱和与该至少一个柱面对的至少一个第一导电元件或第二导电元件。结合金属还可沿柱高度的至少一半与柱的边缘接触。底充胶层可与第一元器件的第一表面及第二元器件的第二表面接触并结合。在至少一些柱与结合金属之间的至少一个界面处存在底充胶层的残渣,或在结合金属内存在底充胶层的残渣。
在一个实施例中,第一元器件可为微电子元件,且第二元器件可为介电元件。替代地,微电子元件可为芯片。
在一个实施例中,第一元器件可为介电元件。
在一个实施例中,第一元器件和第二元器件可都为微电子元件;或第一导电元件可为导电柱。
在一个实施例中,第二导电元件可为导电柱。
在一个实施例中,第一导电元件和第二导电元件可都为导电柱。
在一个实施例中,结合金属可堆积在至少一个导电柱上。
在一个实施例中,焊料掩模可设置为与导电柱邻接,或导电柱的至少一部分可涂敷抵抗结合金属的材料。
在一个实施例中,结合金属可覆盖至少一个导电柱的一半或小于一半的高度。
在一个实施例中,第二导电元件可为导电柱。
附图说明
图1是根据本发明一个实施例的体现。
图2是图1(c)的俯视图。
图2A是图1(f)的一部分的分解图。
图3是图1的替代实施例。
图4是图1的替代实施例。
图5是图1的另一替代实施例。
图6是图1的另一替代实施例。
图7是图6的替代实施例。
图8是图1的另一替代实施例。
图9是图1(f)一部分的替代实施例。
图10是根据本发明实施例的系统。
图11是根据本发明一个实施例系统的示意图。
具体实施方式
图1是根据本发明实施例微电子封装100(图1(f))制备方法的截面图。如图所示,微电子封装100包括微电子元件30和其上有导电柱40暴露的介电元件50(图1(a)至图1(b))。
参照图1(a),在一个示例中,微电子元件30可为单个的“裸片”,即未封装裸片,如其上具有微电子电路的半导体芯片。复数个触点,如结合垫20,可在半导体裸片的触点承载表面32上暴露,且可在此表面上布置为一排或多排。
如在本文应用的,声明导电元件“暴露在”介电元件的表面,指的是导电元件可与一理论点接触,该理论点以垂直于该介电元件表面的方向从介电元件外部向该介电元件表面移动。因此,暴露在介电元件表面上的端子或其他导电元件可从该表面突出;可与该表面平齐;或可相对该表面凹陷,并通过介电元件上的孔或凹坑暴露。
结合金属10,如焊料、铟、锡、或其组合,可与微电子元件30的结合垫20接合。
参照图1(b),在一个实施例中,可提供其表面有导电元件暴露的介电元件50,如基板、芯片载体、带等。在一个实施例中,介电元件50可具有大于微电子元件长度L2的长度L1。替代地,介电元件与微电子元件的长度可相同。在所示的实施例中,导电元件为基本刚性的金属柱40,从介电元件50的顶面52向上或向外延伸。柱40可采用本领域中已知的任意方法制备。
例如,如菲耶尔斯塔德(Fjelstad)的专利号为6177636的美国专利中所述,从基板表面彼此平行地突出的复数个基本刚性的细长柱,可通过在基板表面附接导电板、然后选择性去除导电板的一部分而形成,其公开的内容以引用的方式并入本文。金属板可主要由铜组成,或可具有一层或多层铜,且其内可具有一层或多层其他金属,如镍等的蚀刻隔离金属。柱的顶端可共面。
因此,例如,基本刚性的柱可通过光刻技术(lithography)而图案化,从附接至介电元件50的导电板上形成在介电元件50顶面52上方向上延伸的实心金属柱。这种过程倾向于形成截头圆锥形状的金属柱,其中柱的边缘从导电柱40的顶端42向外倾斜。类似地,柱可通过双重蚀刻过程而形成,如共同转让的公开号为2008/0003402、申请日为2007年3月13日的美国专利申请中所公开的,其公开的内容以引用的方式并入本文。替代地,柱可如以下专利申请中所公开的方法形成,如哈巴(Haba)的共同转让的公开号为2010/0044860、申请日为2009年7月30日的美国专利申请,或者如远腾(Endo)的公开号为2009/0188706、申请日为2008年12月23日的美国专利申请,其中所有公开的内容以引用的方式并入本文。
另外,在大沢(Oosawa)等人的专利号为6372620和6617236的美国专利中描述了用于在金属基板上形成柱的电解电镀方法,其公开的内容以引用的方式并入本文。与在蚀刻过程中导电层在基板上的暴露部分是被除去不同,基本刚性的导电柱通过在基板的暴露部分上沉积金属而形成。与蚀刻过程中生成的截头圆锥形状形成对比,这些柱可具有更均匀的圆的形状。
参照图1(c),可在介电元件50上沉积预定量的底充胶,使得底充胶60覆盖介电元件50的暴露顶面52和柱40。在一个示例性的实施例中,底充胶60可旋涂在介电元件50的顶面52及柱40的顶面或顶端42上。导电柱的边缘表面44及顶端42可与底充胶60接触,从而柱被底充胶完全覆盖(参见图1(c)和图2)。底充胶可包括聚合物组分,在组件最终封装及包装后,聚合物组分使微电子元件30与介电元件50之间机械连接的刚度增加。
现在参照图1(d),微电子元件30上的结合金属块,如焊料10,可与远离介电元件50而延伸的导电柱40并置。在所示的实施例中,焊料块10可朝导电柱40移动,即,通过使微电子元件朝基板移动而移动焊料块。替代地,其上具有导电柱40的基板可朝着微电子元件的焊料块10移动,或者焊料及导电柱都移动而彼此靠近。例如,裸片30和介电元件50可放置在相应的板(未示出)上,通过沿方向62、64中的一个方向移动微电子元件30或介电元件50中的一个、或沿该两个方向移动二者,而使导电柱40和焊料10可移动并靠近在一起。为确保导电柱40与焊料10紧密配合,焊料10可压入底充胶60内,使得底充胶60的至少一部分变形。在这种布置中,底充胶60可与介电元件50的顶面52及焊料10的边缘表面44接触,但与微电子元件30的触点承载表面32可以接触或可不接触。在特定实施例中,该方法可包括,使导电柱与结合金属块对齐的步骤。但是,在一些情况下,无需使柱与结合金属对齐的步骤,而使介电元件的柱与微电子元件上的结合金属接合也是可能的。亦即,当结合金属被加热至液化温度时,结合金属可具有使结构自对齐的倾向,在此时结合金属的表面张力可帮助导电柱与结合金属块更好地对齐。
现在转至图1(e),微电子元件30可继续朝着介电元件50移动,使得导电柱40的顶端42嵌入底充胶60内。即使没有完全穿入焊料10内,顶端42至少也使焊料10的至少一部分变形。在一个实施例中,导电柱40至少穿入距离D(图1(e)),该距离为焊料10远离微电子元件30的触点承载表面32延伸的高度HS(图1(a))的至少25%。例如,如果焊料10的高度为在微电子元件30的表面上方100微米,导电柱可穿入焊料10至少25微米。
与在先技术中的微电子封装相比,由于导电柱40的基本刚性的尖锐边缘46(图1和图2),使导电柱40穿透底充胶60及使焊料10变形和/或穿入焊料10成为可能。导电柱40的结构使它们能刺穿或冲过底充胶60,即使没有嵌入焊料10内也至少使焊料10变形。一旦导电柱穿过底充胶并至少使焊料10的一部分变形后,底充胶60可与微电子元件的触点承载表面32及介电元件50的顶面52都接触。在替代实施例中,为使逐渐嵌入底充胶60与焊料10内,介电元件50可朝微电子元件30移动,或微电子元件30和介电元件50可同时朝着对方移动。
现在参照图1(f),在焊料10和导电柱40接合在一起后,整个微电子封装100可加热至回流温度,使得焊料可围绕导电柱40的边缘流动,以形成导电支柱90。在示例性的实施例中,焊料将润湿导电柱高度Hc/2,亦即导电柱总高度HC的至少50%。在特定实施例中,焊料可覆盖柱并至介电元件的暴露表面52,或可覆盖导电柱40在其高度Hc/2与介电元件50顶面52的邻近柱部分之间的任意部分。
如图所示,导电柱40的高度Hc、焊料支柱10A的高度Hsolder及结合垫20,都可构成微电子元件的触点承载表面32与介电元件50的顶面52之间的间隔距离X的一部分。在示例性的实施例中,导电柱40的高度Hc为介电元件50的顶面52与微电子元件的触点承载表面32之间的间隔距离X的至少百分之四十(40%)。在一个示例中,距离X可为25至100微米,导电柱40具有至少10微米的高度Hc。可以理解的是,距离X可取自设置在微电子元件的触点承载表面32上的元件的暴露顶面与设置在介电元件顶面上的元件的顶面之间的距离,各元件如焊料掩模、粘接层、或覆盖介电元件暴露表面或微电子元件的触点承载表面32的任意其他材料。
参照图2A,示出了图1(f)中一个导电柱顶端的放大示意图。如夸大的细节中所示,在焊料10与导电柱之间的接合点,焊料10内存在底充胶60的残渣62。当导电柱40和/或焊料10彼此朝着对方施压时,焊料10内可存在或混入底充胶60的残渣62。返回参照图1(d),当导电柱40与焊料10彼此相对并置时,底充胶60的一部分P位于焊料10与导电柱40的顶端42之间。当介电元件50与微电子元件30移动并相互靠近(图1(d)和图1(e))时,导电柱40逐渐嵌入焊料10内,位于焊料10与导电柱40之间的底充胶60的残渣(未示出),也将嵌入焊料10内。实际上,导电柱40可能把底充胶60推入焊料10内。这些残渣部分62将出现在导电柱40与焊料10之间的接合点。
可以理解的是,图1的实施例可以做出许多修改,其中一些将在本文更详细地描述。例如,与设置在介电元件50上相对比,底充胶60可沉积在微电子元件30的顶面32上(图4),或底充胶可在微电子元件30及介电元件50上都沉积(图8)。替代地,可在介电元件50上沉积焊料掩模(图3(a))或可涂敷导电柱40,从而限制与介电元件50或微电子元件30的表面直接接触的底充胶60及焊料10的量(图8)。焊料掩模或涂层还可防止底充胶60与从微电子元件30的表面32或从介电元件50的表面52延伸的导电柱的边缘接触。焊料或其他结合金属10不是直接放置在结合垫20上,焊料可替代地直接放置在导电柱40中一个或多个的顶端42上(图6)。
现在参照图3,示出了制造微电子封装300(图3(f))的方法的替代实施例。该实施例与图2所示实施例类似,且经历相同步骤,从其上具有结合金属10的微电子元件330(图3(a))及其上具有柱340的介电元件350(图3(b))而开始。权利要求3的方法的不同点仅在于,焊料掩模370(图3(b))设置在介电元件350的主表面352上,影响与导电柱340和介电元件350的表面352直接接触的底充胶360及焊料310的多少。在图3(b)所示的示例中,焊料掩模370可横置在介电元件350的顶面352上,使得焊料掩模370与导电柱340的侧面边缘344接触。替代地,焊料掩模可与导电柱340'的边缘344'间隔一定距离,从而在焊料掩模370的边缘374与导电柱340'的边缘344'之间具有间隙G。
如图3(c)所示,底充胶360可以在焊料掩模370的暴露顶面372上方流动。因为焊料掩模370沉积在介电元件350上,底充胶360将不与导电柱340的底部或基部346的边缘表面344接触。因此,底充胶360可覆盖并接触导电柱的顶端342、及导电柱仍暴露的从焊料掩模370向上延伸的边缘表面344。
如图3(e)所示,在介电元件350和微电子元件330接合在一起(图3(d))后,当微电子元件330朝着介电元件350上的导电柱340的顶端342移动时,堆积在微电子元件330的结合垫320上的焊料310可因导电柱而变形,或导电柱340可逐渐嵌入焊料内。一旦导电柱340的顶端342使焊料310变形、或逐渐嵌入焊料310内后,可使封装300回流。在所示的示例中,焊料掩模370防止焊料310润湿导电柱340与焊料掩模370直接接触的基部346的边缘。只有导电柱340的在焊料掩模370的表面372上方延伸的暴露部分被焊料310润湿。
现在参照图3(f),在焊料10和导电柱340接合在一起后,整个微电子封装300可加热至回流温度,使得焊料310可沿导电柱340的边缘流动,以形成导电支柱390。如图所示,因为焊料掩模370沉积为与导电柱340的基部346的边缘344邻接,焊料310将只沿导电柱340的从焊料掩模370的表面372向外延伸且在表面372上方暴露的那部分边缘流动并与其接触。相反地,当焊料掩模370与导电柱340'的边缘不接触时,焊料310可回流至导电柱340'的基部或与介电元件350的顶面邻接。
参照图3(g),与先前实施例类似,导电柱40的高度HP为从焊料掩模370的顶面372至导电柱340的顶面而测量。高度HP可为微电子元件330的顶面332与焊料掩模370的暴露顶面372之间的间隔距离X的至少百分至四十(40%)。在一个示例中,间隔距离X可为25至100微米,导电柱40具有至少为10微米的高度。
仍参照图3(g),一旦封装300完成后,其可与电路面板390或电路板电连接。介电元件350上的端子345与在表面352暴露的柱340或其他导电元件电连接。如图所示,焊料球362可用于使端子345与电路板上的接触垫355连接。取代焊料球362的使用,任意其他常规的使微电子封装300与电路板390导电连接的方式都可采用,如导电引脚、导电材料的其他形式、或类似物。可以理解的是,微电子封装300可与任意其他形式的外部元件或器件电连接。
在图4(a)至图4(f)中,示出了根据本发明另一替代实施例的微电子封装400(图4(f))。除了如图4(c)所示,底充胶460可替代地设置在微电子元件430的顶面432上,且可不在介电元件450的顶面452上设置以外,该实施例与参照图1至图2所描述的方法类似。参照图4(d),一旦微电子元件430上的焊料410与导电柱440彼此相对并置及相互移动并靠近在一起后,导电柱440的顶端442开始穿过底充胶460。在一个实施例中,在这个步骤中,底充胶460将从微电子元件430的触点承载表面432延伸并与导电柱440接触。
然后,微电子元件430和介电元件450中一个或二者可朝着对方移动,使得导电柱440可冲过底充胶60,即使还没有嵌入焊料410内,至少使焊料410变形。在所示的实施例中,柱的顶端442只在焊料410内延伸距离D,该距离为焊料410与导电垫420总高度HS的至少25%。此后,封装400可回流,使得焊料410沿导电柱440的暴露边缘流动。如图所示,因为导电柱440上没有防止焊料润湿柱的焊料掩模或其他涂层,焊料410沿导电柱440流动,且可形成从微电子元件的结合垫420延伸至导电柱440基部446的导电支柱490,导电柱440从介电元件450向上延伸。
现在参照图5,示出了图1(a)至图1(f)的替代实施例。该实施例与图1(a)至图1(f)的实施例类似,不同点在于,与远离介电元件550的表面552而延伸相对比,在最初的元器件(图5(a))中,导电柱540远离微电子元件530的触点承载表面532而延伸。类似地,焊料510可从在介电元件550(图5(b))的顶面552暴露的结合垫520延伸,而不是先前实施例中的从微电子元件530延伸。
为了便于参照,在本文中声明的方向是参照半导体芯片的“顶面”、即触点承载表面532的。总体上,称为“向上”、“上升”或“从……延伸”的方向,指的是垂直于微电子元件顶面532并远离该顶面的方向。称为“向下”的方向,指的是垂直于元件顶面532且与向上方向相反的方向。“垂直”方向指的是垂直于芯片顶面的方向。术语“高于”参照点指的是点在参照点上方,术语“低于”参照点指的是点在参照点下方。可以进一步理解的是,类似的标号将用于描述类似的元件。
该方法的步骤与本文先前描述的类似。参照图5(c),底充胶560可设置在结合金属上方,例如从介电元件550延伸的焊料510的上方。在该实施例中,底充胶560还覆盖焊料510的整个表面514。转向图5(d),导电柱540可与焊料510并置,使得导电柱540能嵌入底充胶560内或穿过底充胶。如图5(e)所示及如先前实施例中所述,导电柱540的顶端542穿入焊料510而延伸。一旦回流时,底充胶560可与导电柱540的暴露边缘544接触。与上述参照图1(f)所描述的实施例类似,焊料可沿微电子元件顶面532上柱的高度HC的一部分或整个高度与柱接触。在示例性的实施例中,焊料可沿表面532上柱的至少一半的高度与柱接触。如图5(f)中特别地示出的,在一个实施例中,当没有防止焊料润湿导电柱540任何部分的焊料掩模和/或涂敷在导电柱上的其他材料时,焊料的导电支柱590可从微电子元件530的触点承载表面532延伸至介电元件550的表面552上暴露的触点520。
现在参照图6,示出了根据本发明的制造微电子封装600(图6(e))的另一方法。该方法与本文先前描述的类似,但不同点在于,导电柱640A(图6(a))从微电子元件630延伸,而导电柱640B(图6(b))也从介电元件650延伸。此外,焊料610可直接堆积在导电柱640A的顶端642上,且焊料掩模680可设置为与导电柱640A邻接。例如,氮化硅的暴露层可用作掩模680,以避免微电子元件630的表面632被如焊料等的结合金属润湿。
如图6(c)所示,底充胶660沉积在从介电元件650的顶面652延伸的导电柱640的上方。然后导电柱640A和导电柱640B可彼此相对并置(图6(d))。导电柱640A的顶端642、及顶端642上的焊料610,可压至底充胶660内,使得顶端642及其上的焊料610可延伸至底充胶660的至少一部分内。可继续向介电元件650及微电子元件630一起施压(或一个压向另一个),直至顶端642B能穿入焊料610的至少一部分内,使得焊料610(图1(e))最初高度HS的至少25%被导电柱640B穿过(图6(e))。此后,封装可回流,以使堆积在导电柱640A顶端642A的焊料610流动并润湿导电柱640A及640B的边缘(图6(f))。在该实施例中,如图6(f)所示,因为在导电柱640A的顶端642A上只堆积了有限量的焊料610,焊料610可能不完全润湿导电柱640A的边缘644A及导电柱640B的边缘644B。如图所示,导电柱640B的基部646可能仍然暴露、并能与底充胶660直接接触。
现在参照图7,示出了图6的替代方法。在该实施例中,介电元件750也支撑柱740B。但是,与图6的实施例相比,没有沿微电子元件630的长度延伸的焊料掩模(图7(a))。底充胶760沉积在微电子元件730的触点承载表面732的暴露部分、及导电柱740A的没有被焊料710覆盖的暴露部分上。在所示的实施例中,底充胶优选地越过每个导电柱740A的外边缘而延伸(图7(c))。可以理解的是,在替代实施例中,焊料可替代地放置在从介电元件750延伸的导电柱上。
现在转向图7(d),导电柱740A与从其延伸的焊料710、及从介电元件750延伸的导电柱740B彼此相对并置。介电元件750和微电子元件730可压在一起,使得导电柱740B进入底充胶760内。
进一步如图7(e)中可以看出的,一旦导电柱740B穿过底充胶760后,介电元件750与微电子元件730可继续压缩,直至导电柱740B嵌入焊料内,焊料暴露在从微电子元件730延伸的导电柱740A的导电顶端742A。然后封装可回流,使得焊料710润湿导电柱740A和740B的暴露表面的边缘(图7(f))。
现在参照图8,示出了根据本发明的另一微电子封装800(图8(e))。如图所示,微电子封装包括具有大致相同长度的两个介电元件850A(图8(a))和850B(图8(b))。参照图8(c1)和图8(c2),底充胶层可沉积在介电元件850A的顶面852A和介电元件850B的顶面852B上方。介电元件850B可包括远离介电元件850的顶面852B延伸的导电柱840。导电柱840的基部846可涂敷如焊料掩模材料等的材料、或能有助于防止焊料或其他材料润湿导电柱的任意无机或有机材料。
如图8(d)所示,导电柱840可与从介电元件850A延伸的焊料810并置。参照图8(e),可继续移动介电元件850A和850B而靠近在一起,以使导电柱840与焊料810接触。在该实施例中,导电柱840没有刺穿或穿过焊料810。如图所示,导电柱840只使从介电元件850A延伸的焊料810变形。转至图8(f),一旦封装回流,焊料810将沿导电柱840的边缘流动,除了涂敷有防止润湿导电柱840基部846的材料848的地方以外。
参照图9,示出了另一替代微电子封装900。该实施例与先前制造微电子封装的方法类似,不同点仅在于,导电元件(即导电柱940、焊料910、导电柱920)是由相应微电子元件930A、930B支撑的,并没有从介电元件延伸的导电元件。底充胶960在两个微电子元件930A、930B之间密封封装的内部。
参照图10,示出了微电子组件的另一替代部分。图10为图1(f)的一部分的替代视图,示出导电垫1023可设置在第一介电元件1050上或其内。介电层1051可形成在介电元件1050上,且可在介电层内形成开口1056。导电柱1042可通过开口电镀并形成柱而形成,或替代地,在介电层1051上及开口1056内沉积连续的金属层,然后蚀刻连续金属层而形成所需大小和形状的柱。
上述的各种微电子组件可在不同的电子系统的构造中利用。例如,如图11所示,根据本发明另一实施例的系统1900包括如上文所述微电子组件的先前实施例中的结构1906与其他电子元器件1908和1910联合。在描述的示例中,元器件1908为半导体芯片,而元器件1910为显示屏,但任意其他元器件都可使用。当然,尽管为清楚图示起见,在图11中只描述了两个附加元器件,系统可包括任意数量的这种元器件。如上文所述的结构1906可为,例如,复合芯片或包含复数个芯片的结构。在另一变例中,二者都可提供,且任意数量的这种结构都可应用。结构1906和元器件1908、1910都安装至以虚线示意性地描述的共同外壳1901内,且必要时彼此电互连以形成所需的电路。在所示的示例性系统中,系统包括如柔性印刷电路板等的电路板1902,且电路板包括使元器件之间彼此互连的大量导电体1904,其中在图25中只示出了一个导电体。但是,这只是示例,任意适当的用于形成电连接的结构都可应用。外壳1901作为便携式外壳而描述,具有用于如移动电话或个人数字助理等的类型,显示屏1910暴露在外壳的表面。其中结构1906包括如成像芯片等的光敏元件,还可配置镜头1911或其他光学器件,以提供光到达该结构的路线。同样,图11内所示的简化系统只是示例,其他系统,包括一般被视为固定结构的系统,如台式计算机、路由器及类似的结构,都可应用上述的结构而制成。
尽管本发明参照特定实施例进行描述,可以理解的是,这些实施例只是说明本发明的原理和应用。因此,应理解为,在不偏离由附加的权利要求书所限定的本发明实质和范围的情况下,说明的实施例可做出许多修改及可设计出其他布置。
Claims (36)
1.用于制造微电子组件的方法,包括:
提供微电子元件和介电元件,所述微电子元件具有第一表面和在所述第一表面上方突出的第一导电元件,所述介电元件具有第二表面和在所述第二表面上方突出的第二导电元件,至少一些第一导电元件或至少一些第二导电元件为刚性的导电柱,其他的第一导电元件或第二导电元件包括与至少一些导电柱并置的结合金属,这些导电柱具有在其突出的相应表面上方的高度,底充胶层覆盖至少一些的所述第一导电元件或至少一些的所述第二导电元件,所述导电柱包括具有共面表面的顶端;
使所述第一导电元件中至少一个朝所述第二导电元件中另一个移动,使得刚性的导电柱的所述顶端刺穿所述底充胶层,并至少使所述结合金属变形;及
加热所述微电子元件和所述介电元件至接合温度,直至所述结合金属沿所述导电柱的边缘流动,并沿所述导电柱的所述高度的至少一半与所述边缘接触,及使所述微电子元件与所述介电元件电接合,
其中所述导电柱在其突出的相应表面上方的所述高度,至少为所述第一表面与所述第二表面之间距离的百分之四十;
其中在使所述结合金属变形的步骤之前,微量的所述底充胶层被所述导电柱推入所述结合金属内。
2.根据权利要求1所述的方法,其中所述导电柱为蚀刻形成的导电柱。
3.根据权利要求2所述的方法,其中所述第一导电元件和所述第二导电元件都为刚性的导电柱。
4.根据权利要求2所述的方法,其中所述第一导电元件的顶端和所述第二导电元件的顶端共面。
5.根据权利要求1所述的方法,其中所述第一导电元件包括所述结合金属,且所述至少一些导电柱为所述介电元件的第二导电元件。
6.根据权利要求1所述的方法,其中所述至少一些导电柱为所述微电子元件的第一导电元件,且所述第二导电元件包括所述结合金属。
7.根据权利要求1所述的方法,其中使所述第一导电元件中至少一个朝所述第二导电元件中另一个移动的步骤包括,所述刚性的导电柱剌穿所述结合金属。
8.根据权利要求1所述的方法,其中使所述第一导电柱中至少一个朝所述第二导电元件中另一个移动的步骤包括,穿过所述结合金属的深度为,所述第一表面或所述第二表面中相应一个上方的焊料高度的至少25%。
9.根据权利要求1所述的方法,其中所述第一导电元件中至少一些为刚性的导电柱。
10.根据权利要求1所述的方法,其中所述第一导电元件中至少一些为导电垫。
11.根据权利要求1所述的方法,其中所述第二导电元件中至少一些为刚性的导电柱。
12.根据权利要求1所述的方法,其中所述第二导电元件中至少一些为导电垫。
13.根据权利要求1所述的方法,其中所述底充胶覆盖所述第一导电元件。
14.根据权利要求1所述的方法,其中所述底充胶覆盖所述第二导电元件。
15.根据权利要求1所述的方法,其中所述底充胶覆盖所述第一导电元件及所述第二导电元件。
16.根据权利要求1所述的方法,其中所述第二导电元件中至少一些为刚性的导电柱,所述提供步骤包括,在所述刚性的导电柱中至少一些上提供结合金属。
17.根据权利要求1所述的方法,其中所述第一导电元件中至少一些为接触垫,所述提供步骤包括,在所述接触垫中至少一些上提供结合金属。
18.根据权利要求2所述的方法,其中所述第一导电元件中至少一些为刚性的导电柱,且所述第二导电元件中至少一些为刚性的导电柱。
19.微电子组件,包括:
第一元器件,具有第一表面和在第一表面上方突出的第一导电元件;
第二元器件,具有第二表面和在第二表面上方突出的第二导电元件,
所述第一元器件或所述第二元器件中至少一个为微电子元件,至少一些第一导电元件或至少一些第二导电元件为刚性的导电柱,所述导电柱具有在所述导电柱从其上突出的相应表面上方的高度,所述刚性的导电柱具有共面的表面,
结合金属,设置在各成对导电元件之间,所述成对导电元件中每个都包括至少一个导电柱和与该至少一个导电柱面对的至少一个第一导电元件或第二导电元件,所述结合金属沿所述导电柱的所述高度的至少一半与所述导电柱的边缘接触;及
底充胶层,与所述第一元器件的所述第一表面及所述第二元器件的所述第二表面接触并结合,其中在所述导电柱中至少一些与结合金属之间的至少一个界面处,存在所述底充胶层的残渣,或在所述结合金属内存在所述底充胶层的残渣。
20.根据权利要求19所述的微电子组件,其中所述第一元器件为微电子元件,且所述第二元器件为介电元件。
21.根据权利要求20所述的微电子组件,其中所述微电子元件为芯片。
22.根据权利要求19所述的微电子组件,其中所述第一元器件为介电元件。
23.根据权利要求19所述的微电子组件,其中所述第一元器件和所述第二元器件都为微电子元件。
24.根据权利要求19所述的微电子组件,其中所述第一导电元件为导电柱。
25.根据权利要求19所述的微电子组件,其中所述第二导电元件为导电柱。
26.根据权利要求19所述的微电子组件,其中所述第一导电元件和所述第二导电元件都为导电柱。
27.根据权利要求20所述的微电子组件,其中结合金属堆积在所述导电柱中至少一个上。
28.根据权利要求22所述的微电子组件,其中结合金属堆积在所述导电柱中至少一个上。
29.根据权利要求23所述的微电子组件,其中结合金属堆积在所述导电柱中至少一个上。
30.根据权利要求19所述的微电子组件,其中焊料掩模设置为与所述导电柱邻接。
31.根据权利要求19所述的微电子组件,其中所述导电柱的至少一部分涂敷有抵抗结合金属的材料。
32.根据权利要求19所述的微电子组件,其中所述结合金属覆盖所述导电柱中至少一个的一半或小于一半的高度。
33.根据权利要求20所述的微电子组件,其中所述第二导电元件为导电柱。
34.根据权利要求23所述的微电子组件,其中所述第二导电元件为导电柱。
35.系统,包括根据权利要求19所述的微电子组件以及一个或多个与所述微电子组件电连接的其他电子元器件。
36.根据权利要求35所述的系统,进一步包括外壳,所述微电子组件和所述其他电子元器件安装于所述外壳。
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