CN103270489B - For carrying out system, the apparatus and method of segment register read and write and no matter prerogative grade - Google Patents
For carrying out system, the apparatus and method of segment register read and write and no matter prerogative grade Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/30032—Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/30101—Special purpose registers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
- G06F9/342—Extension of operand address space
Abstract
Describe and read or write the system of instruction, the embodiment of apparatus and method for performing franchise unknowable segment base register.Illustrative methods can comprise the franchise unknowable segment base register write command of acquisition, wherein this franchise unknowable write command comprises 64 bit data source operand, obtained privilege unknowable segment base register write command is decoded, and the privilege unknowable segment base register write command performed through decoding is so that by the segment base register of the operational code mark of 64 bit data writes franchise unknowable segment base register write command by this of source operand.
Description
Invention field
Field of the present invention relates generally to computer processor framework, particularly relates to the instruction producing particular result when being performed.
Background
Many modern processors have different prerogative grades, these prerogative grades determine what can with can not be performed by special entity.By prerogative grade, different rings is divided into this usual view.As shown in Figure 1, ring 0 is most highly privileged grade, and therefore at ring 0(prerogative grade 0 or kernel mode) in the program run can do anything by system, and at ring 3(user model) in the code that runs there is less privilege, and therefore its limited ability.This franchise separating needle is applied protection ring 3 to another ring 3 and is applied, and applies protection ring 0 kernel for ring 3.Ring 3 is applied and should be lost efficacy at any time when all the other application not affecting computer system, because keep the mission critical of computer run to apply available to ring 0 kernel instead of ring 3.Ring 1 and ring 2 more more limited than ring 0, but less more limited than ring 3.
These grades provide for software the accident of system environments (and security of system branch of correspondence) or the hardware protection that sabotages." trusted " of system software part is only had to be allowed to perform in the not constrained environment of kernel mode, and only just like this when imperative.Every other software performs in one or more user model.
Accompanying drawing is sketched
The present invention is described by way of example and not limitation of, wherein same tag instruction similar elements in each figure of accompanying drawing, and wherein:
Fig. 1 shows common prerogative grade framework.
Fig. 2 shows the embodiment arranging the method supporting instruction.
Fig. 3 shows the embodiment of the method for segment base register read/write.
Fig. 4 shows the embodiment of the method processing franchise unknowable segment base register write command.
Fig. 5 shows the embodiment of the method processing franchise unknowable segment base register read instructions.
Fig. 6 is the block diagram of the exemplary unordered core framework illustrated according to various embodiments of the present invention.
Fig. 7 shows the block diagram of system according to an embodiment of the invention.
Fig. 8 shows the block diagram of second system according to an embodiment of the invention.
Fig. 9 shows the block diagram of the 3rd system according to an embodiment of the invention.
Describe in detail
In the following description, set forth multiple detail.But, should be appreciated that embodiments of the invention can be put into practice when not having these details.In other instances, known circuit, structure and technology are not shown in detail in order to avoid obscure the understanding to this description.
Special characteristic, structure or characteristic can be comprised to the embodiment quoted described by expression of " embodiment ", " embodiment ", " example embodiment " etc. in instructions, but, each embodiment can not necessarily comprise this special characteristic, structure, or feature.In addition, such phrase not necessarily refers to same embodiment.In addition, when describing special characteristic, structure or characteristic in conjunction with the embodiments, think and those skilled in the art will know that other embodiment that no matter whether combination obviously describe is to realize these features, structure or characteristic.
Now, even if be not whole, most of OS supports the multiple execution threads in individual address space.Thread specific information in processor, CPU or core is called as thread context.Operating system is responsible for guaranteeing before active thread, this particular CPU to exist correct thread context on a CPU.When operating system switch threads context is as when being switched to another thread a part of from a thread, this is commonly called contextual processing.Operating system is also provided for providing certain mechanism of the execution thread specific store being called as thread specific store.On x86 processor, use FS and/or GS segment register provides the access to thread specific store.By using segment register, each thread can both use same section and skew when visit data, but access is unique data set to this thread.This normally many IA32 and Intel
the sole purpose of the non-maximum restriction section based on non-zero in 64 bit manipulation systems or its equivalent.Segment descriptor is a part for thread context and must carries out contextual processing together with the remainder of thread context.Identical ring 0 or kernel address space is shared in much operating system all threads in systems in which.These operating systems are usually by the thread specific store being used for kernel different for the thread specific store had from be used for ring 3 or user model.In kernel, in fact thread specific store will be logic processor specific store, and will comprise the information unique to this processor.These operating systems must change segment descriptor when ring is changed and revise these segment descriptors and use in the personal code work in context swap code.
When introducing 64 variant (Intel of x86 framework
64) time, except FS and GS segment register, from 64 bit patterns, segmentation is removed.Segment descriptor is not enhanced to support larger address space.These segment descriptors are left as 8 byte descriptors and only support 32 plots.Virtual address space is divided into kernel address space above and user address space below by much operating system.In addition, core logic processor exclusive data needs in kernel address space, and thread exclusive data needs in user address space.Even if user and kernel address space are reversed, also cannot realize with 32 plots.In order to allow these sections to be placed on any position, 48 virtual address spaces supported in 64 bit patterns need a kind of Exchange rings.The mechanism realized is to provide two MSR of the plot of the mapping pair section of answering, i.e. IA32_FS_BASEMSR (C0000100H) and IA32-GS_BASEMSR (C0000101H).The plot of section is by writing these MSR simply to change.RDMSR and WRMSR is the privileged instruction allowing write 64, unavailable to user class code.SWAPGS instruction also simplify ring conversion time kernel mode and user model GS section between switching.Instruction RDMSR, WRMSR and SWAPGS are limited to ring 0 or kernel mode is vital MSR to guarantee that ring 3 application cannot be handled the operation of whole operating system.Above-mentioned instruction is limited to ring 0, and this is true, and the ability that ring 3 is applied is limited to amendment FS and GS section by this restriction artificially.Therefore, for current I A system, application is limited to carry out system call or change segment descriptor to switch FS or GS plot.System call is slowly, because it relates to ring conversion, and because segment descriptor only preserves 32 segment bases (as mentioned above), therefore the value of these two segment bases is limited to the very little part in the available address space in the system of minimum 4GB(64 position) and the sum of segment descriptor is limited to is less than 8K.Traditional x86 processor also comprises two system table registers, i.e. GDTR (GDTR) and LDTR (LDTR).These two registers all store 32 or 64 bit linear plots.
For the thread only making a small amount of work between contextual processing, system call, contextual processing and to return to user mode code follow-up be often the major part of the work that this thread completes when its each run.A kind of possible solution for this problem is user mode threads, and the contextual processing between its thread completes in user mode code.Each in these user mode threads needs its oneself unique thread specific store copy.When there is no its oneself unique copy, user mode threads must be limited to single OS thread (thread specific store can not follow them when they move between OS thread), and then there is the problem of the ignorant each other multiple entity using same storage.
In most of existing system, it is very expensive for being switched to " kernel mode " from " user model ".Thus, the above-mentioned reading from segment register/to the mode of the write of segment register be undesirable.What below describe in detail is the embodiment of the system, architecture etc. of the instruction that can be used for performing for carrying out read and write and current privilege no matter in 64 bit patterns to segment base registers such as such as IA32_GS_BASE or IA32_FS_BASE.These instructions can be parts for prerogative grade 3 program.
The example of the unknowable write command of privilege is " WRGSBASERAX ", and wherein " RAX " is register or the memory operand of 64 bit data value comprised being written into GS segment base register.WRGSBASE is operational code and identifies IA32_GS_BASE register.The execution of this instruction is by the data of RAX register write GS segment base register.Similarly, WRFSBASERAX is by the instruction of the data of RAX write FS segment register (IA32_FS_BASE) when being performed.
The unknowable example reading instruction of privilege is " RDGSBASERAX ", and wherein " RAX " will store from the register of 64 bit data of GS segment base register read or memory operand.RDGSBASE is operational code and identifies IA32_GS_BASE register.The execution of this instruction causes the value of GS segment base register to read in RAX register.Similarly, RDFSBASERAX reads its data when being performed from FS segment base register (IA32_FS_BASE) and these data is stored in the instruction RAX.
In certain embodiments, before the franchise unknowable segment base register read/write instruction of execution, one in operating system, processor or chipset arranges the instruction that this processor can support this instruction.The embodiment arranging the method for this instruction is shown in FIG. 2.
Determine whether the logic processor of processor supports the execution of following operation 201: from the one or more reading processor segment base register and/or to one or more writes 64 place value in processor segment base register no matter prerogative grade.Usually, the CPUID characteristic indication that this judgement exists support by the instruction of examine processor has come.
If there is no support, then use from segment base register read/to the more efficient means of segment base register write 203.Support if existed, then instruction at least one mark to the support of the instruction of these types is set in control register.Such as, in certain embodiments, control register 4 has the mark for this instruction is arranged.Certainly, other registers also can be used for this object.
Fig. 3 shows the embodiment of the method for segment base register read/write.301, determine whether to enable franchise unknowable base register read/write instruction.Such as, if use the control register such as control register 4 grade in such as x86 framework, then check what respective flag supports to check.If support franchise unknowable segment base register read/write instruction, then will process these instructions 313 when such as obtaining these instructions.
If do not support franchise unknowable segment base register read/write instruction, then determine whether the prerogative grade residing for logic processor is prerogative grade 0 303.As above described in detail, prerogative grade 0 mean for can run what have seldom (if any) restriction.If this is prerogative grade, then 305, to carry out reading from IA32_GS_BASE or IA32_FS_BASE by using corresponding RDMSR or WRMSR privileged instruction/carry out writing to upgrade GS and FS plot 64 bit patterns to IA32_GS_BASE or IA32_FS_BASE.
If prerogative grade is higher than 0, then proceed to the switching of prerogative grade 0 307.Once in prerogative grade 0, then 309, to carry out reading from IA32_GS_BASE or IA32_FS_BASE by using corresponding RDMSR or WRMSR privileged instruction/carry out writing to upgrade GS and FS plot 64 bit patterns to IA32_GS_BASE or IA32_FS_BASE.After carrying out this action, make 311 the switching getting back to previous prerogative grade.Certainly, lower performance penalties is which increased.
Fig. 4 shows the embodiment of the method processing franchise unknowable segment base register write command.Before arbitrary step of this illustrative methods, may there is the judgement supporting instruction.401, receive franchise unknowable segment base register write command.This instruction comprises the operand of 64 bit data comprised being written into segment base register (such as, IA32_GS_BASE or IA32_FS_BASE).This operand can be memory location or register, but more typically register.
The unknowable segment base register write command of privilege is carried out decoding and at 405 search operaqtion logarithmic datas 403 by decode logic.Such as, if operand is the register of such as RAX and so on, then the data from register are retrieved.
The unknowable segment base register write command of privilege performs 407 to make the data retrieved write suitable segment base register, and regardless of current privilege.
Fig. 5 shows the embodiment of the method processing franchise unknowable this register read instructions of segment base.Before arbitrary step of this illustrative methods, there is the judgement supporting instruction.501, receive franchise unknowable segment register and read instruction.This instruction comprises mark and will store from section MSR(such as, IA32_GS_BASE or IA32_FS_BASE) operand of the position of 64 bit data that reads.This operand can be memory location or register.
The unknowable segment base register read instructions of privilege is decoded 503 by decode logic.Such as, if operand is the registers such as such as RAX, then the data from register are retrieved.
The unknowable segment base register read instructions of privilege performs to cause reading the data in suitable segment base register 505, and regardless of prerogative grade.507, then these data are stored in the position of operand definition.
Exemplary computer system and processor
Below describe in detail and can perform the device of above-mentioned instruction and the embodiment of system.Fig. 6 is the block diagram of the exemplary unordered core architecture illustrated according to various embodiments of the present invention.But above-mentioned instruction also can perform in orderly architecture.In figure 6, arrow indicates the coupling between two or more unit, and the direction of data stream between these unit of the direction of arrow.Assembly in this architecture can be used for the instruction processing above detailed description, comprises the acquisition of these instructions, decoding and execution.
Fig. 6 comprises the front end unit 605 being coupled to enforcement engine unit 610 and memory cell 615; Enforcement engine unit 610 is also coupled to memory cell 615.
Front end unit 605 comprises one-level (L1) inch prediction unit 620 being coupled to secondary (L2) inch prediction unit 622.These unit allow core to obtain and perform instruction and do not wait for that branch is resolved.L1 and L2 inch prediction unit 620 and 622 is coupled to L1 Instruction Cache Unit 624.L Instruction Cache Unit 624 preserves the instruction or one or more thread that may be performed by enforcement engine unit 610.
L1 Instruction Cache Unit 624 is coupled to instruction transformation look-aside buffer (ITLB) 626.ITLB626 is coupled to instruction acquisition and pre-decode unit 628, and byte stream is divided into discrete instruction by this instruction acquisition and pre-decode unit 628.
Instruction acquisition and pre-decode unit 628 are coupled to instruction queue unit 630 to store these instructions.Decoding unit 632 decoding comprises the queued instructions of above-mentioned instruction.In certain embodiments, decoding unit 632 comprises complex decoder unit 634 and three simple decoder elements 636,638 and 640.Simple demoder can process great majority (if not all) x86 instruction, and it is decoded into single micro-order.Complex decoder decodable code is mapped to the instruction of multiple micro-order.Decoding unit 632 also can comprise microcode ROM cell 642.
L1 Instruction Cache Unit 624 is also coupled to the L2 cache element 648 in memory cell 615.Instruction TLB unit 626 is also coupled to the secondary TLB unit 646 in memory cell 615.Decoding unit 632, microcode ROM cell 642 and circulation detector (LSD) unit 644 are coupled to the rename/dispenser unit 656 in enforcement engine unit 610 separately.LSD unit 644 detects the ring in when executive software, stops the stream instruction of predicted branches (and may last branch of the incorrect prediction loop) and its outside.In certain embodiments, LSD644 high-speed cache microoperation.
Enforcement engine unit 610 comprises the rename/dispenser unit 656 being coupled to retired unit 674 and United Dispatching device unit 658.Rename/dispenser unit 656 was determined resource requirement and is distributed available resources for performing before any register renaming.Logic register is also renamed to the physical register of physical register file by this unit.
Retired unit 674 is also coupled to performance element 660 and comprises resequencing buffer unit 678.This unit makes instruction retired when instruction completes.
United Dispatching device unit 658 is also coupled to physical register file unit 676, and physical register file unit 676 is coupled to performance element 660.Be shared between the different threads that this scheduler runs on a processor.
Physical register file unit 676 comprises MSR unit 677A, flating point register unit 677B and integer registers unit 677C, and unshowned adjunct register file (such as, being aliasing in the scalar floating point stack register file that MMX packs on integer plane registers device file 550) can be comprised.MSR unit comprises IA32_GS_BASE and IA32_FS_BASE register.
Performance element 660 comprises three mixing scalar sum SIMD performance elements 662,664 and 672; Load unit 666; Memory address unit 668; Storage data units 670.Load unit 666, memory address unit 668 and storage data units 670 perform load/store and storage operation, and are coupled to the TLB unit 652 in memory cell 615 further separately.
Memory cell 615 comprises the secondary TLB unit 646 being coupled to data TLB unit 6452.Data TLB unit 652 is coupled to L1 data cache unit 654.L1 data cache unit 654 is also coupled to L2 cache element 648.In certain embodiments, L2 cache element 648 is also coupled to the inner and/or outside L3 of memory cell 615 and more senior cache element 650.
It is below the example system being applicable to perform instruction detailed in this article.For laptop computer, desktop computer, Hand held PC, personal digital assistant, engineer work station, server, the network equipment, hub, interchanger, flush bonding processor, digital signal processor (DSP), graphics device, video game device, Set Top Box, microcontroller, cell phone, portable electronic device, handheld device and other electronic equipment various, other system known in the art and configuration are also applicable.Generally speaking, disclosed herein various can the system of merging treatment device and/or other actuating logic or electronic equipment be generally applicable.
With reference now to Fig. 7, the block diagram of system 700 according to an embodiment of the invention that shown is.System 700 can comprise the one or more treatment elements 710,715 being coupled to Graphics Memory Controller maincenter (GMCH) 720.Optionally representing by a dotted line in the figure 7 of additional treatment element 715.
Each treatment element can be monokaryon, or alternately comprises multinuclear.Treatment element optionally comprises element on other sheet except process core, such as integrated memory controller and/or integrated I/O steering logic.In addition, at least one embodiment, (multiple) for the treatment of element endorse multithreading, because they comprise more than one hardware thread contexts to each endorsing.
Fig. 7 illustrates that GMCH720 can be coupled to storer 740, and this storer 740 can be such as dynamic RAM (DRAM).For at least one embodiment, DRAM can be associated with non-volatile cache.
GMCH720 can be a part for chipset or chipset.GMCH720 can communicate with (multiple) processor 710,715, and mutual between control processor 710,715 and storer 740.GMCH720 also can take on the accelerate bus interface between (multiple) processor 710,715 and other element of system 700.For at least one embodiment, GMCH720 communicates with (multiple) processor 710,715 via the multi-point bus of such as Front Side Bus (FSB) 795 and so on.
In addition, GMCH720 is coupled to display 745(such as flat-panel monitor).GMCH720 can comprise integrated graphics accelerator.GMCH720 is also coupled to I/O (I/O) controller maincenter (ICH) 750, and this I/O (I/O) controller maincenter (ICH) 750 can be used to various peripherals to be coupled to system 700.In the embodiment of Fig. 7, exemplarily show external graphics devices 760 and another peripherals 770, this external graphics devices 760 can be the discrete graphics device being coupled to ICH750.
Alternatively, additional or different treatment elements can also be there is in system 700.Such as, additional (multiple) treatment element 715 can comprise the Attached Processor identical with processor 710, with processor 710 foreign peoples or asymmetric additional (multiple) processor, accelerator (such as such as graphics accelerator or digital signal processing (DSP) unit), field programmable gate array or other treatment element any.According to the tolerance spectrum comprising architecture, microarchitecture, heat, power consumption features etc. advantage, between physical resource 710,715, there is various difference.These difference effectively can be shown as asymmetry between treatment element 710,715 and heterogeneity.For at least one embodiment, various treatment element 710,715 can reside in same die package.
Referring now to Fig. 8, the block diagram of shown is second system 800 according to an embodiment of the invention.As shown in Figure 8, multicomputer system 800 is point-to-point interconnection systems, and comprises the first treatment element 870 and the second treatment element 880 be coupled via point-to-point interconnection 850.As shown in Figure 8, each in treatment element 870 and 880 can be polycaryon processor, comprises the first and second processor cores (that is, processor core 874a and 874b and processor core 884a and 884b).
Alternatively, one or more in treatment element 870,880 can be elements in addition to processors, such as accelerator or field programmable gate array.
Although only illustrate with two treatment elements 870,880, scope of the present invention should be understood and be not limited thereto.In other embodiments, one or more additional processing elements can be there is in given processor.
First treatment element 870 also can comprise memory controller hub (MCH) 872 and point-to-point (P-P) interface 876 and 878.Similarly, the second treatment element 880 can comprise MCH882 and P-P interface 886 and 888.Processor 870,880 can exchange data via using point-to-point (PtP) interface 850 of point-to-point (PtP) interface circuit 878,888.As shown in Figure 8, processor is coupled to corresponding storer by MCH872 and 882, i.e. storer 842 and storer 844, and these storeies can be the primary memory parts that this locality is attached to respective processor.
Processor 870,880 can exchange data via the independent PtP interface 852,854 and chipset 890 that use point-to-point interface circuit 876,894,886,898 separately.Chipset 890 also can exchange data via high performance graphics interface 839 and high performance graphics circuit 838.Embodiments of the present invention can be placed in the random processor of the process core with arbitrary number, or are placed in each of PtP bus agent of Fig. 8.In one embodiment, random processor is endorsed and is comprised local cache memory (not shown) or be otherwise associated with local cache memory (not shown).In addition, share high-speed cache (not shown) can be included in the outside of these two processors but interconnect in arbitrary processor of being connected with these processors via p2p, if thus a processor is placed in low-power mode, then the local cache information of any one or these two processors can be stored in this high-speed cache shared.
First treatment element 870 and the second treatment element 880 can be coupled to chipset 890 via P-P interconnection 876,886 and 884 respectively.As shown in Figure 8, chipset 890 comprises P-P interface 894 and 898.In addition, chipset 890 comprises the interface 892 be coupled with high performance graphics engine 848 by chipset 890.In one embodiment, bus 849 can be used to graphics engine 848 to be coupled to chipset 890.Alternatively, point-to-point interconnection 849 can be coupled these parts.
Chipset 890 is coupled to the first bus 816 via interface 896 again.In one embodiment, the first bus 816 can be the bus of peripheral component interconnect (pci) bus or such as PCIExpress bus or another third generation I/O interconnect bus and so on, although scope of the present invention is not limited thereto.
As shown in Figure 8, various I/O equipment 814 can be coupled to the first bus 816 together with bus bridge 818, and the first bus 816 is coupled to the second bus 820 by bus bridge 818.In one embodiment, the second bus 820 can be low pin count (LPC) bus.Multiple equipment can be coupled to the second bus 820, and comprise such as keyboard/mouse 822, communication facilities 826 and data storage cell 828(such as disk drive or other mass-memory unit, it can comprise code 830 in one embodiment).In addition, audio frequency I/O824 can be coupled to the second bus 820.Note, other architecture is possible.Such as, replace the Peer to Peer Architecture of Fig. 8, system can implement multi-point bus or another this type of framework.
Referring now to Fig. 9, the block diagram of the 3rd system 900 that shown is according to the embodiment of the present invention.Similar elements in Fig. 8 and 9 uses same reference numerals, and some aspect eliminating Fig. 8 is in fig .9 with the other side of the Fig. 9 that avoids confusion.
Fig. 9 illustrates that treatment element 870,880 can comprise integrated memory and I/O steering logic (" CL ") 872 and 882 respectively.For at least one embodiment, CL872,882 can comprise the memory controller hub logic (MCH) such as described by above composition graphs 7 and 8.In addition, CL872,882 also can comprise I/O steering logic.Fig. 9 illustrates that not only storer 842,844 is coupled to CL872,882, and I/O equipment 914 is also coupled to steering logic 872,882.Conventional I/O equipment 915 is coupled to chipset 890.
The embodiment of mechanism disclosed herein can realize according to the combination of hardware, software, firmware or this type of implementation method.Embodiments of the invention can be implemented as and comprise the computer program that the programmable system of at least one processor, data storage system (comprising volatibility and nonvolatile memory and/or storage unit), at least one input equipment and at least one output device performs.
The program code of all codes 830 as shown in Figure 8 can be applied to input data to perform function described herein, and produce output information.According to known way, output information can be applied to one or more output device.In order to the object of this application, disposal system comprises any system of the processor such as with such as digital signal processor (DSP), microcontroller, special IC (ASIC) or microprocessor and so on.
Program can realize according to level process or OO high-level programming language, to communicate with disposal system.Program code also can realize according to compilation or machine language when needed.In fact, mechanism described herein is not limited to any certain programmed language in scope.Under any circumstance, this language can be compiling or interpretative code.
One or more aspects of at least one embodiment can be realized by the representative data stored on a machine-readable medium, various logic in this data representation processor, it makes this machine generate the logic performing technology described herein when being read by machine.These expressions being called as " IP kernel " can be stored on tangible machine readable media, and are provided to each client or production facility to be loaded in the manufacturing machine of this logical OR processor of actual manufacture.
This type of machinable medium can include but not limited to the tangible arrangements of the particle by machine or device fabrication or formation, comprises storage medium, such as: hard disk; Comprise floppy disk, CD, compact disk ROM (read-only memory) (CD-ROM), can the dish of other type any of rewriteable compact disc (CD-RW) and magneto-optic disk; The such as semiconductor devices of ROM (read-only memory) (ROM) and so on; The such as random-access memory (ram) of dynamic RAM (DRAM), static RAM (SRAM) and so on; Erasable Programmable Read Only Memory EPROM (EPROM); Flash memory; Electrically Erasable Read Only Memory (EEPROM); Magnetic or optical card; Or be suitable for the medium of other type any of store electrons instruction.
Therefore, embodiments of the invention also comprise non-transient tangible machine computer-readable recording medium, and this medium comprises the design data of such as HDL and so on, and this design data limits structure described herein, circuit, device, processor and/or system features.This type of embodiment also can be called as program product.
Some operation of instruction disclosed herein can be performed by nextport hardware component NextPort, and may be embodied in machine-executable instruction, and this instruction is for causing or at least causing circuit or other nextport hardware component NextPort to perform the instruction programming of this operation.Circuit can comprise universal or special processor or logical circuit, only provides several example here.Operation is also optionally performed by the combination of hardware and software.Actuating logic and/or processor can comprise in response to the machine instruction derived from machine instruction or one or more control signal with the special or particular electrical circuit of the result operand storing instruction and specify or other logic.Such as, the embodiment of instruction disclosed herein can Fig. 7,8 and 9 one or more systems in perform, and the embodiment of instruction can be stored in the program code that performs in systems in which.
Foregoing description is intended to the preferred embodiments of the present invention are described.According to the above discussion, also should it is evident that, development rapidly and further progress be difficult in this technical field predicted, those skilled in the art can arrangement and details on modify to the present invention, and do not deviate from drop on claims and equivalence thereof scope in principle of the present invention.Such as, one or more operations of method may be combined with or separate further.
Embodiment
Although described the embodiment by naturally performing instruction disclosed herein, but the simulation layer that optional embodiment of the present invention performs by operating on the processor (processor of the ARM instruction set that the ARM such as, perform the processor of the MIPS instruction set of the MIPS technology of the sub-state Sani Wei Er of U.S. markon good fortune, performing the sub-state Sani Wei Er of markon's good fortune keeps) of different instruction set performs instruction.Equally, although the process flow diagram in accompanying drawing illustrate some embodiment of the present invention specific operation order, by should understand this order be exemplary (such as, embodiment can by different order executable operations, combine some operate, make some operation overlap etc.).
In the above description, for the purpose of explaining, numerous detail is illustrated to provide the thorough understanding to embodiments of the invention.But, by it is apparent to those skilled in the art that when do not have in these details some, also can put into practice other embodiments one or more.Described specific embodiment is provided not to be to limit the present invention but in order to embodiments of the invention are described.Scope of the present invention is not determined by the concrete example provided above, but only determined by claims.
Claims (14)
1. in computer processor, perform a method for franchise unknowable segment base register write command, comprising:
Obtain described privilege unknowable segment base register write command, wherein said privilege unknowable segment base register write command comprises 64 bit data source operand;
Obtained privilege unknowable segment base register write command is decoded;
Perform the privilege unknowable segment base register write command through decoding, 64 bit data of described source operand to be write in the segment base register identified by the operational code of described privilege unknowable segment base register write command.
2. the method for claim 1, is characterized in that, described segment base register is IA32_FS_BASE.
3. the method for claim 1, is characterized in that, described segment base register is IA32_GS_BASE.
4. the method for claim 1, is characterized in that, described privilege unknowable segment base register write command is a part for prerogative grade 3 program.
5. the method for claim 1, is characterized in that, also comprises:
By checking that the CPUID characteristic indication of described computer processor determines that described computer processor can support described privilege unknowable segment base register write command.
6. method as claimed in claim 5, is characterized in that, also comprise:
The mark that described privilege unknowable segment base register write command is supported in instruction is set in described computer processor.
7. the method for claim 1, is characterized in that, also comprises:
By checking that the CPUID characteristic indication of described computer processor determines that described computer processor can not support described privilege unknowable segment base register write command; And
The mark that described privilege unknowable segment base register write command is not supported in instruction is set in described computer processor.
8. in computer processor, perform a method for franchise unknowable segment base register read instructions, comprising:
Obtain the unknowable segment base register read instructions of described privilege, the unknowable segment base register read instructions of wherein said privilege comprises 64 bit data destination operands;
The unknowable segment base register read instructions of obtained privilege is decoded;
Perform the unknowable segment base register read instructions of privilege through decoding, to read 64 bit data in the segment base register identified by the operational code of the unknowable segment base register of described privilege, and this 64 bit data is stored in the position identified by described 64 bit data destination operands.
9. method as claimed in claim 8, it is characterized in that, described segment base register is IA32_FS_BASE.
10. method as claimed in claim 8, it is characterized in that, described segment base register is IA32_GS_BASE.
11. methods as claimed in claim 8, is characterized in that, the unknowable segment base register read instructions of described privilege is a part for prerogative grade 3 program.
12. methods as claimed in claim 8, is characterized in that, also comprise:
By checking that the CPUID characteristic indication of described computer processor determines that described computer processor can support the unknowable segment base register read instructions of described privilege.
13. methods as claimed in claim 12, is characterized in that, also comprise:
The mark that the unknowable segment base register read instructions of described privilege is supported in instruction is set in described computer processor.
14. methods as claimed in claim 8, is characterized in that, also comprise:
By checking that the CPUID characteristic indication of described computer processor determines that described computer processor can not support the unknowable segment base register read instructions of described privilege;
The mark that the unknowable segment base register read instructions of described privilege is not supported in instruction is set in described computer processor.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/976,981 US8938606B2 (en) | 2010-12-22 | 2010-12-22 | System, apparatus, and method for segment register read and write regardless of privilege level |
| US12/976,981 | 2010-12-22 | ||
| PCT/US2011/060011 WO2012087446A1 (en) | 2010-12-22 | 2011-11-09 | System, apparatus, and method for segment register read and write regardless of privilege level |
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| CN103270489A CN103270489A (en) | 2013-08-28 |
| CN103270489B true CN103270489B (en) | 2016-03-02 |
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| WO2012098211A1 (en) * | 2011-01-21 | 2012-07-26 | Technicolor Delivery Technologies | Method for backward-compatible aggregate file system operation performance improvement, and respective apparatus |
| EP2973175B1 (en) | 2013-03-13 | 2019-07-31 | Intel Corporation | Managing device driver cross ring accesses |
| US20140310484A1 (en) * | 2013-04-16 | 2014-10-16 | Nvidia Corporation | System and method for globally addressable gpu memory |
| US20150178078A1 (en) * | 2013-12-21 | 2015-06-25 | H. Peter Anvin | Instructions and logic to provide base register swap status verification functionality |
| US10706143B2 (en) * | 2017-05-19 | 2020-07-07 | Intel Corporation | Techniques for secure-chip memory for trusted execution environments |
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- 2011-11-09 JP JP2013546145A patent/JP5688165B2/en active Active
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| TW201241742A (en) | 2012-10-16 |
| KR20130112909A (en) | 2013-10-14 |
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