CN103247531B - Thin-film transistor and preparation method thereof and display - Google Patents
Thin-film transistor and preparation method thereof and display Download PDFInfo
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- CN103247531B CN103247531B CN201210032626.1A CN201210032626A CN103247531B CN 103247531 B CN103247531 B CN 103247531B CN 201210032626 A CN201210032626 A CN 201210032626A CN 103247531 B CN103247531 B CN 103247531B
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Abstract
One embodiment of the invention provides a kind of manufacture method of thin-film transistor, comprising: on a substrate, sequentially form a grid, a gate insulation layer and an active layers; Form an insulating metal oxide layer and cover active layers, wherein insulating metal oxide layer comprises the metal oxide of one first metal; Cover active layers in formation one metal level, metal level comprises one second metal; Formed with the one source pole of a trench separation and a drain electrode on metal level; Remove the metal level that groove exposes; And an annealing process is carried out to metal level and insulating metal oxide layer, to make metal level and insulating metal oxide layer react and form a conductivity composite metal oxide layer, it comprises the first metal and the second metal.
Description
Technical field
The present invention has about a kind of thin-film transistor, and relates to a kind of bottom gate thin film transistor especially.
Background technology
Along with being showing improvement or progress day by day of display science and technology, people can make life more convenient by the auxiliary of display, are the characteristic asking display light, thin, impel the main flow that flat-panel screens (flatpaneldisplay, FPD) becomes current.In many flat-panel screens, liquid crystal display (liquidcrystaldisplay, LCD) has the advantageous characteristic such as high spatial utilization ratio, low consumpting power, radiationless and low EMI, and therefore, liquid crystal display is very popular.
Liquid crystal display is mainly made up of active array substrate, colored optical filtering substrates and the liquid crystal layer between two substrates.Active array substrate has active region and periphery circuit region.Active array is positioned at active region, and the drive circuit with multiple bottom gate thin film transistor is then positioned at periphery circuit region.
In prior art, the technique of bottom gate thin film transistor can suffer from some problems, and such as, when forming source electrode with drain electrode, easy damage is positioned at the active layers under it, so that back of the body passage is impaired.
Summary of the invention
One embodiment of the invention provides a kind of manufacture method of thin-film transistor, comprising: provide a substrate; A grid and a gate insulation layer cover gate is formed on substrate; On gate insulation layer, form an active layers, wherein active layers is positioned at above grid; On gate insulation layer, form an insulating metal oxide layer cover active layers, wherein insulating metal oxide layer comprises the metal oxide of one first metal; Formation one metal level on insulating metal oxide layer, metal level covers active layers, and wherein metal level comprises the second metal that is different from the first metal; On metal level, form one source pole and a drain electrode, and drain electrode is positioned in active layers and with the relative both sides of a trench separation in grid, groove exposes partial metal layers for source electrode; Remove the metal level that groove exposes, to expose SI semi-insulation metal oxide layer; And an annealing process is carried out to metal level and insulating metal oxide layer, react to make metal level and insulating metal oxide layer and form a conductivity composite metal oxide layer, it comprises the first metal and the second metal, and wherein conductivity composite metal oxide layer electrical connection active layers is with source electrode and be electrically connected active layers and drain electrode.
One embodiment of the invention provides a kind of manufacture method of thin-film transistor, comprising: provide a substrate; A grid and a gate insulation layer cover gate is formed on substrate; On gate insulation layer, form an active layers, wherein active layers is positioned at above grid; On gate insulation layer, form an insulating metal oxide layer cover active layers, wherein insulating metal oxide layer comprises the metal oxide of a metal; Formation one mask layer on insulating metal oxide layer, mask layer has a Part I and the Part II that one first opening and one second opening expose insulating metal oxide layer respectively, and Part I and Part II lay respectively at above the relative both sides of grid; Carry out an annealing process, so that Part I and Part II are reduced into one first conductive part and one second conductive part respectively, the material of the first conductive part and the second conductive part is the first metal or the oxygen content conducting metal oxide lower than insulating metal oxide layer; Remove mask layer; And one source pole and a drain electrode is formed respectively on the first conductive part and the second conductive part.
One embodiment of the invention provides a kind of thin-film transistor, comprising: a substrate; One grid, is configured on substrate; One gate insulation layer, to be configured on substrate and cover gate; One active layers, to be configured on gate insulation layer and to be positioned at above grid; One protection conductive layer, be configured in active layers, and there is one first conductive part and one second conductive part of the relative both sides laying respectively at grid, first conductive part and the second conductive part, with a trench separation, wherein protect conductive layer to be that the metal oxide layer or of metal level, containing the first metal containing one first metal comprises the first metal and a bimetallic conductivity composite metal oxide layer simultaneously; One insulating metal oxide layer, is configured in active layers, and is arranged in groove, and with electrical isolation first conductive part and the second conductive part, wherein insulating metal oxide layer is a metal oxide layer containing the first metal; And one source pole and drains, be configured at respectively on the first conductive part and the second conductive part.
The present invention utilizes metal level as etching stop layer during etching separating part, to protect insulating metal oxide layer under it and active layers.Further, utilize insulating metal oxide layer as protective layer when removing metal level, to protect the active layers be positioned under insulating metal oxide layer.Afterwards, annealing process is utilized to make insulating metal oxide layer and metal level react and form conductivity composite metal oxide layer, to be electrically connected active layers with source electrode and be electrically connected active layers and drain electrode.
Accompanying drawing explanation
Figure 1A to Fig. 1 D illustrates the process section of the thin-film transistor of one embodiment of the invention.
Fig. 2 illustrates the process section of the thin-film transistor of another embodiment of the present invention.
Fig. 3 A to Fig. 3 C illustrates the process section of the thin-film transistor of another embodiment of the present invention.
Fig. 4 A to Fig. 4 D illustrates the process section of the thin-film transistor of another embodiment of the present invention.
Fig. 5 illustrates the profile of the display of one embodiment of the invention.
Drawing reference numeral:
110 ~ substrate;
120 ~ grid;
130 ~ gate insulation layer;
140 ~ active layers;
150,410 ~ insulating metal oxide layer;
160 ~ metal level;
170 ~ protection conductive layer;
172 ~ source electrode;
174 ~ drain electrode;
176 ~ separating part;
178,186 ~ groove;
180 ~ conductivity composite metal oxide layer;
182 ~ the first conductive parts;
184 ~ the second conductive parts;
190 ~ boundary layer;
412 ~ Part I;
412a ~ the first conductive part;
414 ~ Part II;
414a ~ the second conductive part;
420 ~ mask layer;
422 ~ the first openings;
424 ~ the second openings;
500 ~ display;
510 ~ thin film transistor base plate;
520 ~ substrate;
530 ~ display medium;
P ~ photoresist layer;
T1 ~ thickness.
Embodiment
Making and the occupation mode of the embodiment of the present invention will be described in detail below.But it should be noted, the invention provides many inventive concepts for application, it can multiple specific pattern be implemented.In literary composition illustrate discuss specific embodiment be only manufacture with use ad hoc fashion of the present invention, be not used to limit the scope of the invention.In addition, label or the sign of repetition may be used in different embodiments.These repeat only clearly to describe the present invention in order to simple, do not represent between discussed different embodiment and/or structure and have any relevance.Moreover, when address one first material layer to be positioned on one second material layer or on time, comprise the first material layer directly contacted or to be separated with one or more other materials layer situation with the second material layer.In the drawings, the shape of embodiment or thickness can expand, to simplify or conveniently to indicate.Moreover the element not illustrating in figure or describe, for having the form usually known known to the knowledgeable in art.
Figure 1A to Fig. 1 D illustrates the process section of the thin-film transistor of one embodiment of the invention.Please refer to Figure 1A, provide a substrate 110, such as a glass substrate.Then, on substrate 110, form grid 120 and gate insulation layer 130 cover gate 120.In one embodiment, the material of grid 120 can comprise aluminium (Al) and molybdenum (Mo) or other electric conducting materials be applicable to.The material of gate insulation layer 130 is such as silicon dioxide or other have the dielectric material of high-k.
Then, on gate insulation layer 130, form an active layers 140, wherein active layers 140 is positioned at above grid 120.The material of active layers 140 is such as indium gallium zinc oxide (IGZO, indium – gallium – zinc – oxide) or other semi-conducting materials being suitable for as active layers.
Afterwards, on gate insulation layer 130, form an insulating metal oxide layer 150 cover active layers 140, wherein insulating metal oxide layer 150 comprises the metal oxide of one first metal, such as aluminium oxide.Form the method for insulating metal oxide layer 150 such as pass into oxygen to be directly plated in active layers 140 by metal oxide while jet-plating metallization.The thickness T1 of insulating metal oxide layer 150 is such as about 100 dust to 300 dusts.In one embodiment, the thickness T1 of insulating metal oxide layer 150 is about 150 dust to 250 dusts.
Then, on insulating metal oxide layer 150, form a metal level 160, metal level 160 covers active layers 140, and wherein metal level 160 comprises the second metal that is different from the first metal.The material of metal level 160 is such as titanium or other metal materials be applicable to.
Then; on metal level 160, optionally form a protection conductive layer 170; protection conductive layer 170 comprises one source pole 172, in active layers 140 and to drain 174 and one separating parts 176 between source electrode 172 and drain electrode 174, wherein source electrode 172 and the 174 relative both sides laying respectively at grid 120 that drain.The material of protection conductive layer 170 can comprise aluminium, molybdenum, titanium, copper or other electric conducting materials be applicable to.In the present embodiment, the material of conductive layer 170 is protected to comprise aluminium and molybdenum.Afterwards, on protection conductive layer 170, form a photoresist layer P cover source electrode 172 and drain electrode 174, and expose separating part 176.
Afterwards, referring to Figure 1A and Figure 1B, with photoresist layer P for mask carries out a wet etching process, to remove separating part 176 and to expose partial metal layers 160.Specifically, a groove 178 can be left between source electrode 172 and drain electrode 174 after removing separating part 176, and groove 178 exposes partial metal layers 160.In one embodiment, metal level 160 is a titanium layer, and because wet etching process not easily etches titanium, therefore, metal level 160 can be used as the etching stop layer of wet etching process.
Then, please refer to Fig. 1 C, optionally with source electrode 172 with drain electrode 174 for mask, carry out a dry etch process, to remove the metal level 160 that groove 178 exposes, and then expose SI semi-insulation metal oxide layer 150.
Then, please refer to Fig. 1 D, an annealing process is carried out to metal level 160 and insulating metal oxide layer 150, form a conductivity composite metal oxide layer 180 to make metal level 160 and insulating metal oxide layer 150 react.The technological temperature of annealing process is such as about 300 DEG C to 700 DEG C, and the process time is such as more than 30 minutes.
Specifically, due to conductivity composite metal oxide layer 180 by the insulating metal oxide layer 150 comprising the first metal with comprise bimetallic metal level 160 and react and form, therefore, conductivity composite metal oxide layer 180 is one comprise the first metal and bimetallic conductive layer simultaneously.In one embodiment, the first metal is aluminium, and insulating metal oxide layer 150 is aluminium oxide (Al
2o
3) layer, the second metal is titanium, and conductivity composite metal oxide layer 180 is titanium aluminum oxide (TiAl
2o
5) layer.
Conductivity composite metal oxide layer 180 is electrically connected active layers 140 and source electrode 172 and is electrically connected active layers 140 and drain electrode 174.Specifically, conductivity composite metal oxide layer 180 has one first conductive part 182 and one second conductive part 184 of the relative both sides laying respectively at grid 120, and the first conductive part 182 and the second conductive part 184 are separated with a groove 186, wherein insulating metal oxide layer 150 is arranged in groove 186, with electrical isolation first conductive part 182 and the second conductive part 184.Source electrode 172 lays respectively on the first conductive part 182 and the second conductive part 184 with drain electrode 174.Metal level 160 is between the first conductive part 182 and source electrode 172 and between the second conductive part 184 and drain electrode 174.
In one embodiment, source electrode 172 is identical with the metal level 160 of length roughly with corresponding of drain electrode 174.Specifically, the same length of source electrode 172 is in the length of the part between the first conductive part 182 and source electrode 172 of metal level 160.The same length of drain electrode 174 is in the length of the part between the second conductive part 184 and drain electrode 174 of metal level 160.In one embodiment, the length of active layers 140 is less than the length of grid 120.
It should be noted that, because the conduction property of conductivity composite metal oxide layer 180 (such as titanium aluminum oxide) is close to semiconductor, therefore can match with the contact impedance of the active layers 140 being all semiconductor material, therefore active layers 140 and source electrode 172 (or draining 174) can be electrically connected well.
In addition, the part adjacent with metal level 160 of insulating metal oxide layer 150 must complete reaction become conductivity composite metal oxide layer 180 to be electrically connected active layers 140 and source electrode 172 (or draining 174), but metal level 160 might not want complete reaction to become conductivity composite metal oxide layer 180.Fig. 1 D is the embodiment illustrating metal level 160 not complete reaction, but is not limited thereto, and in other embodiments, as shown in Figure 2, metal level 160 complete reaction can become conductivity composite metal oxide layer 180.
From aforementioned, the present embodiment utilizes metal level 160 as etching stop layer during etching separating part 176, to protect insulating metal oxide layer it under 150 and active layers 140.Therefore, the present embodiment can avoid prior art to fall separating part to such an extent as to the problem of active layers under damaging it because of direct etching.Further, utilize insulating metal oxide layer 150 as protective layer when removing metal level 160, to protect the active layers 140 be positioned under insulating metal oxide layer 150.Afterwards, utilize annealing process to make the connection active layers 140 of insulating metal oxide layer 150 and the part of source electrode 172 and be connected active layers 140 and react with metal level 160 with the part of drain electrode 174 and form conductivity composite metal oxide layer 180, to be electrically connected active layers 140 with source electrode 172 and be electrically connected active layers 140 and drain 174.
Fig. 3 A to Fig. 3 C illustrates the process section of the thin-film transistor of another embodiment of the present invention.In another embodiment, please refer to Fig. 3 A, before formation metal level 160, insulating metal oxide layer 150 can deposit a boundary layer 190, boundary layer 190 comprises the first metal and bimetallic oxide, and boundary layer 190 such as comprises titanium aluminum oxide (Ti
0.2al
0.8o
x, TAO, wherein 0.2≤X<1.4).Afterwards, can be formed on boundary layer 190 metal level 160, source electrode 172, with drain electrode 174.
Then, please refer to Fig. 3 B, the metal level 160 that removable groove 178 exposes and the boundary layer 190 be positioned at below groove 178.Afterwards, please refer to Fig. 3 C, one annealing process is carried out to metal level 160, boundary layer 190 and insulating metal oxide layer 150, to make metal level 160, boundary layer 190, react with insulating metal oxide layer 150 and to form a conductivity composite metal oxide layer 180.
Fig. 4 A to Fig. 4 D illustrates the process section of the thin-film transistor of another embodiment of the present invention.It should be noted that the element of the present embodiment is same as the element of the embodiment of Figure 1A to Fig. 1 D, material, structure are identical with manufacture method, therefore, repeat no more in this.
First, please refer to Fig. 4 A, a substrate 110 is provided.Then, to be same as the method for Fig. 4 A, substrate 110 sequentially forms grid 120, gate insulation layer 130 and an active layers 140.Then, on gate insulation layer 130, form an insulating metal oxide layer 410 cover active layers 140, wherein insulating metal oxide layer 410 comprises the metal oxide of a metal.
Form the method for insulating metal oxide layer 410 such as pass into oxygen to be directly plated in active layers 140 by metal oxide while jet-plating metallization.In one embodiment, metal is copper, molybdenum or aluminium, and insulating metal oxide layer 410 is copper monoxide layer, molybdenum monoxide layer or an alumina layer.
Then, form a mask layer 420 on insulating metal oxide layer 410, mask layer 420 has Part I 412 and the Part II 414 that one first opening 422 and one second opening 424 expose insulating metal oxide layer 410 respectively.Part I 412 and Part II 414 lay respectively at above the relative both sides of grid 120.The material of mask layer 420 is such as photoresist or applicable organic material.
Then, please refer to Fig. 4 B, such as, in an environment under low pressure, carry out an annealing process, so that Part I 412 and Part II 414 are reduced into one first conductive part 412a and one second conductive part 414a respectively.The pressure of environment under low pressure is such as be less than 100 milli-torrs.The temperature of annealing process such as about 100 DEG C to 400 DEG C.
Specifically, the present embodiment removes by annealing process the oxygen molecule that Part I 412 has with Part II 414, to form electrical conductivity the first higher conductive part 412a and the second conductive part 414a, wherein the material of the first conductive part 412a and the second conductive part 414a can be the first metal or the oxygen content conducting metal oxide lower than insulating metal oxide layer 410.
It should be noted that, after carrying out annealing process, for insulating metal oxide layer 410, the part of only having mask layer 420 to expose (Part I 412 and Part II 414) just can be transformed into the first conductive part 412a and the second conductive part 414a with conduction property, and all the other parts of being covered by mask layer 420 are not removed due to oxygen molecule therefore still possess the character of insulation.Therefore, the part of possessing the character of insulation of insulating metal oxide layer 410 can be separated between the first conductive part 412a and the second conductive part 414a, is electrically insulated to make the first conductive part 412a and the second conductive part 414a.
Afterwards, please refer to Fig. 4 C, remove mask layer 420.Then, please refer to Fig. 4 D, on the first conductive part 412a and the second conductive part 414a, form one source pole 172 and respectively drain 174.Source electrode 172 can be similar to the formation method shown in Figure 1A and Figure 1B with the formation method of drain electrode 174.
From aforementioned, the present embodiment forms insulating metal oxide layer 410 by active layers 140, and the predetermined connection source electrode 172 of insulating metal oxide layer 410 is become the first conductive part 412a and the second conductive part 414a with the partial reduction of drain electrode 174, to be electrically connected active layers 140 and source electrode 172 and to be electrically connected active layers 140 and to drain 174 in the arrange in pairs or groups mode of annealing process of mask layer 420.After an anneal process, the part of possessing insulation characterisitic of insulating metal oxide layer 410 can be separated between the first conductive part 412a and the second conductive part 414a, and can be used as protective layer when forming source electrode 172 and drain electrode 174.
It should be noted that, although aforementioned multiple embodiment is the thin-film transistor with bottom gate configuration for example explains, but the present invention is not limited thereto, for example, thin-film transistor structure of the present invention and manufacture method also can be applicable on the thin-film transistor that has and push up grid structure.
Fig. 5 illustrates the profile of the display of one embodiment of the invention.Please refer to Fig. 5, the display 500 of the present embodiment comprises thin film transistor base plate 510, substrate 520 and and is sandwiched in display medium 530 between thin film transistor base plate 510 and substrate 520.Thin film transistor base plate 510 can be earlier figures 1D, the thin film transistor base plate shown in Fig. 2, Fig. 3 C and Fig. 4 D, and display medium 530 can be liquid crystal layer or organic luminous layer.Substrate 520 is such as colored optical filtering substrates or transparency carrier.
In sum, the present invention utilizes metal level as etching stop layer during etching separating part, to protect insulating metal oxide layer under it and active layers.Further, utilize insulating metal oxide layer as protective layer when removing metal level, to protect the active layers be positioned under insulating metal oxide layer.Afterwards, annealing process is utilized to make insulating metal oxide layer and metal level react and form conductivity composite metal oxide layer, to be electrically connected active layers with source electrode and be electrically connected active layers and drain electrode.
From aforementioned, the present invention is by forming insulating metal oxide layer in active layers, and the predetermined connection source electrode of insulating metal oxide layer is become the first conductive part and the second conductive part with the partial reduction of drain electrode, to be electrically connected active layers with source electrode and be electrically connected active layers and drain electrode in the mode of mask layer collocation annealing process.After an anneal process, the part of possessing insulation characterisitic of insulating metal oxide layer can be separated between the first conductive part and the second conductive part, and can be used as protective layer when forming source electrode and drain electrode.
Though the present invention discloses as above with preferred embodiment; so itself and be not used to limit scope of the present invention; technical staff in any art; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion of defining with claim.
Claims (25)
1. a manufacture method for thin-film transistor, is characterized in that, described method comprises:
One substrate is provided;
A grid is formed and a gate insulation layer covers described grid on described substrate;
On described gate insulation layer, form an active layers, wherein said active layers is positioned at above described grid;
On described gate insulation layer, form an insulating metal oxide layer cover described active layers, wherein said insulating metal oxide layer comprises the metal oxide of one first metal;
Formation one metal level on described insulating metal oxide layer, described metal level covers described active layers, and wherein said metal level comprises the second metal that is different from described first metal;
On described metal level, form one source pole and a drain electrode, described source electrode and described drain electrode are positioned in described active layers and with the relative both sides of a trench separation in described grid, described groove exposes the described metal level of part;
Remove and be exposed to metal level described in described groove, to expose the described insulating metal oxide layer being positioned at described groove; And
One annealing process is carried out to described metal level and described insulating metal oxide layer, to produce in the place of overlapping each other to make described metal level and described insulating metal oxide layer and react and form a conductivity composite metal oxide layer, it comprises described first metal and described second metal, and wherein said conductivity composite metal oxide layer connects described active layers with described source electrode and be connected described active layers and described drain electrode.
2. the manufacture method of thin-film transistor as claimed in claim 1, it is characterized in that, described first metal is aluminium, and described insulating metal oxide layer is an alumina layer, described second metal is titanium, and described conductivity composite metal oxide layer is a titanium al oxide layer.
3. the manufacture method of thin-film transistor as claimed in claim 1, it is characterized in that, the step forming described source electrode and described drain electrode comprises:
On described metal level, form a protection conductive layer, described protection conductive layer comprises one source pole, the separating part of a drain electrode and between described source electrode and described drain electrode in described active layers;
On described protection conductive layer, form a photoresist layer cover described source electrode and described drain electrode, and expose described separating part; And
With described photoresist layer for mask carries out a wet etching process, to remove described separating part and to expose the described metal level of part.
4. the manufacture method of thin-film transistor as claimed in claim 1, it is characterized in that, the step removing the described metal level that described groove exposes comprises:
With described source electrode and described drain electrode for mask, carry out a dry etch process.
5. the manufacture method of thin-film transistor as claimed in claim 1, is characterized in that, before the described metal level of formation, described manufacture method more comprises:
Described insulating metal oxide layer forms a boundary layer, and described boundary layer comprises described first metal and described bimetallic oxide,
The step wherein removing the described metal level that described groove exposes more comprises:
Remove the described boundary layer being positioned at described beneath trenches.
6. a manufacture method for thin-film transistor, is characterized in that, described method comprises:
One substrate is provided;
A grid is formed and a gate insulation layer covers described grid on described substrate;
On described gate insulation layer, form an active layers, wherein said active layers is positioned at above described grid;
On described gate insulation layer, form an insulating metal oxide layer cover described active layers, wherein said insulating metal oxide layer comprises the metal oxide of one first metal;
Formation one mask layer on described insulating metal oxide layer, described mask layer has a Part I and the Part II that one first opening and one second opening expose described insulating metal oxide layer respectively, and described Part I and described Part II lay respectively at above the relative both sides of described grid;
Carry out an annealing process, so that described Part I and described Part II are reduced into one first conductive part and one second conductive part respectively, the material of described first conductive part and described second conductive part is described first metal or the oxygen content conducting metal oxide lower than described insulating metal oxide layer;
Remove described mask layer; And
One source pole and a drain electrode is formed respectively on described first conductive part and described second conductive part.
7. the manufacture method of thin-film transistor as claimed in claim 6, it is characterized in that, the step of carrying out described annealing process comprises:
Described annealing process is carried out in an environment under low pressure.
8. the manufacture method of thin-film transistor as claimed in claim 7, it is characterized in that, the pressure of described environment under low pressure is less than 100 milli-torrs.
9. the manufacture method of thin-film transistor as claimed in claim 6, it is characterized in that, the temperature of described annealing process is 100 DEG C to 400 DEG C.
10. a thin-film transistor, is characterized in that, described thin-film transistor comprises:
One substrate;
One grid, is configured on described substrate;
One gate insulation layer, to be configured on described substrate and to cover described grid;
One active layers, to be configured on described gate insulation layer and to be positioned at above described grid;
One protection conductive layer, be configured in described active layers, and there is one first conductive part and one second conductive part of the relative both sides laying respectively at described grid, described first conductive part and described second conductive part are with a trench separation, and wherein said protection conductive layer is that the metal oxide layer or of metal level, containing described first metal containing one first metal comprises the bimetallic conductivity composite metal oxide layer that described first metal and is different from described first metal simultaneously;
One insulating metal oxide layer, is configured in described active layers, and is arranged in described groove, and with the first conductive part described in electrical isolation and described second conductive part, wherein said insulating metal oxide layer is a metal oxide layer containing described first metal; And
One source pole and one drains, and is configured at respectively on described first conductive part and described second conductive part.
11. thin-film transistors as claimed in claim 10, is characterized in that, the oxygen content of described insulating metal oxide layer is higher than the oxygen content of described protection conductive layer.
12. thin-film transistors as claimed in claim 10, is characterized in that, comprise described first metal and described bimetallic described conductivity composite metal oxide layer is a titanium al oxide layer.
13. thin-film transistors as claimed in claim 10, is characterized in that, the described metal oxide layer containing described first metal is copper monoxide layer, molybdenum monoxide layer or an alumina layer.
14. thin-film transistors as claimed in claim 10, is characterized in that, the described metal level containing described first metal is a layers of copper, a molybdenum layer or an aluminium lamination.
15. thin-film transistors as claimed in claim 10, it is characterized in that, described first metal is copper, molybdenum or aluminium, and described insulating metal oxide layer is copper monoxide layer, molybdenum monoxide layer or an alumina layer.
16. thin-film transistors as claimed in claim 10, is characterized in that, the material of described active layers comprises indium gallium zinc oxide.
17. thin-film transistors as claimed in claim 10, is characterized in that, when described protection conductive layer is for comprising described first metal and described bimetallic described conductivity composite metal oxide layer, described thin-film transistor more comprises:
One metal level, between described first conductive part and described source electrode and between described second conductive part and described drain electrode, described metal level comprises described second metal.
18. thin-film transistors as claimed in claim 17, is characterized in that, described source electrode is identical with the length of corresponding described metal level with the length of described drain electrode.
19. thin-film transistors as claimed in claim 10; it is characterized in that; when described protection conductive layer is for comprising described first metal and described bimetallic described conductivity composite metal oxide layer; described first metal is aluminium; described insulating metal oxide layer is an alumina layer; described second metal is titanium, and described conductivity composite metal oxide layer is a titanium al oxide layer.
20. thin-film transistors as claimed in claim 10, is characterized in that, the thickness of described insulating metal oxide layer is 100 dust to 300 dusts.
21. thin-film transistors as claimed in claim 20, is characterized in that, the thickness of described insulating metal oxide layer is 150 dust to 250 dusts.
22. thin-film transistors as claimed in claim 10, it is characterized in that, the length of described active layers is less than the length of grid.
23. 1 kinds of displays, is characterized in that, described display comprises:
One thin film transistor base plate, is provided with multiple thin-film transistor as claimed in claim 10;
One substrate, is oppositely arranged with described thin film transistor base plate; And
One display medium, is formed between described thin film transistor base plate and described substrate.
24. displays as claimed in claim 23, it is characterized in that, described display medium is a liquid crystal layer.
25. displays as claimed in claim 23, it is characterized in that, described display medium is an organic luminous layer.
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| WO2016088488A1 (en) * | 2014-12-05 | 2016-06-09 | 凸版印刷株式会社 | Display device substrate, method for manufacturing display device substrate, and display device using same |
| CN104617152A (en) * | 2015-01-27 | 2015-05-13 | 深圳市华星光电技术有限公司 | Oxide film transistor and manufacturing method thereof |
| CN104766803B (en) | 2015-04-01 | 2018-09-11 | 京东方科技集团股份有限公司 | Production method and TFT, array substrate, the display device of TFT |
| JP6827270B2 (en) * | 2016-03-28 | 2021-02-10 | 株式会社ジャパンディスプレイ | Manufacturing method of semiconductor device |
| CN107946322A (en) * | 2017-12-15 | 2018-04-20 | 京东方科技集团股份有限公司 | Array base palte and its manufacture method, display device |
| CN108550625B (en) * | 2018-04-18 | 2021-04-02 | Tcl华星光电技术有限公司 | Thin film transistor and manufacturing method thereof |
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| CN111710727A (en) * | 2020-06-12 | 2020-09-25 | 深圳市华星光电半导体显示技术有限公司 | Array substrate, preparation method thereof and display panel |
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| CN102122673A (en) * | 2010-11-30 | 2011-07-13 | 友达光电股份有限公司 | Oxide semiconductor thin film transistor structure and manufacturing method thereof |
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| JP3540262B2 (en) * | 1999-09-16 | 2004-07-07 | 松下電器産業株式会社 | Method of manufacturing thin film transistor and method of manufacturing display device using the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3533032A1 (en) * | 1985-09-17 | 1987-03-19 | Standard Elektrik Lorenz Ag | Thin-film field-effect transistor and a method for its fabrication |
| US5286659A (en) * | 1990-12-28 | 1994-02-15 | Sharp Kabushiki Kaisha | Method for producing an active matrix substrate |
| CN102122673A (en) * | 2010-11-30 | 2011-07-13 | 友达光电股份有限公司 | Oxide semiconductor thin film transistor structure and manufacturing method thereof |
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