CN103247531A - Thin film transistor, fabricating method thereof and display - Google Patents
Thin film transistor, fabricating method thereof and display Download PDFInfo
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- CN103247531A CN103247531A CN2012100326261A CN201210032626A CN103247531A CN 103247531 A CN103247531 A CN 103247531A CN 2012100326261 A CN2012100326261 A CN 2012100326261A CN 201210032626 A CN201210032626 A CN 201210032626A CN 103247531 A CN103247531 A CN 103247531A
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Abstract
An embodiment of the invention provides a fabricating method of a thin film transistor, which comprises the steps as follows: a grid electrode, a grid insulation layer and an initiative layer are formed on a substrate sequentially; an insulation metal oxide layer is formed to cover the initiative layer, and contains a metal oxide of a first metal; a meal layer is formed to cover the initiative layer and comprises a second metal; a source electrode and a drain electrode which are separated by a groove are formed on the metal layer; the metal layer exposed out of the groove is removed; and the metal layer and the insulation metal oxide layer are subjected to an annealing process, so that the metal layer and the insulation metal oxide layer react to form a conductive composite metal oxide layer which comprises the first metal and the second metal.
Description
Technical field
The present invention is relevant for a kind of thin-film transistor, and particularly relevant for a kind of bottom gate thin film transistor.
Background technology
Along with showing being showing improvement or progress day by day of science and technology, people can make life more convenient by the auxiliary of display, and for asking light, the thin characteristic of display, (flat panel display FPD) becomes present main flow to impel flat-panel screens.In many flat-panel screens, (liquid crystal display LCD) has advantageous characteristic such as high spatial utilization ratio, low consumpting power, radiationless and low electromagnetic interference to LCD, and therefore, LCD is very popular.
LCD is made of active array substrate, colored optical filtering substrates and the liquid crystal layer between two substrates.Active array substrate has active region and periphery circuit region.Active array is positioned at active region, and the drive circuit with a plurality of bottom gate thin film transistors then is positioned at periphery circuit region.
In prior art, the technology of bottom gate thin film transistor can suffer from some problems, and for example when forming source electrode with drain electrode, damage is positioned at the active layers under it easily, so that back of the body passage is impaired.
Summary of the invention
One embodiment of the invention provides a kind of manufacture method of thin-film transistor, comprising: a substrate is provided; On substrate, form a grid and a gate insulation layer cover gate; Form an active layers on gate insulation layer, wherein active layers is positioned at the grid top; Form an insulating metal oxide layer and cover active layers on gate insulation layer, wherein the insulating metal oxide layer comprises the metal oxide of one first metal; Form a metal level on the insulating metal oxide layer, metal level covers active layers, and wherein metal level comprises that one is different from second metal of first metal; Form one source pole and a drain electrode on metal level, source electrode is positioned on the active layers and is separated in the relative both sides of grid with a groove with draining, and groove exposes the part metals layer; Remove the metal level that groove exposes, to expose the SI semi-insulation metal oxide layer; And metal level and insulating metal oxide layer carried out an annealing process,, metal level and insulating metal oxide layer form a conductivity composite metal oxide layer so that reacting, it comprises first metal and second metal, and wherein conductivity composite metal oxide layer is electrically connected active layers with source electrode and is electrically connected active layers and drain electrode.
One embodiment of the invention provides a kind of manufacture method of thin-film transistor, comprising: a substrate is provided; On substrate, form a grid and a gate insulation layer cover gate; Form an active layers on gate insulation layer, wherein active layers is positioned at the grid top; Form an insulating metal oxide layer and cover active layers on gate insulation layer, wherein the insulating metal oxide layer comprises the metal oxide of a metal; On the insulating metal oxide layer, form a mask layer, mask layer has a first and the second portion that one first opening and one second opening expose the insulating metal oxide layer respectively, and first and second portion lay respectively at the top, relative both sides of grid; Carry out an annealing process, so that first and second portion are reduced into one first conductive part and one second conductive part respectively, the material of first conductive part and second conductive part is the conducting metal oxide that metal or an oxygen content are lower than the insulating metal oxide layer; Remove mask layer; And on first conductive part and second conductive part, form one source pole and a drain electrode respectively.
One embodiment of the invention provides a kind of thin-film transistor, comprising: a substrate; One grid is disposed on the substrate; One gate insulation layer is disposed on the substrate and cover gate; One active layers is disposed on the gate insulation layer and is positioned at grid top; One protection conductive layer, be disposed on the active layers, and one first conductive part and one second conductive part with the relative both sides that lay respectively at grid, first conductive part and second conductive part are separated with a groove, and wherein protecting conductive layer is the conductivity composite metal oxide layer that metal oxide layer or that a metal level, that contains one first metal contains first metal comprises first metal and one second metal simultaneously; One insulating metal oxide layer is disposed on the active layers, and is arranged in groove, and with electrical isolation first conductive part and second conductive part, wherein the insulating metal oxide layer is one to contain the metal oxide layer of first metal; And one source pole and a drain electrode, be disposed at respectively on first conductive part and second conductive part.
The present invention is the etching stop layer when utilizing metal level as the etching separating part, to protect insulating metal oxide layer and the active layers under it.And, when removing metal level, utilize the insulating metal oxide layer as protective layer, be positioned at active layers under the insulating metal oxide layer with protection.Afterwards, utilize annealing process that insulating metal oxide layer and metal level are reacted and formation conductivity composite metal oxide layer, to be electrically connected active layers with source electrode and to be electrically connected active layers and drain electrode.
Description of drawings
Figure 1A to Fig. 1 D illustrates the process section of the thin-film transistor of one embodiment of the invention.
Fig. 2 illustrates the process section of the thin-film transistor of another embodiment of the present invention.
Fig. 3 A to Fig. 3 C illustrates the process section of the thin-film transistor of another embodiment of the present invention.
Fig. 4 A to Fig. 4 D illustrates the process section of the thin-film transistor of another embodiment of the present invention.
Fig. 5 illustrates the profile of the display of one embodiment of the invention.
Drawing reference numeral:
110～substrate;
120～grid;
130～gate insulation layer;
140～active layers;
150,410～insulating metal oxide layer;
160～metal level;
170～protection conductive layer;
172～source electrode;
174～drain electrode;
176～separating part;
178,186～groove;
180～conductivity composite metal oxide layer;
182～the first conductive parts;
184～the second conductive parts;
190～boundary layer;
412～first;
412a～first conductive part;
414～second portion;
414a～second conductive part;
420～mask layer;
422～the first openings;
424～the second openings;
500～display;
510～thin film transistor base plate;
520～substrate;
530～display medium;
P～photoresist layer;
T1～thickness.
Embodiment
Below will describe making and the occupation mode of the embodiment of the invention in detail.Yet, it should be noted that the invention provides many inventive concepts of supplying usefulness, it can multiple specific pattern be implemented.The specific embodiment of discussing of giving an example in the literary composition only is to make and use ad hoc fashion of the present invention, and is non-in order to limit the scope of the invention.In addition, in different embodiment, may use label or the sign of repetition.These only repeat to have any relevance in order simply clearly to narrate the present invention, not represent between the different embodiment that discuss and/or the structure.Moreover, when address that one first material layer is positioned on one second material layer or on the time, comprise that first material layer directly contacts with second material layer or be separated with the situation of one or more other materials layers.In graphic, the shape of embodiment or thickness can enlarge, to simplify or convenient the sign.Moreover the element that does not illustrate among the figure or describe is for having the form of knowing usually known to the knowledgeable in the affiliated technical field.
Figure 1A to Fig. 1 D illustrates the process section of the thin-film transistor of one embodiment of the invention.Please refer to Figure 1A, provide a substrate 110, for example a glass substrate.Then, on substrate 110, form a grid 120 and a gate insulation layer 130 cover gate 120.In one embodiment, the material of grid 120 can comprise aluminium (Al) and molybdenum (Mo) or other electric conducting materials that is fit to.The material of gate insulation layer 130 for example is silicon dioxide or other have the dielectric material of high-k.
Then, form an active layers 140 on gate insulation layer 130, wherein active layers 140 is positioned at grid 120 tops.The material of active layers 140 for example be indium gallium zinc oxide (IGZO, indium-gallium-zinc-oxide) or other are suitable for semi-conducting material as active layers.
Afterwards, form an insulating metal oxide layer 150 and cover active layers 140 on gate insulation layer 130, wherein insulating metal oxide layer 150 comprises the metal oxide of one first metal, for example aluminium oxide.The method that forms insulating metal oxide layer 150 for example for aerating oxygen in jet-plating metallization directly metal oxide is plated on the active layers 140.The thickness T 1 of insulating metal oxide layer 150 for example is about 100 dust to 300 dusts.In one embodiment, the thickness T 1 of insulating metal oxide layer 150 is about 150 dust to 250 dusts.
Then, form a metal level 160 on insulating metal oxide layer 150, metal level 160 covers active layers 140, and wherein metal level 160 comprises that one is different from second metal of first metal.The material of metal level 160 for example is titanium or other metal materials that is fit to.
Then; optionally on metal level 160, form a protection conductive layer 170; protection conductive layer 170 comprises in the one source pole 172 on the active layers 140, a drain electrode 174 and at source electrode 172 and the separating part 176 of drain electrode between 174, wherein source electrode 172 and the 174 relative both sides that lay respectively at grid 120 that drain.The material of protection conductive layer 170 can comprise aluminium, molybdenum, titanium, copper or other electric conducting materials that is fit to.In the present embodiment, the material of protection conductive layer 170 comprises aluminium and molybdenum.Afterwards, on protection conductive layer 170, form a photoresist layer P and cover source electrode 172 and drain electrode 174, and expose separating part 176.
Afterwards, please be that mask carries out a wet etching technology with photoresist layer P, to remove separating part 176 and to expose part metals layer 160 simultaneously with reference to Figure 1A and Figure 1B.Specifically, remove separating part 176 and can between source electrode 172 and drain electrode 174, stay a groove 178 afterwards, and groove 178 exposes part metals layer 160.In one embodiment, metal level 160 is a titanium layer, because wet etching technology is difficult for the etching titanium, therefore, metal level 160 can be used as the etching stop layer of wet etching technology.
Then, please refer to Fig. 1 C, is mask with source electrode 172 with drain electrode 174 optionally, carries out a dry etch process, removing the metal level 160 that groove 178 exposes, and then exposes SI semi-insulation metal oxide layer 150.
Then, please refer to Fig. 1 D, metal level 160 and insulating metal oxide layer 150 are carried out an annealing process, so that metal level 160 forms a conductivity composite metal oxide layer 180 with 150 reaction of insulating metal oxide layer.The technological temperature of annealing process for example is about 300 ℃ to 700 ℃, and the process time for example is more than 30 minutes.
Specifically, because conductivity composite metal oxide layer 180 is formed by the insulating metal oxide layer 150 that comprises first metal and metal level 160 reactions that comprise second metal, therefore, conductivity composite metal oxide layer 180 is one to comprise the conductive layer of first metal and second metal simultaneously.In one embodiment, first metal is aluminium, and insulating metal oxide layer 150 is aluminium oxide (Al
2O
3) layer, second metal is titanium, conductivity composite metal oxide layer 180 is titanium aluminum oxide (TiAl
2O
5) layer.
Conductivity composite metal oxide layer 180 is electrically connected active layers 140 with source electrode 172 and is electrically connected active layers 140 and drain electrode 174.Specifically, conductivity composite metal oxide layer 180 has one first conductive part 182 and one second conductive part 184 of the relative both sides that lay respectively at grid 120, and first conductive part 182 and second conductive part 184 are separated with a groove 186, wherein insulating metal oxide layer 150 is arranged in groove 186, with electrical isolation first conductive part 182 and second conductive part 184.Source electrode 172 lays respectively on first conductive part 182 and second conductive part 184 with drain electrode 174.Metal level 160 is between first conductive part 182 and the source electrode 172 and between second conductive part 184 and drain electrode 174.
In one embodiment, source electrode 172 and drain electrode 174 length are roughly identical with corresponding metal level 160.Specifically, the same length of source electrode 172 is in the length of the part between first conductive part 182 and source electrode 172 of metal level 160.The same length of drain electrode 174 is in the length of the part between second conductive part 184 and drain electrode 174 of metal level 160.In one embodiment, the length of active layers 140 is less than the length of grid 120.
It should be noted that, because the conduction property of conductivity composite metal oxide layer 180 (for example titanium aluminum oxide) is near semiconductor, so can be complementary with the contact impedance of the active layers 140 that is all semiconductor material, so can be electrically connected active layers 140 and source electrode 172 (or draining 174) well.
In addition, the part adjacent with metal level 160 of insulating metal oxide layer 150 must complete reaction become conductivity composite metal oxide layer 180 being electrically connected active layers 140 and source electrode 172 (or draining 174), but metal level 160 might not want complete reaction to become conductivity composite metal oxide layer 180.Fig. 1 D illustrates the not embodiment of complete reaction of metal level 160, but is not limited thereto, and in other embodiments, as shown in Figure 2, but metal level 160 complete reactions become conductivity composite metal oxide layer 180.
By as can be known aforementioned, present embodiment is the etching stop layer when utilizing metal level 160 as etching separating part 176, to protect the insulating metal oxide layer 150 and active layers 140 under it.Therefore, to such an extent as to present embodiment can avoid prior art to damage the problem of the active layers under it because directly etching away separating part.And, when removing metal level 160, utilize insulating metal oxide layer 150 as protective layer, be positioned at active layers 140 under the insulating metal oxide layer 150 with protection.Afterwards, utilize the part of connection active layers 140 that annealing process makes insulating metal oxide layer 150 and source electrode 172 and be connected part and metal level 160 reactions of active layers 140 and drain electrode 174 and form conductivity composite metal oxide layer 180, to be electrically connected active layers 140 with source electrode 172 and to be electrically connected active layers 140 and to drain 174.
Fig. 3 A to Fig. 3 C illustrates the process section of the thin-film transistor of another embodiment of the present invention.In another embodiment, please refer to Fig. 3 A, can be before forming metal level 160, at insulating metal oxide layer 150 deposition one boundary layer 190, boundary layer 190 comprises the oxide of first metal and second metal, and boundary layer 190 for example comprises titanium aluminum oxide (Ti
0.2Al
0.8O
X, TAO, wherein 0.2≤X＜1.4).Afterwards, can boundary layer 190 form metal levels 160, source electrode 172, with drain electrode 174.
Then, please refer to Fig. 3 B, the metal level 160 that removable groove 178 exposes and the boundary layer 190 that is positioned at groove 178 belows.Afterwards, please refer to Fig. 3 C, to metal level 160, boundary layer 190, carry out an annealing process with insulating metal oxide layer 150, so that metal level 160, boundary layer 190, form a conductivity composite metal oxide layer 180 with 150 reaction of insulating metal oxide layer.
Fig. 4 A to Fig. 4 D illustrates the process section of the thin-film transistor of another embodiment of the present invention.It should be noted that the element of present embodiment is same as the element of the embodiment of Figure 1A to Fig. 1 D, material, structure are identical with manufacture method, therefore, repeat no more in this.
At first, please refer to Fig. 4 A, a substrate 110 is provided.Then, to be same as the method for Fig. 4 A, on substrate 110, form a grid 120, a gate insulation layer 130 and an active layers 140 in regular turn.Then, form an insulating metal oxide layer 410 and cover active layers 140 on gate insulation layer 130, wherein insulating metal oxide layer 410 comprises the metal oxide of a metal.
The method that forms insulating metal oxide layer 410 for example for aerating oxygen in jet-plating metallization directly metal oxide is plated on the active layers 140.In one embodiment, metal is copper, molybdenum or aluminium, and insulating metal oxide layer 410 is copper monoxide layer, molybdenum monoxide layer or an alumina layer.
Then, form a mask layer 420 on insulating metal oxide layer 410, mask layer 420 has a first 412 and the second portion 414 that one first opening 422 and one second opening 424 expose insulating metal oxide layer 410 respectively.First 412 and second portion 414 lay respectively at the top, relative both sides of grid 120.The material of mask layer 420 for example is photoresist or suitable organic material.
Then, please refer to Fig. 4 B, for example in an environment under low pressure, carry out an annealing process, so that first 412 is reduced into one first conductive part 412a and one second conductive part 414a respectively with second portion 414.The pressure of environment under low pressure for example is less than 100 milli-torrs.For example about 100 ℃ to 400 ℃ of the temperature of annealing process.
Specifically, present embodiment is to remove the oxygen molecule that first 412 and second portion 414 have by annealing process, to form the higher first conductive part 412a and the second conductive part 414a of electrical conductivity, wherein the material of the first conductive part 412a and the second conductive part 414a can be the conducting metal oxide that metal or an oxygen content are lower than insulating metal oxide layer 410.
It should be noted that, after carrying out annealing process, for insulating metal oxide layer 410, the part (first 412 and second portion 414) of having only mask layer 420 to expose just can be transformed into the first conductive part 412a and the second conductive part 414a with conduction property, and all the other parts of being covered by mask layer 420 are still possessed the character of insulation because oxygen molecule is not removed.Therefore, the part of the character of possessing insulation of insulating metal oxide layer 410 can be separated between the first conductive part 412a and the second conductive part 414a, so that the first conductive part 412a and the second conductive part 414a are electrically insulated.
Afterwards, please refer to Fig. 4 C, remove mask layer 420.Then, please refer to Fig. 4 D, on the first conductive part 412a and the second conductive part 414a, form one source pole 172 and a drain electrode 174 respectively.Source electrode 172 can be similar to the formation method shown in Figure 1A and Figure 1B with the formation method of drain electrode 174.
By as can be known aforementioned, present embodiment is by forming insulating metal oxide layer 410 in active layers 140, and in the mode of mask layer 420 collocation annealing processs the predetermined connection source electrode 172 of insulating metal oxide layer 410 is become the first conductive part 412a and the second conductive part 414a with the partial reduction of drain electrode 174, to be electrically connected active layers 140 with source electrode 172 and to be electrically connected active layers 140 and to drain 174.After annealing process, the part of possessing insulation characterisitic of insulating metal oxide layer 410 can be separated between the first conductive part 412a and the second conductive part 414a, and can be used as the protective layer that forms source electrode 172 and drained at 174 o'clock.
It should be noted that, though aforementioned a plurality of embodiment is the thin-film transistor with bottom-gate structure is that example explains, but the invention is not restricted to this, for instance, thin-film transistor structure of the present invention and manufacture method also can be applicable on the thin-film transistor with top grid structure.
Fig. 5 illustrates the profile of the display of one embodiment of the invention.Please refer to Fig. 5, the display 500 of present embodiment comprises that a thin film transistor base plate 510, a substrate 520 and are sandwiched in the display medium 530 between thin film transistor base plate 510 and the substrate 520.Thin film transistor base plate 510 can be the thin film transistor base plate shown in earlier figures 1D, Fig. 2, Fig. 3 C and Fig. 4 D, and display medium 530 can be liquid crystal layer or organic luminous layer.Substrate 520 for example is colored optical filtering substrates or transparency carrier.
In sum, the present invention is the etching stop layer when utilizing metal level as the etching separating part, to protect insulating metal oxide layer and the active layers under it.And, when removing metal level, utilize the insulating metal oxide layer as protective layer, be positioned at active layers under the insulating metal oxide layer with protection.Afterwards, utilize annealing process that insulating metal oxide layer and metal level are reacted and formation conductivity composite metal oxide layer, to be electrically connected active layers with source electrode and to be electrically connected active layers and drain electrode.
By as can be known aforementioned, the present invention is by forming the insulating metal oxide layer in active layers, and in the mode of mask layer collocation annealing process the predetermined connection source electrode of insulating metal oxide layer is become first conductive part and second conductive part with the partial reduction of drain electrode, with the electrical connection active layers with source electrode and be electrically connected active layers and drain electrode.After annealing process, the part of possessing insulation characterisitic of insulating metal oxide layer can be separated between first conductive part and second conductive part, and can be used as the protective layer when forming source electrode with drain electrode.
Though the present invention discloses as above with preferred embodiment; so it is not in order to limit scope of the present invention; technical staff in the technical field under any; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when with being as the criterion that claim was defined.
Claims (25)
1. the manufacture method of a thin-film transistor is characterized in that, described method comprises:
One substrate is provided;
Formation one grid and a gate insulation layer cover described grid on described substrate;
Form an active layers on described gate insulation layer, wherein said active layers is positioned at described grid top;
Form an insulating metal oxide layer and cover described active layers on described gate insulation layer, wherein said insulating metal oxide layer comprises the metal oxide of one first metal;
Form a metal level on described insulating metal oxide layer, described metal level covers described active layers, and wherein said metal level comprises that one is different from second metal of described first metal;
Form one source pole and drain with one on described metal level, described source electrode and described drain electrode are positioned on the described active layers and are separated in the relative both sides of described grid with a groove, and described groove exposes the described metal level of part;
Remove and be exposed to the described metal level of described groove, to expose the described insulating metal oxide layer that is positioned at described groove; And
Described metal level and described insulating metal oxide layer are carried out an annealing process, so that described metal level and described insulating metal oxide layer produce reaction in the place of overlapping each other and form a conductivity composite metal oxide layer, it comprises described first metal and described second metal, and wherein said conductivity composite metal oxide layer connects described active layers with described source electrode and is connected described active layers and described drain electrode.
2. the manufacture method of thin-film transistor as claimed in claim 1, it is characterized in that described first metal is aluminium, described insulating metal oxide layer is an alumina layer, described second metal is titanium, and described conductivity composite metal oxide layer is a titanium al oxide layer.
3. the manufacture method of thin-film transistor as claimed in claim 1 is characterized in that, the step that forms described source electrode and described drain electrode comprises:
Form a protection conductive layer on described metal level, described protection conductive layer comprises at the one source pole on the described active layers, the separating part of a drain electrode and between described source electrode and described drain electrode;
On described protection conductive layer, form a photoresist layer and cover described source electrode and described drain electrode, and expose described separating part; And
Be that mask carries out a wet etching technology with described photoresist layer, to remove described separating part and to expose the described metal level of part.
4. the manufacture method of thin-film transistor as claimed in claim 1 is characterized in that, the step that removes the described metal level that described groove exposes comprises:
Be mask with described source electrode and described drain electrode, carry out a dry etch process.
5. the manufacture method of thin-film transistor as claimed in claim 1 is characterized in that, before forming described metal level, described manufacture method more comprises:
Form a boundary layer at described insulating metal oxide layer, described boundary layer comprises the oxide of described first metal and described second metal,
The step that wherein removes the described metal level that described groove exposes more comprises:
Remove the described boundary layer that is positioned at described beneath trenches.
6. the manufacture method of a thin-film transistor is characterized in that, described method comprises:
One substrate is provided;
Formation one grid and a gate insulation layer cover described grid on described substrate;
Form an active layers on described gate insulation layer, wherein said active layers is positioned at described grid top;
Form an insulating metal oxide layer and cover described active layers on described gate insulation layer, wherein said insulating metal oxide layer comprises the metal oxide of one first metal;
On described insulating metal oxide layer, form a mask layer, described mask layer has a first and the second portion that one first opening and one second opening expose described insulating metal oxide layer respectively, and described first and described second portion lay respectively at the top, relative both sides of described grid;
Carry out an annealing process, so that described first and described second portion are reduced into one first conductive part and one second conductive part respectively, the material of described first conductive part and described second conductive part is the conducting metal oxide that described metal or an oxygen content are lower than described insulating metal oxide layer;
Remove described mask layer; And
On described first conductive part and described second conductive part, form one source pole and a drain electrode respectively.
7. the manufacture method of thin-film transistor as claimed in claim 6 is characterized in that, the step of carrying out described annealing process comprises:
In an environment under low pressure, carry out described annealing process.
8. the manufacture method of thin-film transistor as claimed in claim 7 is characterized in that, the pressure of described environment under low pressure is less than 100 milli-torrs.
9. the manufacture method of thin-film transistor as claimed in claim 6 is characterized in that, about 100 ℃ to 400 ℃ of the temperature of described annealing process.
10. a thin-film transistor is characterized in that, described thin-film transistor comprises:
One substrate;
One grid is disposed on the described substrate;
One gate insulation layer is disposed on the described substrate and covers described grid;
One active layers is disposed on the described gate insulation layer and is positioned at described grid top;
One protection conductive layer, be disposed on the described active layers, and one first conductive part and one second conductive part with the relative both sides that lay respectively at described grid, described first conductive part and described second conductive part are separated with a groove, and wherein said protection conductive layer is that the metal oxide layer or that a metal level, that contains one first metal contains described first metal comprises the conductivity composite metal oxide layer that described first metal and is different from second metal of described first metal simultaneously;
One insulating metal oxide layer is disposed on the described active layers, and is arranged in described groove, and with described first conductive part of electrical isolation and described second conductive part, wherein said insulating metal oxide layer is one to contain the metal oxide layer of described first metal; And
One source pole and a drain electrode are disposed at respectively on described first conductive part and described second conductive part.
11. thin-film transistor as claimed in claim 10 is characterized in that, the oxygen content of described insulating metal oxide layer is higher than the oxygen content of described protection conductive layer.
12. thin-film transistor as claimed in claim 10 is characterized in that, the described conductivity composite metal oxide layer that comprises described first metal and described second metal is a titanium al oxide layer.
13. thin-film transistor as claimed in claim 10 is characterized in that, the described metal oxide layer that contains described first metal is copper monoxide layer, molybdenum monoxide layer or an alumina layer.
14. thin-film transistor as claimed in claim 10 is characterized in that, the described metal level that contains described first metal is a bronze medal layer, a molybdenum layer or an aluminium lamination.
15. thin-film transistor as claimed in claim 10 is characterized in that, described first metal is copper, molybdenum or aluminium, and described insulating metal oxide layer is copper monoxide layer, molybdenum monoxide layer or an alumina layer.
16. thin-film transistor as claimed in claim 10 is characterized in that, the material of described active layers comprises indium gallium zinc oxide.
17. thin-film transistor as claimed in claim 10 is characterized in that, when described protection conductive layer is that described thin-film transistor more comprises when comprising the described conductivity composite metal oxide layer of described first metal and described second metal:
One metal level, between described first conductive part and the described source electrode and between described second conductive part and described drain electrode, described metal level comprises described second metal.
18. thin-film transistor as claimed in claim 17 is characterized in that, roughly the length with corresponding described metal level is identical for the length of described source electrode and described drain electrode.
19. thin-film transistor as claimed in claim 10; it is characterized in that; when described protection conductive layer is when comprising the described conductivity composite metal oxide layer of described first metal and described second metal; described first metal is aluminium; described insulating metal oxide layer is an alumina layer; described second metal is titanium, and described conductivity composite metal oxide layer is a titanium al oxide layer.
20. thin-film transistor as claimed in claim 10 is characterized in that, the thickness of described insulating metal oxide layer is about 100 dust to 300 dusts.
21. thin-film transistor as claimed in claim 20 is characterized in that, the thickness of described insulating metal oxide layer is about 150 dust to 250 dusts.
22. thin-film transistor as claimed in claim 10 is characterized in that, the length of described active layers is less than the length of grid.
23. a display is characterized in that, described display comprises:
One thin film transistor base plate is provided with a plurality of thin-film transistors as claimed in claim 10;
One substrate is oppositely arranged with described thin film transistor base plate; And
One display medium is formed between described thin film transistor base plate and the described substrate.
24. display as claimed in claim 23 is characterized in that, described display medium is a liquid crystal layer.
25. display as claimed in claim 23 is characterized in that, described display medium is an organic luminous layer.
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| US9905580B2 (en) | 2015-04-01 | 2018-02-27 | Boe Technology Group Co., Ltd. | Method for manufacturing thin film transistor, thin film transistor, and array substrate and display device using the same |
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| CN108550625B (en) * | 2018-04-18 | 2021-04-02 | Tcl华星光电技术有限公司 | Thin film transistor and manufacturing method thereof |
| WO2021046734A1 (en) * | 2019-09-11 | 2021-03-18 | 咸阳彩虹光电科技有限公司 | Switch element and display panel |
| WO2021248609A1 (en) * | 2020-06-12 | 2021-12-16 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and preparation method therefor, and display panel |
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