CN103236425B - A kind of DRAM dual chip stack package structure and packaging technology - Google Patents
A kind of DRAM dual chip stack package structure and packaging technology Download PDFInfo
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2924/151—Die mounting substrate
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- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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Abstract
The invention discloses a kind of DRAM dual chip stack package structure and packaging technology, intermediary substrate is adopted to transfer the first chip and the second chip in substrate according to the present invention, intermediary substrate reduces the constraint of transmission line, improve data long distance and transmit the problem brought, improve the electric property of encapsulation.Be different from during traditional DRAM encapsulates the feature of the gold thread camber existed above the second chip, only there is the bonding line between intermediary substrate and substrate in this programme, the second chip to have liquidated bonding line camber in substrate normal direction, decreases the whole height of packaging body.On the other hand, because packaging body only carries out a routing, decrease gold thread consumption, saved packaging cost thus.
Description
Technical field
The present invention relates to a kind of DRAM dual chip stack package structure and packaging technology, DRAM is the abbreviation of DynamicRandomAccessMemory, i.e. dynamic random access memory.
Background technology
Modern society information explosion increases, and be unable to do without the fast development of the consumer electronics product of electronic product-especially and universal, and electronic product miscellaneous is the life of people, study, work bring facility.
Along with the raising that development and the consumer of science and technology require electronic product, mobile phone and the continuous diversification of other consumer electronics functions, performance fast lifting, speed improve constantly, and size strides forward towards light, thin, short, little trend.For this reason, integrated circuit by following two kinds of approach to reduce small product size and to alleviate product weight, the first is SOC(SystemOnChip), i.e. system level chip, by on a single die integrated to memory, processor, analog circuit, digital circuit, interface circuit etc., to realize the functions such as voice, image, data processing; The second is SIP(Systeminpackage), i.e. system in package, by the combination of the integrated circuit (IC) chip of several functions in a package, to realize the function identical with SOC.
With regard to integrated antenna package technology, for meeting compact design concept, the Advanced Packaging form that to have occurred with stacked package, TSV, CSP and WLP be representative.The one that chip stack package encapsulates as 3D, feature with better function with it, cost performance is higher replaces traditional single-chip package gradually, has complied with the trend of electronic product to high integration, multi-functional and miniaturization.Nearest semiconductor equipment shows with materials international (SEMI) and TechSearchInternational research report, be expected to develop with the growth rate of average annual 12% from 2008 to 2010 years chip stack packages, but, manufacture view is but in the face of a challenge, be exactly that chip goes to put the challenge with material aspect, and become increasingly conspicuous, be that traditional chip load adhesive process can not for ultra-thin chip provides enough mechanical support, production capacity and yields as load film.
Dual chip encapsulation is a kind of simple stacked package, some traditional packaging technologies are available reluctantly, this type is encapsulated, the data transmission channel (as input/output interface) of oneself must be had by each chip, and the impact of the power circuit supporting its circuit function must be equipped with, its structure and traditional encapsulated object are had and comparatively significantly distinguishes.
At present, traditional DRAM dual chip encapsulating structure mainly contain two kinds: one be adopt FOW(FilmOverWire) film dual chip encapsulation, it is a kind of and the immediate a kind of packaging technology of traditional load film packaging technology, FOW film integrates the function of load bellows scribing film, its encapsulating structure as shown in Figure 2, the main feature of this structure is for the FOW material without the need to hot curing process after load, disk layer adheres to scribing on FOW film 13b, then the first chip 12b and the second chip 11b load, then carry out wire bonding and plastic packaging.In the structure shown in Fig. 2, gold thread 15b amount ratio as bonding line is larger, cause high expensive, and there is certain gold thread camber for the gold thread 15b of bonding second chip 11b, as the gold thread that label 15b in Fig. 2 directly guides, cause plastic packaging material 16b consumption large, and cause packaging body entirety partially thick further.
Another kind of traditional DRAM dual chip is encapsulated as the dual chip encapsulation that wafer carries out RDL (Redistributionlayer), as shown in Figure 3, this encapsulating structure and upper a kind of encapsulating structure have certain similitude, comparison diagram 2 and Fig. 3, can find out that its gold thread 15c will lack compared with the gold thread 15b shown in Fig. 2.But its major defect be wafer RDL costly, cause packaging cost to increase.Also there is the partially thick defect of the entirety the same with upper a kind of encapsulating structure in it simultaneously.
Comprehensive above-mentioned traditional DRAM two kinds of dual chip encapsulating structures, both must place FOW film or spacer chip to support the second chip in bottom and the second chip.Simultaneously, some stacked package adopts the intermediary layer with conductive through hole, as opened hole in silicon chip and pouring into copper in through hole as interface channel, it is large that this type of technology not only realizes difficulty, and copper and intervening material thermal coefficient of expansion do not mate and may cause departing from intermediary layer in copper heating process and cause package reliability poor.
Summary of the invention
In order to improve, cost in traditional DRAM dual chip stacked package is high, packaging body thickness is large, the problem of poor reliability and poor electrical performance, the object of the present invention is to provide a kind of DRAM dual chip stack package structure using bonding line less, and a kind of packaging technology of this encapsulating structure is provided.
The present invention is by the following technical solutions:
One aspect of the present invention, a kind of DRAM dual chip stack package structure is provided, comprise the first chip, the second chip and be provided with the substrate of substrate circuit, described first chip attachment is in described substrate precalculated position, and the active face of this first chip is the opposite face in attachment face; First surface and described first chip of the intermediary substrate be electrically connected by bonding line and described substrate are electrically connected, and second relative with first surface on intermediary substrate is then electrically connected with the active face of described second chip.
Above-mentioned DRAM dual chip stack package structure, described intermediary substrate and the first chip, the second chip chamber leave fills gap, thus forms packed layer after filling gap-fill filler also solidification.
Above-mentioned DRAM dual chip stack package structure, described intermediary substrate, based on the wiring board of flip-chip, is correspondingly formed for electrically and the first surface salient point of mechanical connection and second salient point on described first surface and second.
Above-mentioned DRAM dual chip stack package structure, described first surface salient point and second salient point are the tin ball formed in select location deposition.
Above-mentioned DRAM dual chip stack package structure, is formed with the transmission line that wire is formed in described intermediary substrate, the starting point of transmission line is connected to corresponding first surface salient point or second salient point, and is formed with the pad for bonding line described in bonding at the end of transmission line.
Above-mentioned DRAM dual chip stack package structure, the width as the described transmission line of power line or earth connection is greater than the width of the transmission line as holding wire.
Above-mentioned DRAM dual chip stack package structure, if the first chip is identical with the second chip size, then intermediary substrate and the longitudinal direction of the first chip are than being 1:1, laterally than being 1.05:1 ~ 1.15:1; If the size of the first chip is greater than the size of the second chip, then intermediary substrate and the longitudinal direction of the first chip are than being 1:1, laterally than being 1:1.
According to another aspect of the present invention, a kind of DRAM dual chip stacking encapsulation method is provided, comprises the following steps:
(1) brush coating, mate the mounting position of the first chip on substrate and carry out brush coating, positional precision should control in 15 μm;
(2) paste the first chip, the opposite face in the first chip active face is mounted on described mounting position, upper slice precision controlling is in 3 μm;
(3) apply filler, the filler of coating predetermined thickness is in the active face of the first chip, and the exposed part electrically for being electrically connected;
(4) paste intermediary substrate, intermediary substrate is mounted on form first chip of filling basic unit active face on, coupling electrical connection, upper slice precision controlling is in 3 μm;
(5) apply filler, the filler of coating predetermined thickness in intermediary substrate mount the first chip opposite face on, and the exposed part for being electrically connected;
(6) mount the second chip, by the second chip attachment on intermediary substrate, form electrical connection, upper slice precision controlling is in 3 μm;
(7) Reflow Soldering, structure after completing steps is sent into reflow soldering and is carried out Reflow Soldering, and Reflow Soldering temperature controls at 245 DEG C ± 2 DEG C, makes the first chip and intermediary substrate and the second chip weld with the electrical connection between intermediary substrate and filler is solidified;
(8) routing, mates intermediary substrate with substrate bonding line and couples together;
(9) plastic packaging;
(10) plant ball, tin ball bonding is connected on the outer contact of the packaging body after plastic packaging.
Above-mentioned DRAM dual chip stacking encapsulation method is copper transmission line in intermediary substrate, and adopting etch process in the circuit board shaping, is tin welding spot for connecting the surperficial salient point of the first chip and the second chip, adopts plating mode to be formed in the selected node of copper transmission line.
As can be seen from above scheme, according to the present invention, adopt intermediary substrate to transfer the first chip and the second chip in substrate, intermediary substrate reduces the constraint of transmission line, improves data long distance and transmits the problem brought, improve the electric property of encapsulation.Be different from during traditional DRAM encapsulates the feature of the gold thread camber existed above the second chip, only there is the bonding line between intermediary substrate and substrate in this programme, the second chip to have liquidated bonding line camber in substrate normal direction, decreases the whole height of packaging body.On the other hand, because packaging body only carries out a routing, decrease gold thread consumption, saved packaging cost thus.
Accompanying drawing explanation
Fig. 1 is according to a kind of DRAM dual chip encapsulating structure schematic diagram of the present invention.
Fig. 2 is known a kind of FOW film dual chip encapsulating structure schematic diagram.
Fig. 3 is known a kind of RDL dual chip encapsulating structure schematic diagram.
Fig. 4 is DRAM dual chip packaging technology flow chart, and wherein, a represents according to a kind of DRAM dual chip packaging technology flow chart of the present invention; B represents known a kind of FOW film dual chip packaging technology flow chart; C represents known a kind of RDL dual chip packaging technology flow chart.
Fig. 5 is a kind of intermediary substrate profile.
Fig. 6 is a kind of intermediary substrate plane graph.
In figure:
11a: the second chip; 12a: the first chip; 13a: intermediary substrate; 14a: intermediary substrate upper surface salient point; 15a: intermediary substrate lower surface salient point; 16a: substrate; 17a: gold thread; 18a: plastic packaging material; 19a: elargol; 110a: soldered ball; 111a: filler;
11b: the second chip; 12b: the first chip; 13b:FOW film; 14b: substrate; 15b: gold thread; 16b: plastic packaging material; 17b: soldered ball; 18b: elargol;
11c: the second chip; 12c: the first chip; 13c:RDL layer and spacer; 14c: substrate; 15c: gold thread; 16c: plastic packaging material; 17c: soldered ball; 18c: elargol;
31: transmission line; 32: intermediary's upper surface salient point; 33: intermediary substrate lower surface salient point
41: pad on intermediary substrate; 42: earth connection; 43: power line; 44: holding wire.
Embodiment
With reference to Figure of description 1, some basic comprisings are comprised in figure, as being provided with the substrate 16a of substrate circuit, substrate 16a and external electrical connections as prefabricated tin ball 110a or pad, non-outside connection side is together packed together with packed stacking chip, the rectangle frame that the plastic packaging material specified by label 18a represents.
In the construction shown in fig. 1, part also comprises the first chip 12a, second chip 11a, intermediary substrate 13a, for connecting the elargol 19a of the first chip 12a and substrate 16a, be filled on intermediary substrate 13a and the filler 111a(between the first chip 12a and the second chip 11a, last one deck, guide with two lines in FIG), also comprise the gold thread 17a as bonding line.In content below, its composition and structure thereof are described in detail.
In a kind of DRAM dual chip stack package structure shown in Fig. 1, described first chip 12a is mounted on described substrate 16a precalculated position, in the construction shown in fig. 1, and the structure of the stacked vertical of employing, the first chip 12a and substrate 16a common normal.
The active face of wherein said first chip 12a is the opposite face in attachment face, be to be understood that, attachment face and above-mentioned attachment adapt, be to be understood that simultaneously, in semiconductor chip, usual plate, sheet macroscopically have two faces, above substrate 16a as shown in Figure 1 has and below, above first chip 12a also has and below, its in FIG be active face above.Like this, the first chip 12a mounts on substrate 16a again, and form mechanical support, both are not directly electrically connected.
There is an intermediary device in the construction shown in fig. 1, namely by intermediary substrate 13a that bonding line and described substrate 16a are electrically connected, bonding line can use gold thread 17a as shown in Figure 1, silver-colored line or copper cash, at this, the bonding line met required for bonding obviously also can be applied with this programme.
Intermediary substrate 13a plays the effect of transfer, be to be understood that, as basic class device, it should be formed with circuit, owing to not relating to the improvement of himself herein, it only needs the connection of interposer 16a and the first chip 12a and the second chip 11a, and those skilled in the art is easy understand annexation in logic accordingly.
And then the first surface of intermediary substrate 13a, namely intermediary substrate is electrically connected at the bottom surface of Fig. 1 and described first chip 12a, and second relative with first surface on intermediary substrate 13a is then electrically connected with the active face of described second chip 11a.
The active face of chip and the wiring side of substrate should have certain isolation, it can be space isolation, namely air insulated, but this construction machine intensity is low, for this reason, in the construction shown in fig. 1, leave between described intermediary substrate 13a and the first chip 12a, the second chip 11a and fill gap, thus form packed layer after filling gap-fill filler 111a also solidification.In such an embodiment, intermediary substrate 13a also serves as the effect improving packaging body overall mechanical properties, and especially under encapsulation condition, the coated formation of the packed body of intermediary substrate 13a reliably connects, positive mechanical in the middle of being formed supports, and ensures packaging body long term reliability.
Adopt plastic package process can form plastic packaging layer with the erosion avoiding chip to be subject to external mechanical impact and environment in chip surrounding.Soldered ball 110a is positioned at the below of substrate 16a as packaging body input/output end port.
About described intermediary substrate 13a and the connection between the first chip 12a and the first chip 11a, gold thread bonding can be adopted, after packed layer is formed, also can ensure required mechanical strength, and distance is shorter, can not produce too large problem to the transmission of data.But in order to improve the mechanical performance of packaging body, and the problem that the long-distance transmissions improving data is brought, Intermediate substrate 13a is the wiring board based on flip-chip (Flipchip), correspondingly be formed for electrically and the first surface salient point of mechanical connection and second salient point on described first surface and second, intermediary substrate upper surface salient point 14a as shown in Figure 1 and intermediary substrate lower surface salient point 15a, be generally tin ball, Area of bearing is large.
Flipchip, also known as flip-chip, is a kind of without pin configuration, generally containing circuit unit.Be designed for the tin ball (conductive adhesive covered) be positioned on its face by right quantity, on electrically and be mechanically connected to circuit.
Flip-chip is deposit tin shot on I/Opad, then tin shot chip upset being added heat utilization melting this technology that combines with ceramic machine plate is replaced conventional routing and is engaged, become following encapsulation main flow gradually, current be mainly used in high clock pulse CPU, GPU (GraphicProcessorUnit) and the product such as Chipset be main.Compared with COB, direction down for the chip structure of this packing forms and I/O end (tin ball), because I/O exit is distributed in whole chip surface, therefore Flipchip reaches peak in packaging density and processing speed, particularly it can adopt the means of similar SMT technology to process, and is therefore the final direction of chip encapsulation technology and high-density installation.
The existence of the two-sided salient point of intermediary substrate 13a reduces distributed capacitance, thus improves data long distance and transmit the problem brought, and improves the electric property of encapsulation.
Form the transmission line be made up of wire in described intermediary substrate, the wiring on natural wiring board is generally conductor strip, identifies with width.Transmission line adopts copper transmission line here, also can adopt with same resistivity close, the metal wire that cost is close.
In the structure shown in Fig. 6, the layout of transmission line can clearly illustrate out, and its starting point is connected to corresponding first surface salient point or second salient point, and is formed with the pad for bonding line described in bonding at the end of transmission line.
Transmission line type is different, as copper transmission line, it can have different width according to concrete purposes, can reduce inductive sensor between the resistance of wire and wire, improve the noise characteristic of packaged chip simultaneously by the copper line width increasing power line 43 and earth connection 42; Accordingly, the copper line width reducing holding wire 44 can reduce parasitic capacitance between circuit, thus improves the Signal transmissions of circuit.
If the first chip is different from the second chip, surperficial salient point is connected with each self-corresponding pad respectively; If the first chip is identical with the second chip, both holding wire 44, power line 43 etc. can be connected on same pad, are formed and connect.
Simultaneously, because chip signal realizes being connected through gold thread and bottom substrate via after intermediary substrate again, compared to traditional double chip package, gold thread length significantly reduces, avoid signal long-distance transmission (as the gold thread of the second chip to substrate connects), thus reduce parasitic capacitance and stray inductance, improve the high-frequency transmission performance of packaging body.
For being conducive to encapsulation, intermediary substrate 13a size can be determined by the first chip 12a and the second chip 11a size, if first and second chip size is identical, intermediary substrate 13a size and chip size are longitudinally than being 1:1, laterally than being 1.05-1.15:1, if the first chip 12a size is large compared with the second chip 11a size, then intermediary substrate 13a size and the first chip 12a size are longitudinally than being 1:1, laterally than being 1:1.As shown in Figure 1, intermediary substrate 13a will be a bit larger tham two chips, is used for the connection of bonding line on the one hand, can produce middle basic point on the other hand because of plastic packaging, improves overall mechanical strength.
In the packaging technology shown in 4 left sides, mate the encapsulation of above-mentioned packaging body, it comprises the following steps:
Step 21a, brush coating, by elargol brush on substrate 16a, positional precision controls at 10-20 μm, prepares for mounting the first chip, and positional precision is the technical requirement ensureing electrical connection reliability, in lower defeated content, required positional precision should be ensured as much as possible.
Step 22a, pastes the first chip 12a, and be upwards mounted on substrate 16a by the first chip 12a active face, upper slice precision is 2-4 μm.
Step 23a, coating filler 111a, is coated in filler 111a on the first chip 12a active face.
Step 24a, paste intermediary substrate 13a, be mounted on by intermediary substrate 13a on the first chip 12a, positional precision is 2-4 μm.
Step 25a, coating filler 111a, is coated in filler on intermediary substrate 13a.
Step 26a, pastes the second chip 11a, is mounted on intermediary substrate 13a by the second chip 11a, and upper slice precision is 2-4 μm.
Step 27a, Reflow Soldering, carries out Reflow Soldering by the substrate 16a posting first, second chip and intermediary substrate 13a in reflow soldering, and Reflow Soldering temperature controls within 240 DEG C-260 DEG C, to realize the solidification of welding between each parts and filler.
Step 28a, routing, adopts thermosonic bonding to be coupled together by intermediary substrate 13a and substrate 16a gold thread 17a, bonding wire temperature 150 DEG C-170 DEG C, position of bonding wire precision 2-4 μm.
Step 29a, plastic packaging, the packaging body plastic packaging material plastic packaging completed by routing, plastic packaging temperature controls in 170 DEG C-185 DEG C.
Step 210a, plants ball, tin ball bonding is connected on the packaging body after plastic packaging.
Step 211a, cuts list.The combination of the packaging body of whole piece is cut into the form of single, this just has under the condition of whole piece encapsulation.
In foregoing, the two-sided intermediary substrate with salient point is similar to common BT (BismaleimideTriazine) resin circuit board, and existing substrate manufacture technique can be adopted to process.Substrate surface salient point can adopt the modes such as etching, plating and chemical vapour deposition (CVD) to obtain, and chip realizes interconnecting via above-mentioned salient point and intermediary substrate.Not there is circuit loop in intermediary substrate, but there is transmission line and the through hole of copper conductor formation in length and breadth, as Passive components for the first chip and the second chip provide data, power supply and ground connection transmission channel.The end of transmission line is metal pad, to be connected with bottom substrate by gold thread.
The above embodiment is the technical conceive of this patent, and the usual change that those skilled in the art carry out in the art of this patent aspects and replacement all should be included in the protection range of this patent.
Claims (2)
1. a DRAM dual chip stacking encapsulation method, is characterized in that, comprises the following steps:
(1) brush coating, mate the mounting position of the first chip (12a) on substrate (16a) and carry out brush coating, positional precision should control in 15 μm;
(2) paste the first chip (12a), the opposite face of the first chip (12a) active face is mounted on described mounting position, upper slice precision controlling is in 3 μm;
(3) apply filler, the filler of coating predetermined thickness is in the active face of the first chip (12a), and the exposed part electrically for being electrically connected;
(4) paste intermediary substrate (13a), intermediary substrate (13a) is mounted on form first chip (12a) of filling basic unit active face on, coupling electrical connection, upper slice precision controlling is in 3 μm;
(5) apply filler, the filler of coating predetermined thickness mounts on the opposite face of (12a) of the first chip in intermediary substrate (13a), and the exposed part for being electrically connected;
(6) mount the second chip, be mounted on by the second chip (11a) on intermediary substrate (13a), form electrical connection, upper slice precision controlling is in 3 μm;
(7) Reflow Soldering, structure after completing steps (6) is sent into reflow soldering and is carried out Reflow Soldering, and Reflow Soldering temperature controls at 245 DEG C ± 2 DEG C, makes the first chip and intermediary substrate and the second chip weld with the electrical connection between intermediary substrate and filler is solidified;
(8) routing, mates intermediary substrate (13a) and substrate (16a) with bonding line and couples together;
(9) plastic packaging;
(10) plant ball, tin ball bonding is connected on the outer contact of the packaging body after plastic packaging.
2. DRAM dual chip stacking encapsulation method according to claim 1, it is characterized in that, be copper transmission line in intermediary substrate (13a), adopt etch process in the circuit board shaping, being tin welding spot for connecting the surperficial salient point of the first chip and the second chip, adopting plating mode to be formed in the selected node of copper transmission line.
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| CN105742283B (en) * | 2016-02-29 | 2018-01-30 | 三星半导体(中国)研究开发有限公司 | It is inverted stack package |
| CN106449612A (en) * | 2016-08-23 | 2017-02-22 | 武汉寻泉科技有限公司 | Stacking and packaging structure for memory chips |
| CN110783210A (en) * | 2019-10-30 | 2020-02-11 | 华天科技（西安）有限公司 | Two-side packaged storage product packaging structure and manufacturing method |
| CN111224317B (en) * | 2020-04-20 | 2021-03-19 | 深圳市汇顶科技股份有限公司 | Laser emitting device |
| CN111498791A (en) * | 2020-04-30 | 2020-08-07 | 青岛歌尔微电子研究院有限公司 | Micro-electro-mechanical system packaging structure and manufacturing method thereof |
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| CN101256997A (en) * | 2008-03-05 | 2008-09-03 | 日月光半导体制造股份有限公司 | Encapsulation structure capable of reducing encapsulation stress |
| CN203277377U (en) * | 2013-04-23 | 2013-11-06 | 山东华芯半导体有限公司 | DRAM (dynamic random access memory) double-chip stack packaging structure |
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| US6937477B2 (en) * | 2004-01-21 | 2005-08-30 | Global Advanced Packaging Technology H.K. Limited | Structure of gold fingers |
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| CN101256997A (en) * | 2008-03-05 | 2008-09-03 | 日月光半导体制造股份有限公司 | Encapsulation structure capable of reducing encapsulation stress |
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