CN103236425A - DRAM (dynamic random access memory) double-chip stacking and packaging structure and packaging technology - Google Patents
DRAM (dynamic random access memory) double-chip stacking and packaging structure and packaging technology Download PDFInfo
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Abstract
The invention discloses a DRAM (dynamic random access memory) double-chip stacking and packaging structure and packaging technology. According to the invention, an intermediary substrate is used for connecting a first chip and a second chip onto the substrate; restriction on a transmission line caused by the intermediary substrate is reduced; problems brought by the long-distance transmission of data are eliminated; and the packaging electrical properties are improved. The scheme is characterized in that only a bonding wire between the intermediary substrate and the substrate exists, thus being different from the characteristic of a gold wire slack above the second chip in the traditional DRAM package, the bonding wire slack is hedged by the second chip on the normal of the substrate, and the integral height of a packaging body is reduced. Due to the fact that the packaging body is only routed once, the gold wire use amount is reduced, and therefore the packaging cost is saved.
Description
Technical field
The present invention relates to a kind of DRAM twin-core sheet stack package structure and packaging technology, DRAM is the abbreviation of Dynamic Random Access Memory, i.e. dynamic random access memory.
Background technology
Modern society's amount of information explosive increase, too busy to get away electronic product-especially the fast development of consumer electronics product reaches and popularizes, and electronic product miscellaneous has brought facility for people's life, study, work.
Along with the raising that the continuous development of science and technology and consumer require electronic product, mobile phone and the continuous diversification of other consumer electronics functions, performance fast lifting, speed improve constantly, and size strides forward towards light, thin, short, little trend.For this reason, integrated circuit by following two kinds of approach to dwindle small product size and to alleviate product weight, first kind is SOC(System On Chip), it is system level chip, memory, processor, analog circuit, digital circuit, interface circuit etc. are integrated on the chip, to realize functions such as voice, image, data processing; Second kind is SIP(System in package), i.e. system in package is combined in the integrated circuit (IC) chip of multiple function in the packaging body, to realize and the SOC identical functions.
With regard to the integrated circuit encapsulation technology, for satisfying compact design concept, having occurred with stacked package, TSV, CSP and WLP is the advanced packing forms of representative.Chip-stacked encapsulation is a kind of as 3D encapsulation, and characteristics with better function with it, that cost performance is higher replace traditional single-chip package gradually, has complied with electronic product to the trend of high integration, multi-functional and miniaturization development.Nearest semiconductor equipment and materials international (SEMI) and TechSearch International research report show, chip-stacked encapsulation in from 2008 to 2010 is expected to the growth rate development with average annual 12%, yet, manufacture view is but in the face of a challenge, be exactly that chip goes to put challenge with the material aspect, and become increasingly conspicuous, be that traditional chip load adhesive process can not provide enough mechanical support, production capacity and yields for ultra-thin chip as the load film.
The encapsulation of twin-core sheet is a kind of simple stacked package, some traditional packaging technologies are available reluctantly, encapsulate for this type, be subjected to each chip must have the data transmission channel (as input/output interface) of oneself, and must be equipped with support the influence of the power circuit of its circuit function, make its structure and traditional encapsulated object have comparatively significantly and distinguish.
At present, traditional DRAM twin-core chip package mainly contains two kinds: one for adopting FOW(Film Over Wire) the twin-core sheet encapsulation of film, it is the immediate a kind of packaging technology of a kind of and traditional load film packaging technology, the FOW film integrates the function of load bellows scribing film, its encapsulating structure as shown in Figure 2, the main feature of this structure is for need not the FOW material that hot curing is handled after the load, the disk layer adheres to FOW film 13b and goes up scribing, the first chip 12b and the second chip 11b load then, bonding and plastic packaging then go between.In structure shown in Figure 2, gold thread 15b amount ratio as bonding line is bigger, cause cost higher, and there is certain gold thread camber in the gold thread 15b that is used for the bonding second chip 11b, as label 15b among Fig. 2 the gold thread that directly guides, cause plastic packaging material 16b consumption big, and further cause packaging body integral body thick partially.
Another kind of traditional DRAM twin-core sheet is encapsulated as the twin-core sheet encapsulation that wafer carries out RDL (Redistribution layer), as shown in Figure 3, this encapsulating structure and last a kind of encapsulating structure have certain similitude, comparison diagram 2 and Fig. 3, its gold thread 15c will lack than the gold thread 15b shown in Fig. 2 as can be seen.But its major defect is that wafer RDL expense is higher, causes packaging cost to increase.Also there be the whole partially thick defective the same with last a kind of encapsulating structure in it simultaneously.
Two kinds of twin-core chip packages of comprehensive above-mentioned traditional DRAM, both must place FOW film or spacer chip to support second chip in bottom and second chip.Simultaneously, some stacked package adopts the intermediary layer with conductive through hole, pour into copper as interface channel as opening in the silicon chip in hole and the through hole, this type of technology realizes that not only difficulty is big, and copper and intermediary's material thermal expansion coefficient do not match and may cause breaking away from the copper heating process intermediary layer and cause package reliability poor.
Summary of the invention
Cost height in traditional DRAM twin-core sheet stacked package, packaging body thickness are big in order to improve, the problem of poor reliability and poor electrical performance, the object of the present invention is to provide and a kind ofly use the less DRAM twin-core sheet stack package structure of bonding line, and a kind of packaging technology of this encapsulating structure is provided.
The present invention is by the following technical solutions:
One aspect of the present invention, a kind of DRAM twin-core sheet stack package structure is provided, comprise first chip, second chip and be provided with the substrate of substrate circuit, described first chip attachment is in described substrate precalculated position, and the active face of this first chip is the opposite face of the face that mounts; First of the intermediary substrate that is electrically connected by bonding line and described substrate is electrically connected with described first chip, and relative with first second then is electrically connected with the active face of described second chip on the intermediary substrate.
Above-mentioned DRAM twin-core sheet stack package structure, described intermediary substrate and first chip, second chip chamber leave fills the gap, thereby fills filler in the filling gap and solidify back formation packed layer.
Above-mentioned DRAM twin-core sheet stack package structure, described intermediary substrate correspondingly are formed with for electric and first salient point and second salient point mechanical connection at described first and second based on the wiring board of flip-chip.
Above-mentioned DRAM twin-core sheet stack package structure, described first salient point and second salient point are the tin ball that forms in the select location deposition.
Above-mentioned DRAM twin-core sheet stack package structure is formed with the transmission line that lead constitutes in the described intermediary substrate, the starting point of transmission line is connected to corresponding first salient point or second salient point, and is formed with pad for the described bonding line of bonding at the end of transmission line.
Above-mentioned DRAM twin-core sheet stack package structure, as the width of the described transmission line of power line or earth connection greater than the width as the transmission line of holding wire.
Above-mentioned DRAM twin-core sheet stack package structure, if first chip is identical with second chip size, then intermediary substrate is 1:1 with vertical ratio of first chip, laterally than being 1.05:1 ~ 1.15:1; If the size of first chip is greater than the size of second chip, then intermediary substrate is 1:1 with vertical ratio of first chip, laterally than being 1:1.
According to another aspect of the present invention, a kind of DRAM twin-core sheet stacking encapsulation method is provided, may further comprise the steps:
(1) brush coating mates the mount position of first chip on substrate and carries out brush coating, and positional precision should be controlled in 15 μ m;
(2) paste first chip, the opposite face of the first chip active face is mounted on the described position that mounts, last slice precision control is in 3 μ m;
(3) coating filler applies the filler of predetermined thickness in the active face of first chip, and exposed electric be used to the part that is electrically connected;
(4) paste intermediary substrate, intermediary substrate is mounted on the active face that forms first chip of filling basic unit, coupling is electrically connected, and last slice precision is controlled in 3 μ m;
(5) coating filler, the filler of coating predetermined thickness in intermediary substrate mount first chip opposite face on, and the exposed part that is electrically connected of being used for;
(6) mount second chip, on intermediary substrate, formation is electrically connected with second chip attachment, and last slice precision is controlled in 3 μ m;
(7) Reflow Soldering, the structure behind the completing steps are sent into reflow soldering and are carried out Reflow Soldering, and the Reflow Soldering temperature is controlled at 245 ℃ ± 2 ℃, make being electrically connected welding and filler is solidified between first chip and intermediary substrate and second chip and intermediary substrate;
(8) routing couples together intermediary substrate and substrate with the bonding line coupling;
(9) plastic packaging;
(10) plant ball, the tin ball bonding is connected on the outer contact of packaging body behind the plastic packaging.
Be the copper transmission line in the above-mentioned DRAM twin-core sheet stacking encapsulation method, intermediary substrate, adopt the etch process moulding in the circuit board, the surperficial salient point that is used for connection first chip and second chip is tin welding spot, adopts plating mode to be formed on the selected node of copper transmission line.
From above scheme as can be seen, according to the present invention, adopt intermediary substrate to transfer first chip and second chip in substrate, intermediary substrate reduces the constraint of transmission line, has improved the problem that the data long distance transmission brings, and has improved the electric property of encapsulation.Be different from the characteristics of the gold thread camber that second chip top exists in the traditional DRAM encapsulation, only have the bonding line between intermediary substrate and the substrate in this programme, second chip has reduced the whole height of packaging body in the substrate normal direction bonding line camber that liquidated.On the other hand, because packaging body only carries out routing one time, reduce the gold thread consumption, saved packaging cost thus.
Description of drawings
Fig. 1 is according to a kind of DRAM twin-core chip package schematic diagram of the present invention.
Fig. 2 is known a kind of FOW film twin-core chip package schematic diagram.
Fig. 3 is known a kind of RDL twin-core chip package schematic diagram.
Fig. 4 is DRAM twin-core sheet packaging technology flow chart, and wherein, a represents according to a kind of DRAM twin-core sheet packaging technology flow chart of the present invention; B represents known a kind of FOW film twin-core sheet packaging technology flow chart; C represents known a kind of RDL twin-core sheet packaging technology flow chart.
Fig. 5 is a kind of intermediary substrate profile.
Fig. 6 is a kind of intermediary substrate plane graph.
Among the figure:
11a: second chip; 12a: first chip; 13a: intermediary substrate; 14a: intermediary substrate upper surface salient point; 15a: intermediary substrate lower surface salient point; 16a: substrate; 17a: gold thread; 18a: plastic packaging material; 19a: elargol; 110a: soldered ball; 111a: filler;
11b: second chip; 12b: first chip; The 13b:FOW film; 14b: substrate; 15b: gold thread; 16b: plastic packaging material; 17b: soldered ball; 18b: elargol;
11c: second chip; 12c: first chip; 13c:RDL layer and spacer; 14c: substrate; 15c: gold thread; 16c: plastic packaging material; 17c: soldered ball; 18c: elargol;
31: transmission line; 32: intermediary's upper surface salient point; 33: intermediary substrate lower surface salient point
41: pad on the intermediary substrate; 42: earth connection; 43: power line; 44: holding wire.
Embodiment
With reference to Figure of description 1, comprise some basic comprisings among the figure, as be provided with the substrate 16a of substrate circuit, substrate 16a be connected with external electric as prefabricated tin ball 110a or pad, non-outside to connect side together packed together with the packed chip that piles up, the rectangle frame of being represented by the specified plastic packaging material of label 18a.
In structure shown in Figure 1, part also comprises the first chip 12a, the second chip 11a, intermediary substrate 13a, be used for connecting the elargol 19a of the first chip 12a and substrate 16a, be filled in last, the last one deck of filler 111a(between intermediary substrate 13a and the first chip 12a and the second chip 11a, in Fig. 1, guide with two lines), also comprise the gold thread 17a as bonding line.In the content below its composition and structure thereof are described in detail.
In a kind of DRAM twin-core sheet stack package structure shown in Figure 1, the described first chip 12a is mounted on described substrate 16a precalculated position, in structure shown in Figure 1, and the structure of the stacked vertical of employing, the first chip 12a and substrate 16a common normal.
The active face of the wherein said first chip 12a is the opposite face of the face that mounts, be to be understood that, mount face and above-mentioned mounting adapts, be to be understood that simultaneously, in semiconductor chip, usually on plate, the sheet macroscopic view two faces are arranged, above substrate 16a as shown in fig. 1 has and below, above the first chip 12a also has and below, it is active face above in Fig. 1.Like this, the first chip 12a mounts on the substrate 16a again, forms mechanical support, and both directly are not electrically connected.
In structure shown in Figure 1, there is an intermediary device, the intermediary substrate 13a that is electrically connected by bonding line and described substrate 16a just, bonding line can use gold thread 17a as shown in Figure 1, silver-colored line or copper cash, at this, satisfy the needed bonding line of bonding obviously also can use with this programme in.
And then first of intermediary substrate 13a, just intermediary substrate is electrically connected at bottom surface and the described first chip 12a of Fig. 1, and intermediary substrate 13a goes up relative with first second and then is electrically connected with the active face of the described second chip 11a.
The active face of chip and the wiring side of substrate should have certain isolation, can be that the space isolates, air insulated just, but this construction machine intensity is low, for this reason, in structure shown in Figure 1, leave between described intermediary substrate 13a and the first chip 12a, the second chip 11a and fill the gap, thereby fill filler 111a in the filling gap and solidify back formation packed layer.In this structure, intermediary substrate 13a also serves as the effect that improves the packaging body overall mechanical properties, and especially under the encapsulation condition, the packed body of intermediary substrate 13a coats and forms reliable the connection, positive mechanical in the middle of forming supports, and guarantees the packaging body long term reliability.
Adopt plastic package process around chip, to form the plastic packaging layer and be subjected to the erosion of extraneous mechanical shock and environment to avoid chip.Soldered ball 110a is positioned at the below of substrate 16a as the packaging body input/output end port.
About being connected between described intermediary substrate 13a and the first chip 12a and the first chip 11a, can adopt the gold thread bonding, also can guarantee necessary mechanical strength after packed layer forms, and distance is shorter, can not produce too big problem to the transmission of data.But in order to improve the mechanical performance of packaging body, and the problem that the long-distance transmissions of improving data is brought, Intermediate substrate 13a is the wiring board based on flip-chip (Flip chip), correspondingly be formed with for electric and first salient point and second salient point mechanical connection at described first and second, intermediary substrate upper surface salient point 14a as shown in Figure 1 and intermediary substrate lower surface salient point 15a, generally be the tin ball, Area of bearing is big.
Flip chip claims flip-chip again, is a kind of no pin configuration, generally contains circuit unit.Be designed for the tin ball (conductive adhesive covers) on its face of being positioned at by right quantity, on electric and mechanically be connected in circuit.
Flip-chip is deposit tin shot on I/O pad, the tin shot that then chip upset is added the heat utilization fusion this technology that combines with the ceramic machine plate is replaced conventional routing joint, become following encapsulation main flow gradually, products such as current CPU, the GPU (Graphic Processor Unit) that is mainly used in high clock pulse and Chipset are main.Compare with COB, direction down for the chip structure of this packing forms and I/O end (tin ball), because the I/O exit is distributed in the entire chip surface, so Flip chip has reached the peak on packaging density and processing speed, particularly it can adopt the means of similar SMT technology to process, and is the final direction of chip encapsulation technology and high-density installation therefore.
The existence of the two-sided salient point of intermediary substrate 13a has reduced distributed capacitance, thereby has improved the problem that the data long distance transmission brings, and has improved the electric property of encapsulation.
Form the transmission line that is made of lead in the described intermediary substrate, the wiring on the natural wiring board generally is conductor strip, identifies with width.Transmission line adopts the copper transmission line here, also can adopt and approach with resistivity, the metal wire that cost is approaching.
In structure shown in Figure 6, the layout of transmission line can clearly illustrate out, and its starting point is connected to corresponding first salient point or second salient point, and is formed with pad for the described bonding line of bonding at the end of transmission line.
Transmission line type is different, as the copper transmission line, it can have different width according to concrete purposes, can reduce inductive sensor between the resistance of lead and lead by the copper line width that increases power line 43 and earth connection 42, improves the noise characteristic of packaged chip simultaneously; Accordingly, the copper line width that reduces holding wire 44 can reduce parasitic capacitance between circuit, thereby improves the signal transmission of circuit.
If first chip is different with second chip, surperficial salient point links to each other with corresponding bonding pad separately respectively; If first chip is identical with second chip, both holding wires 44, power line 43 etc. can be connected on the same pad, form and connect.
Simultaneously, because chip signal is via realizing being connected through gold thread and bottom substrate again after the intermediary substrate, encapsulate compared to the traditional double chip, gold thread length significantly reduces, avoided signal long-distance transmission (connecting as the gold thread of second chip to substrate), reduce parasitic capacitance and stray inductance thus, improved the high-frequency transmission performance of packaging body.
For being conducive to encapsulation, intermediary substrate 13a size can be determined by the first chip 12a and the second chip 11a size, if first and second chip size is identical, intermediary substrate 13a size is vertical than being 1:1 with chip size, laterally than being 1.05-1.15:1, if the first chip 12a size is big than the second chip 11a size, then intermediary substrate 13a size is vertical than being 1:1, laterally than being 1:1 with the first chip 12a size.As shown in Figure 1, intermediary substrate 13a will be a bit larger tham two chips, is used for the connection of bonding line on the one hand, and basic point in the middle of can producing because of plastic packaging on the other hand improves whole mechanical strength.
In the packaging technology shown in 4 left sides, mate the encapsulation of above-mentioned packaging body, it may further comprise the steps:
In the foregoing, two-sided intermediary substrate with salient point is similar to common BT (Bismaleimide Triazine) resin circuit board, can adopt existing substrate manufacture technology to process.The substrate surface salient point can adopt modes such as etching, plating and chemical vapour deposition (CVD) to obtain, and chip is realized interconnection via above-mentioned salient point and intermediary substrate.Do not have circuit loop in the intermediary substrate, but the transmission line and the through hole that exist copper conductor in length and breadth to constitute, provide data, power supply and ground connection transmission channel as passive components and parts for first chip and second chip.The end of transmission line is metal pad, to be connected with bottom substrate by gold thread.
The above embodiment is the technical conceive of this patent, and the common variation that those skilled in the art carry out in the art of this patent scheme scope and replacement all should be included in the protection range of this patent.
Claims (9)
1. DRAM twin-core sheet stack package structure, comprise first chip (12a), second chip (11a) and be provided with the substrate (16a) of substrate circuit, it is characterized in that, described first chip (12a) is mounted on described substrate (16a) precalculated position, and the active face of this first chip (12a) is the opposite face of the face that mounts; First of the intermediary substrate (13a) that is electrically connected by bonding line and described substrate (16a) is electrically connected with described first chip (12a), and intermediary substrate (13a) is gone up relative with first second and then is electrically connected with the active face of described second chip (11a).
2. DRAM twin-core sheet stack package structure according to claim 1, it is characterized in that, leave between described intermediary substrate (13a) and first chip (12a), second chip (11a) and fill the gap, thereby fill filler (111a) in the filling gap and solidify back formation packed layer.
3. DRAM twin-core sheet stack package structure according to claim 1 and 2, it is characterized in that, described intermediary substrate correspondingly is formed with for electric and first salient point and second salient point mechanical connection at described first and second based on the wiring board of flip-chip.
4. DRAM twin-core sheet stack package structure according to claim 4 is characterized in that, described first salient point and second salient point are the tin ball that forms in the select location deposition.
5. DRAM twin-core sheet stack package structure according to claim 4, it is characterized in that, form the transmission line that is constituted by lead in the described intermediary substrate, the starting point of transmission line is connected to corresponding first salient point or second salient point, and is formed with pad for the described bonding line of bonding at the end of transmission line.
6. DRAM twin-core sheet stack package structure according to claim 5 is characterized in that, as the width of the described transmission line of power line or earth connection greater than the width as the transmission line of holding wire.
7. DRAM twin-core sheet stack package structure according to claim 1, it is characterized in that, if first chip (12a) is measure-alike with second chip (11a), then intermediary substrate (13a) is 1:1 with vertical ratio of first chip, laterally than being 1.05:1 ~ 1.15:1; If the size of first chip (12a) is greater than the size of second chip, then intermediary substrate (13a) is 1:1 with vertical ratio of first chip (12a), laterally than being 1:1.
8. a DRAM twin-core sheet stacking encapsulation method is characterized in that, may further comprise the steps:
(1) brush coating mates the mount position of first chip (12a) on substrate (16a) and carries out brush coating, and positional precision should be controlled in 15 μ m;
(2) paste first chip (12a), the opposite face of first chip (12a) active face is mounted on the described position that mounts, last slice precision control is in 3 μ m;
(3) coating filler applies the filler of predetermined thickness in the active face of first chip (12a), and exposed electric be used to the part that is electrically connected;
(4) paste intermediary substrate (13a), intermediary substrate (13a) is mounted on the active face that forms first chip (12a) of filling basic unit, coupling is electrically connected, and last slice precision is controlled in 3 μ m;
(5) coating filler, the filler of coating predetermined thickness mounts in intermediary substrate (13a) on the opposite face of (12a) of first chip, and the exposed part that is electrically connected of being used for;
(6) mount second chip, second chip (11a) is mounted on the intermediary substrate (13a), formation is electrically connected, and last slice precision is controlled in 3 μ m;
(7) Reflow Soldering, the structure behind the completing steps (6) are sent into reflow soldering and are carried out Reflow Soldering, and the Reflow Soldering temperature is controlled at 245 ℃ ± 2 ℃, make being electrically connected welding and filler is solidified between first chip and intermediary substrate and second chip and intermediary substrate;
(8) routing couples together intermediary substrate (13a) and substrate (16a) with the bonding line coupling;
(9) plastic packaging;
(10) plant ball, the tin ball bonding is connected on the outer contact of packaging body behind the plastic packaging.
9. DRAM twin-core sheet stacking encapsulation method according to claim 8, it is characterized in that, be the copper transmission line in the intermediary substrate (13a), adopt the etch process moulding in the circuit board, the surperficial salient point that is used for connection first chip and second chip is tin welding spot, adopts plating mode to be formed on the selected node of copper transmission line.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105742283A (en) * | 2016-02-29 | 2016-07-06 | 三星半导体(中国)研究开发有限公司 | Inverted stacked package |
| CN106449612A (en) * | 2016-08-23 | 2017-02-22 | 武汉寻泉科技有限公司 | Stacking and packaging structure for memory chips |
| CN110783210A (en) * | 2019-10-30 | 2020-02-11 | 华天科技（西安）有限公司 | Two-side packaged storage product packaging structure and manufacturing method |
| CN111224317A (en) * | 2020-04-20 | 2020-06-02 | 深圳市汇顶科技股份有限公司 | Laser emitting device |
| CN111498791A (en) * | 2020-04-30 | 2020-08-07 | 青岛歌尔微电子研究院有限公司 | Micro-electro-mechanical system packaging structure and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5438224A (en) * | 1992-04-23 | 1995-08-01 | Motorola, Inc. | Integrated circuit package having a face-to-face IC chip arrangement |
| US20050156303A1 (en) * | 2004-01-21 | 2005-07-21 | Kai-Chiang Wu | Structure of gold fingers |
| CN101256997A (en) * | 2008-03-05 | 2008-09-03 | 日月光半导体制造股份有限公司 | Encapsulation structure capable of reducing encapsulation stress |
| CN203277377U (en) * | 2013-04-23 | 2013-11-06 | 山东华芯半导体有限公司 | DRAM (dynamic random access memory) double-chip stack packaging structure |
-
2013
- 2013-04-23 CN CN201310142301.3A patent/CN103236425B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5438224A (en) * | 1992-04-23 | 1995-08-01 | Motorola, Inc. | Integrated circuit package having a face-to-face IC chip arrangement |
| US20050156303A1 (en) * | 2004-01-21 | 2005-07-21 | Kai-Chiang Wu | Structure of gold fingers |
| CN101256997A (en) * | 2008-03-05 | 2008-09-03 | 日月光半导体制造股份有限公司 | Encapsulation structure capable of reducing encapsulation stress |
| CN203277377U (en) * | 2013-04-23 | 2013-11-06 | 山东华芯半导体有限公司 | DRAM (dynamic random access memory) double-chip stack packaging structure |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105742283A (en) * | 2016-02-29 | 2016-07-06 | 三星半导体(中国)研究开发有限公司 | Inverted stacked package |
| CN105742283B (en) * | 2016-02-29 | 2018-01-30 | 三星半导体(中国)研究开发有限公司 | It is inverted stack package |
| CN106449612A (en) * | 2016-08-23 | 2017-02-22 | 武汉寻泉科技有限公司 | Stacking and packaging structure for memory chips |
| CN110783210A (en) * | 2019-10-30 | 2020-02-11 | 华天科技（西安）有限公司 | Two-side packaged storage product packaging structure and manufacturing method |
| CN111224317A (en) * | 2020-04-20 | 2020-06-02 | 深圳市汇顶科技股份有限公司 | Laser emitting device |
| CN111224317B (en) * | 2020-04-20 | 2021-03-19 | 深圳市汇顶科技股份有限公司 | Laser emitting device |
| CN111498791A (en) * | 2020-04-30 | 2020-08-07 | 青岛歌尔微电子研究院有限公司 | Micro-electro-mechanical system packaging structure and manufacturing method thereof |
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