CN103208934B - A kind of pulse width modulating switch power source controller and Switching Power Supply - Google Patents
A kind of pulse width modulating switch power source controller and Switching Power Supply Download PDFInfo
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- CN103208934B CN103208934B CN201210007648.2A CN201210007648A CN103208934B CN 103208934 B CN103208934 B CN 103208934B CN 201210007648 A CN201210007648 A CN 201210007648A CN 103208934 B CN103208934 B CN 103208934B
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Abstract
The present invention provides a kind of pulse width modulating switch power source controller and Switching Power Supply, belong to electronic integrated circuit technical field, it is widely used in PWM mode AC/DC switch power supply system, described PWM controller includes: FB sample circuit, current-mode selection circuit, side's wave generation circuit etc., after using this switch power controller, the self adaptation of system operating frequency under different loads can be realized, reduce Switching Power Supply stand-by power consumption.
Description
Technical field
The present invention relates to basic electronic circuit technical field, particularly to a kind of pulse width modulating switch power source controller
And Switching Power Supply.
Background technology
Under the trend that whole world environmental consciousness is the strongest, the energy is utilized to become the common recognition in the whole world more efficiently, in
It is that electronic product and power supply thereof start to be limited by energy-saving act, such as California, USA energy commission in recent years
(California Energy Commission, CEC) energy conservation criteria, and " Energy Star (Energy Star) " mark meter
Draw.In addition to these energy conservation criterias, another new criteria attracted attention is i.e. " stand-by power consumption ".According to statistics, electronics
Product power consumption when standby accounts for the electric power 3%-13% in the whole world, and therefore the power consumption when standby also works up clear and definite specification,
Low standby power loss characteristic maybe will become the essential basic demand of following power supply unit.Switching Power Supply (Switch Mode
Power Supply) with the performance of its excellence be widely applied occasion and occupy the pith in current power supply series market.
But, there is unavoidable loss energy in the course of the work due to Switching Power Supply, including switching loss, conduction loss and control
Circuit loss processed, and these loss all operating frequencies with system have much relations, especially when underloading or unloaded time, use with
Switching frequency identical under heavy condition can reduce the useful work ratio to total work largely, reduces efficiency.And along with
The rising of the Switching Power Supply operating frequency that product trend toward miniaturization is caused, the energy of loss is also continuously increased, and this becomes out
Close power-supply system main part of energy loss under underloading and holding state.
As can be seen here prior art exists: the problem that existing AC/DC Switching Power Supply stand-by power consumption is higher.
Summary of the invention
In order to solve the problems referred to above, it is an object of the invention to provide a kind of pulse width modulating switch power source controller and open
Closing power supply, pulse width modulating switch power source controller includes:
Supply voltage pin, grounding pin, feedback pin fb, control output end pin gate, current monitoring end pin cs
Port RI pin is set with bias current；And
FB sample circuit 202, its input port connects feedback pin fb, and size based on feedback pin fb feedback current,
Feedback current change is changed into voltage sampling signal FB_d and exports；
Current-mode selection circuit 203, the first input end of current-mode selection circuit 203 connects the output of sampled signal FB_d
End, and according to the voltage range of voltage sampling signal FB_d, produce corresponding agitator the first electric current Iosc1 and the second electric current
Iosc2；
Side's wave generation circuit 205, side's first input end of wave generation circuit 205, the second input, the 3rd input, the
Four-input terminal, the 5th input, the 6th input, connect the peak limited voltage of current monitoring end pin CS input voltage respectively
Vth1, current monitoring end pin CS, sampled signal FB_d outfan, the first reference voltage V ref1, agitator the first electric current
Iosc1 outfan and the second electric current Iosc2 outfan, the first output logic signal outfan of 205, the second output logic signal
Outfan, is connected respectively to the grid end of the first transistor N21 and transistor seconds N22, and 205 is defeated according to current monitoring end pin CS
Enter the peak limited voltage vth1 of voltage, current monitoring end pin CS signal, sampled signal FB_d, the first reference voltage V ref1,
Agitator the first electric current Iosc1 and the second electric current Iosc2 obtains first output logic signal and second of switch power controller
Output logic signal；
The grid end of the first transistor N21 is also clamped to the breakdown reverse voltage on ground through the first diode D23, first crystal
The drain terminal of pipe N21 is connected to supply voltage pin vdd terminal, and the source of transistor seconds N22 is connected to ground, the first transistor N21
Source be connected with the drain terminal of transistor seconds N22 after be connected to the control output end of described PWM switch power controller
GATE functional pin, described GATE functional pin end to one the first resistance R25 of ground series connection.
Further, the second input termination RI pin of current-mode selection circuit 203, and obtain reference current accordingly
Iref, 205 export clock square wave CLK, wherein, the second base always according to the first reference voltage V ref1 and the second reference voltage V ref2
Quasi-voltage Vref2 is the peak limited voltage vth1 of current monitoring end pin CS input voltage, also includes soft starting circuit 201,
The first input end of soft starting circuit 201 connects reference current Iref outfan, the second input terminated clock of soft starting circuit 201
Square wave CLK outfan, and under the control of output clock square wave CLK, use reference current Iref charging to make outfan increase
Peak limited voltage vth1 to current monitoring end pin CS input voltage.
Further, soft starting circuit 201 includes electric charge pump PUMP circuit, and described electric charge pump PUMP circuit input end is by vibrating
Device output square-wave signal CLK and reference current Iref co-controlling, its output voltage SS is connected to soft start and terminates comparator
COMP21 obtains positive input, selects control signal with the output of COMP21 negative input voltage vth1 result of the comparison, and 2 select 1
Control signal outfan is selected in the first input end selecting of selector, and according to selecting the control signal current monitoring end from input to draw
The peak limited voltage vth1 and electric charge pump PUMP circuit input voltage SS of foot CS input voltage selects, exports the second base
Quasi-voltage Vref2.
Further, FB sample circuit 202 also include the second diode D21, the 3rd diode D22, the second resistance R21,
Three resistance R22, the 4th resistance R23, the 5th resistance R24, the negative pole of described second diode D21 connects feedback pin fb, and with
The negative pole of two resistance R21 is connected, and the positive pole of the second diode D21 connects the negative pole of the 3rd resistance R22, and with the 3rd diode D22
Positive pole be connected, described second resistance R21 positive pole is connected with second source LVDD, the 3rd resistance R22 positive pole and second source
LVDD is connected, and the positive pole of the 4th resistance R23 and the negative pole of the 3rd diode D22 are connected, the negative pole of the 4th resistance R23 and the 5th electricity
The positive pole of resistance R24 is connected, and the negative pole of the 5th resistance R24 is connected to grounding pin.
Further, current-mode selection circuit 203 also includes: logic control voltage gating circuit 310, grounding lead foot are brilliant
Body pipe N34, agitator the first electric current Iosc1 end transistor P31, agitator the second electric current Iosc2 end transistor P32, the first ratio
Relatively device COMP31, hysteresis comparator COMP32, the first operational amplifier OP31, the second operational amplifier OP32, the 3rd computing are put
Big device OP33, the 6th resistance R31, the 3rd operational amplifier OP33 positive input is connected to 2V DC voltage, negative input
It is connected to RI pin together with outfan, and forms bias current Iref, the second computing by the outer meeting resistance R115 of RI pin
Amplifier OP32 positive input is connected to four reference voltage Vref _ L, and the second operational amplifier OP32 negative input is with defeated
Going out end and be connected to one end of the 6th resistance R31 together, the first operational amplifier OP31 positive input is connected to logic control electricity
The outfan Vs of pressure gating circuit 310, the first operational amplifier OP31 negative input is connected to the other end of the 6th resistance R31
With the source of grounding pin end transistor N34, the outfan of the first operational amplifier OP31 is connected to grounding pin end transistor
The grid end of N34；The drain terminal of grounding pin end transistor N34 is connected to the drain terminal of agitator the second electric current Iosc2 end transistor P32
With grid end Iosc2, it is brilliant that the source of agitator the second electric current Iosc2 end transistor P32 is connected to agitator the first electric current Iosc1 end
The grid end of body pipe P31 and drain terminal Iosc1, the source of agitator the first electric current Iosc1 end transistor P31 is connected to internal low-voltage electricity
Source LVDD, the first input pin of logic control voltage gating circuit 310 is connected with the outfan of COMP31；Second input pin
It is connected with the outfan of COMP32；3rd input pin is connected with the negative input Vref_H of COMP31；4th input pin
It is connected with the positive input FB_d of COMP31 and COMP32；The negative input Vref_B phase of the 5th input pin and COMP32
Even；The outfan of 310 is connected with the positive input of OP31；Wherein logic control voltage gating circuit 310 is for by judging
The voltage range of FB_d, exports different magnitudes of voltage,
When FB_d >=Vref_H when, Vs=Vref_H, Vref_H are the first reference voltage, agitator charging and discharging currentsAgitator sends out ripple with fixing operating frequency；
When Vref_H ＜ FB_d >=Vref_M-Vos when, Vs=FB_d, Vref_M are the 3rd reference voltage, agitator
Charging and discharging currentsThe operating frequency of agitator starts to reduce frequency along with the reduction of output loading
Rate；
When FB_d ＜ Vref_M-Vos when, Vs=Vref_B, Vref_B are the second reference voltage, agitator discharge and recharge
Electric currentUnder output loading underloading or Light Condition, agitator is intermittent with minimum frequency of operation
Send out ripple.
Further, logic control voltage gating circuit 310 includes: include third transistor N31, the 4th transistor N32,
Five transistor N33, the first phase inverter INV31, the second phase inverter INV32, first and door AND31, second with door AND32, the 3rd
With door AND33, the grid of described third transistor N31 connects the outfan of described first and door AND31, described third transistor
The source electrode of N31 meets the positive input Vs of the first operational amplifier OP31, and the drain electrode of described third transistor N31 connects the 3rd benchmark
The grid of voltage Vref_H, described 4th transistor N32 connects the outfan of described second and door AND32, described 4th transistor
The source electrode of N32 meets the positive input Vs of described first operational amplifier OP31, and the drain electrode of described 4th transistor N32 connects described
The sampled voltage FB_d of sampled signal FB_d outfan；The grid of described 5th transistor N33 connects the described 3rd with door AND33's
Outfan, the source electrode of described 5th transistor N33 meets the positive input Vs of described first operational amplifier OP31, and the described 5th
The drain electrode of transistor N33 connects the 4th reference voltage V ref_B；Described first phase inverter INV31's and the second phase inverter INV32
Outfan connects the input of second and door AND32 and the 3rd and door AND33 respectively；The output of described first comparator COMP31
Terminate input and an input of described first and door AND31, the described hysteresis comparator of described first phase inverter INV31
The output termination input of described second phase inverter INV32 of COMP32, described first with another input of door AND31 and
One input of described second and door AND32.
Further, side's wave generation circuit 205 includes:
Described CS peak point current comparator COMP22 positive input receives 2 output voltages selecting 1 selector in succession
Vref2, negative input connects the current monitoring end pin CS of described PWM switch power controller, described CS peak point current ratio
The outfan of relatively device is connected to an input of the first NAND gate I21；Described error comparator COMP23 positive input connects
To sampled signal FB_d outfan, negative input connects current monitoring end pin, the output of described error comparator COMP23
End is connected to another input of the first NAND gate I21；The outfan of the first not gate I21 connects rest-set flip-flop by logical device
R end, described rest-set flip-flop outfan control soft-sphere model circuit Soft Driver, soft-sphere model circuit output logic connect respectively
Grid end to the first transistor N21 and transistor seconds N22；
The input of described agitator OSC is connected with Vref1, Vref2, Iosc1 and Iosc2 signal, described agitator
Output is connected to the S end of rest-set flip-flop, and agitator OSC utilizes bias current Iosc1 and Iosc2 to agitator OSC internal capacitance
C41 charges, and when agitator OSC internal capacitance C41 voltage is more than Vref1, bias current Iosc1 and Iosc2 starts vibration
Device OSC internal capacitance C41 is discharged, and when agitator OSC capacitance voltage is less than Vref2, bias current Iosc1 and Iosc2 opens again
Beginning to charge agitator OSC internal capacitance C41, so circulation makes to be output as shaking square-wave signal.Described agitator OSC also determines
Determine the maximum functional dutycycle of described PWM switch power controller.
Further, agitator OSC includes: include the 6th transistor P41, the 7th transistor P42, the 8th transistor P43,
Nine transistor P44, the tenth transistor P45, the 11st transistor N41, the tenth two-transistor N42, the 13rd transistor N43,
14 transistor N44, the 15th transistor N45, agitator OSC internal capacitance C41, the second comparator COMP41, the 3rd compare
Device COMP42, the 4th with door AND41, the 5th and door AND42, the 3rd phase inverter INV41, the 4th phase inverter INV42, the 5th anti-phase
Device INV43, hex inverter INV44 and the 7th phase inverter INV45；
The grid of described 6th transistor P41 meets bias voltage Iosc1, and the source electrode of described 6th transistor P41 connects described
The drain electrode of the second voltage source LVDD, described 6th transistor P41 connects the source electrode of described 7th transistor P42；
The grid of described 7th transistor P42 meets bias voltage Iosc2, and the drain electrode of described 7th transistor P42 connects described
The drain electrode of the 6th transistor N42, the grid of described 6th transistor N42 and the grid of described 14th transistor N44；
The grid of described 8th transistor P43 meets bias voltage Iosc1, and the source electrode of described 6th transistor P41 connects described
The drain electrode of the second voltage source LVDD, described 8th transistor P43 connects the source electrode of described 9th transistor P44；
The grid of described 9th transistor P44 meets bias voltage Iosc2, and the drain electrode of described 9th transistor P44 connects described
The source electrode of the tenth transistor P45, the grid of described tenth transistor P45 meets outfan and the institute of described hex inverter INV44
State the input of the 7th phase inverter INV45, the drain electrode of described tenth transistor P45 connect the drain terminal of described 15th transistor N45,
Described agitator OSC internal capacitance C41 positive pole, the negative input of described second comparator COMP41 and described 3rd comparator
The positive input of COMP42；
The source electrode of described tenth two-transistor N42 connects the drain electrode of described 11st transistor N41, described 11st transistor
The grid of N41 and the grid of described 13rd transistor N43；
The source ground of described 11st transistor N41, the source ground of described 13rd transistor N43, the described tenth
The drain electrode of three transistor N43 connects the source electrode of described 14th transistor N44；
The source electrode of described 15th transistor N45 connects the drain electrode of described 14th transistor N44, described 15th transistor
The grid of N45 connects the outfan of described 4th phase inverter INV42, the input and the described 4th of described 5th phase inverter INV43
An input with door AND41；
The positive input of described second comparator COMP41 connects the first reference voltage V ref1, described second comparator
The output termination the described 4th of COMP41 and another input of door AND41；
The negative input of described 3rd comparator COMP42 connects voltage 2 and selects output second reference voltage V ref2 of 1, institute
State the output termination the described 5th of the 3rd comparator COMP42 and an input of door AND42；
The output of the described 4th and door AND41 terminates the input of described 3rd phase inverter INV41, described 3rd phase inverter
The output termination the described 5th of INV41 and another input of door AND42, the output of the described 5th and door AND42 terminates institute
Stating the input of the 4th phase inverter INV42, the output of described 5th phase inverter INV43 terminates described hex inverter INV44's
Input, the outfan of described 7th phase inverter INV45 forms agitator square-wave signal CLK.
Further, side's wave generation circuit 205 also includes lead-edge-blanking circuit LEB, the input of described lead-edge-blanking circuit LEB
End is connected to square-wave signal PWM end, and is triggered the lead-edge-blanking circuit LEB shielding time by the rising edge of described square-wave signal PWM
Postponing, the outfan of described lead-edge-blanking circuit LEB is connected to an input of the second NAND gate I22, the first NAND gate I21
Outfan be connected to another input of the second not gate I22, the outfan of the second NAND gate I22 is connected to rest-set flip-flop
R end；Or side's wave generation circuit 205 also includes negative circuit, the outfan of the first not gate I21 connects RS by negative circuit to be triggered
The R end of device.
The embodiment of the present invention also provides for a kind of Switching Power Supply, Switching Power Supply body is provided with pulse width as the aforementioned and adjusts
Switch power controller processed.
This pulse width modulating switch power source controller is integrated with brand-new variable frequency work pattern and discontinuous operation pattern, permissible
The switching frequency making system can alleviate and step-down along with load, reduces power consumption to greatest extent.In order to achieve the above object, originally
Invent the sampled signal FB d size decision-making system load condition of the feedback voltage signal FB according to error amplifier, so that it is determined that
The mode of operation of PWM switch power controller, then selects module to produce corresponding operating current by current-mode and is used for controlling
Oscillator operating frequency processed, it is achieved the self adaptation of system operating frequency under different loads.System operating frequency adaptive process is such as
Under: when system load is heavy condition, the AC/DC Switching Power Supply of described a kind of low standby power loss is operated in maximum system work
Frequency；Assume that system load starts to reduce load, at the AC/DC of load reduction to described a kind of low standby power loss from heavy condition
Before load critical state set by Switching Power Supply, the AC/DC Switching Power Supply of described a kind of low standby power loss is still operated in
Maximum system operating frequency, after load reduction to described load critical state, the AC/DC of described a kind of low standby power loss opens
Close power supply and start to reduce switching frequency along with the reduction of load condition, reduce power consumption；Loading very gently or under no-load condition, system
Entering intermittent mode, the AC/DC Switching Power Supply of described a kind of low standby power loss can completely close transducer output, relies only on transformation
The energy that device stores maintains loaded work piece, and when energy drops to certain value, restarting transducer is that transformator supplements energy, it
After repeat close transducer output action, reach to reduce further the standby merit of described Switching Power Supply by such method
The purpose of consumption.
Accompanying drawing explanation
Fig. 1 is the AC/DC switch power supply system application structure block diagram of a kind of low standby power loss of the present invention；
Fig. 2 is a kind of pulse width modulating switch power source controller internal circuit principle assumption diagram of the present invention；
Fig. 3 is the current-mode selecting circuit structure figure for controlling adaptive oscillator frequency of the present invention；
Fig. 4 is the knot of the frequency adaptive oscillator of the AC/DC Switching Power Supply for a kind of low standby power loss of the present invention
Composition.
Main element description of symbols
101: the AC/DC Switching Power Supply of a kind of low standby power loss
201: soft starting circuit
202:FB sample circuit
203: current-mode selection circuit
204: frequency adaptive oscillator
205: side's wave generation circuit
310: logic control voltage gating circuit
Detailed description of the invention
It is described in detail with embodiment below in conjunction with the accompanying drawings.
Refering to Fig. 1, for the AC/DC switch power supply system application structure block diagram of a kind of low standby power loss of the present invention.Power on
Initially, power switch pipe 107 is closed, and electric capacity 104 is charged by starting resistance 103 by alternating current power supply through bridge rectifier 102,
When on electric capacity 104, voltage is higher than chip UVLO_OFF, described PWM Switching Power Supply 101 starts, and sends enable signal triggering merit
Rate switching tube 107 turns on；The electric current flowing through transformator 106 primary inductance during power tube 107 turns on is oblique with controlled rising
Rate flows through CS peak current detection resistance 108, and PWM Switching Power Supply 101 detects the pressure produced on CS peak current detection resistance 108
Fall, thus control power switch pipe 107 and turn off；Power tube turn off after, RCD clamp circuit 105 to transformator 106 primary around
The crest voltage at group two ends carries out clamped, and transformator 106 secondary windings provides energy through output commutation diode 113 to output,
Transformator 106 assists winding to provide energy through VDD commutation diode 114 to VDD simultaneously；Output voltage sampling resistor 110 and electricity
The magnitude of voltage of resistance 111 series connection dividing potential drop compares amplification with error amplifier 112, and error amplifier 112 compares the electric current that amplification is later
Flowing through optical coupling amplifier 109, the electric current after optical coupling amplifier 109 amplifies flows through the FB merit of PWM Switching Power Supply 101
Energy leads ends, PWM Switching Power Supply 101 produces corresponding operating current by the size of detection FB end feedback current and shakes for control
Swing device operating frequency, it is achieved the self adaptation of system operating frequency under different loads.The operating frequency of system can be made with load
Reduce and reduce, reduce power consumption to greatest extent, raising efficiency.
Refering to Fig. 2,3,4, wherein pulse width modulating switch power source controller includes:
Supply voltage pin, grounding pin, feedback pin fb, control output end pin gate, current monitoring end pin cs
Port RI pin is set with bias current；And
FB sample circuit 202, its input port connects feedback pin fb, and size based on feedback pin fb feedback current,
Feedback current change is changed into voltage sampling signal FB_d and exports；
Current-mode selection circuit 203, the first input end of current-mode selection circuit 203 connects the output of sampled signal FB_d
End, and according to the voltage range of voltage sampling signal FB_d, produce corresponding agitator the first electric current Iosc1 and the second electric current
Iosc2；
Side's wave generation circuit 205, side's first input end of wave generation circuit 205, the second input, the 3rd input, the
Four-input terminal, the 5th input, the 6th input, connect the peak limited voltage of current monitoring end pin CS input voltage respectively
Vth1, current monitoring end pin CS, sampled signal FB_d outfan, the first reference voltage V ref1, agitator the first electric current
Iosc1 outfan and the second electric current Iosc2 outfan, the first output logic signal outfan of 205, the second output logic signal
Outfan, is connected respectively to the grid end of transistor N21 and transistor N22, and 205 according to current monitoring end pin CS input voltage
Peak limited voltage vth1, current monitoring end pin CS signal, sampled signal FB_d, the first reference voltage V ref1, agitator
One electric current Iosc1 and the second electric current Iosc2 obtains the first output logic signal and the second output logic of switch power controller
Signal；
The grid end of transistor N21 is also clamped to the breakdown reverse voltage on ground through diode D23, the drain terminal of transistor N21
Being connected to supply voltage pin vdd terminal, the source of transistor N22 is connected to ground, and the source of transistor N21 is with transistor N22's
Drain terminal is connected to the control output end GATE functional pin of described PWM switch power controller, described GATE merit after connecting
Can leads ends to ground connect a resistance R25.
Further, the second input termination RI pin of current-mode selection circuit 203, and obtain reference current accordingly
Iref, 205 export clock square wave CLK, wherein, benchmark electricity always according to the first reference voltage V ref1 and the second reference voltage V ref2
Pressure Vref2 is the peak limited voltage vth1 of current monitoring end pin CS input voltage, also includes soft starting circuit 201, soft opens
The first input end on galvanic electricity road 201 connects reference current Iref outfan, the second input terminated clock square wave of soft starting circuit 201
CLK outfan, and under the control of output clock square wave CLK, use reference current Iref charging to make outfan rise to electricity
The peak limited voltage vth1 of stream monitoring side pin CS input voltage.
Further, soft starting circuit 201 includes electric charge pump PUMP circuit, and described electric charge pump PUMP circuit input end is by vibrating
Device output square-wave signal CLK and reference current Iref co-controlling, its output voltage SS is connected to soft start and terminates comparator
COMP21 obtains positive input, selects control signal with the output of COMP21 negative input voltage vth1 result of the comparison, and 2 select 1
Control signal outfan is selected in the first input end selecting of selector, and according to selecting the control signal current monitoring end from input to draw
The peak limited voltage vth1 and electric charge pump PUMP circuit input voltage SS of foot CS input voltage selects, output reference electricity
Pressure Vref2.
Further, FB sample circuit 202 also includes diode D21, diode D22, resistance R21, resistance R22, resistance
R23, resistance R24, the negative pole of described diode D21 connects feedback pin fb, and is connected with the negative pole of resistance R21, diode D21's
The negative pole of positive pole connecting resistance R22, and be connected with the positive pole of diode D22, described resistance R21 positive pole and second source LVDD phase
Even, resistance R22 positive pole is connected with second source LVDD, and the positive pole of resistance R23 is connected with the negative pole of diode D22, resistance R23's
Negative pole is connected with the positive pole of resistance R24, and the negative pole of resistance R24 is connected to grounding pin.
Further, current-mode selection circuit 203 also includes: logic control voltage gating circuit 310, grounding lead foot are brilliant
Body pipe N34, oscillator current Iosc1 end transistor P31, oscillator current Iosc2 end transistor P32, comparator COMP31, late
Stagnant comparator COMP32, operational amplifier OP31, operational amplifier OP32, operational amplifier OP33, resistance R31, the 3rd computing
Amplifier OP33 positive input is connected to 2V DC voltage, and negative input is connected to RI pin together with outfan, and leads to
The outer meeting resistance R115 crossing RI pin forms bias current Iref, and the second operational amplifier OP32 positive input is connected to direct current
Voltage Vref_L, the second operational amplifier OP32 negative input is connected to one end of the 6th resistance R31 together with outfan, the
One operational amplifier OP31 positive input is connected to the outfan Vs of logic control voltage gating circuit 310, and the first computing is put
Big device OP31 negative input is connected to the other end and the source of grounding pin end transistor N34 of the 6th resistance R31, the first fortune
The outfan calculating amplifier OP31 is connected to the grid end of grounding pin end transistor N34；The drain terminal of grounding pin end transistor N34
Being connected to drain terminal and the grid end Iosc2 of agitator the second electric current Iosc2 end transistor P32, agitator the second electric current Iosc2 end is brilliant
The source of body pipe P32 is connected to grid end and drain terminal Iosc1, the agitator first of agitator the first electric current Iosc1 end transistor P31
The source of electric current Iosc1 end transistor P31 is connected to internal low-voltage power supply LVDD, the of logic control voltage gating circuit 310
One input pin is connected with the outfan of COMP31；Second input pin is connected with the outfan of COMP32；3rd input pin
It is connected with the negative input Vref_H of COMP31；The positive input FB_d phase of the 4th input pin and COMP31 and COMP32
Even；5th input pin is connected with the negative input Vref_B of COMP32；The positive input phase of the outfan of 310 and OP31
Even；Wherein logic control voltage gating circuit 310 is for the voltage range by judging FB_d, exports different magnitudes of voltage,
When FB_d >=Vref_H when, Vs=Vref H, Vref_H are the first reference voltage, agitator charging and discharging currentsAgitator sends out ripple with fixing operating frequency；
When Vref_H ＜ FB_d >=Vref_M-Vos when, Vs=FB_d, Vref_M are the 3rd reference voltage, agitator
Charging and discharging currentsThe operating frequency of agitator starts to reduce frequency along with the reduction of output loading
Rate；
When FB_d ＜ Vref_M-Vos when, Vs=Vref_B, vref_B are the second reference voltage, agitator discharge and recharge
Electric currentUnder output loading underloading or Light Condition, agitator is intermittent with minimum frequency of operation
Send out ripple.
Further, logic control voltage gating circuit 310 includes: include transistor N31, transistor N32, transistor N33,
Phase inverter INV31, phase inverter INV32 and door AND31 and door AND32 and door AND33, the grid of described transistor N31 meets institute
Stating and the outfan of door AND31, the source electrode of described transistor N31 connects the positive input Vs of operational amplifier OP31, transistor
The drain electrode of N31 meets DC voltage Vref_H, and the grid of described transistor N32 connects the described outfan with door AND32, described crystal
The source electrode of pipe N32 meets the positive input Vs of described operational amplifier OP31, and the drain electrode of transistor N32 connects described sampled signal
The sampled voltage FB_d of FB_d outfan；The grid of transistor N33 connects and the outfan of door AND33, and the source electrode of transistor N33 connects
The positive input Vs of operational amplifier OP31, the drain electrode of transistor N33 meets DC voltage Vref_B；Phase inverter INV31 and
The outfan of phase inverter INV32 connect respectively with door AND32 and with the input of door AND33；Described comparator COMP31's is defeated
Go out to terminate described phase inverter INV31 input and with the input of door AND31, described hysteresis comparator COMP32's is defeated
Go out to terminate the input of described phase inverter INV32 and another input of door AND31 and an input with door AND32.
Further, side's wave generation circuit 205 includes:
Described CS peak point current comparator COMP22 positive input receives 2 output voltages selecting 1 selector in succession
Vref2, negative input connects the current monitoring end pin CS of described PWM switch power controller, described CS peak point current ratio
The outfan of relatively device is connected to an input of NAND gate I21；Described error comparator COMP23 positive input is connected to adopt
Sample signal FB_d outfan, negative input connects current monitoring end pin i.e., and the outfan of error comparator COMP23 connects
Another input to NAND gate I21；The outfan of not gate I21 connects the R end of rest-set flip-flop by logical device, and described RS touches
Sending out device outfan and control soft-sphere model circuit Soft Driver, soft-sphere model circuit output logic is connected respectively to transistor N21 and crystalline substance
The grid end of body pipe N22；
The input of described agitator OSC is connected with Vref1, Vref2, Iosc1 and Iosc2 signal, described agitator
Output is connected to the S end of rest-set flip-flop, and agitator OSC utilizes bias current Iosc1 and Iosc2 to agitator OSC internal capacitance
C41 charges, and when agitator OSC internal capacitance C41 voltage is more than Vref1, bias current Iosc1 and Iosc2 starts vibration
Device OSC internal capacitance C41 is discharged, and when agitator OSC capacitance voltage is less than Vref2, bias current Iosc1 and Iosc2 opens again
Beginning to charge agitator OSC internal capacitance C41, so circulation makes to be output as shaking square-wave signal.Described agitator OSC also determines
Determine the maximum functional dutycycle of described PWM switch power controller.
Further, agitator OSC includes: include transistor P41, transistor P42, transistor P43, transistor P44, crystal
Pipe P45, transistor N41, transistor N42, transistor N43, transistor N44, transistor N45, agitator OSC internal capacitance C41,
Comparator COMP41, comparator COMP42 and door AND41 and door AND42, phase inverter INV41, phase inverter INV42, phase inverter
INV43, phase inverter INV44 and phase inverter INV45；
The grid of described transistor P41 meets bias voltage Iosc1, and the source electrode of described transistor P41 connects described second voltage
Source LVDD, the drain electrode of described transistor P41 connects the source electrode of described transistor P42；
The grid of described transistor P42 connects the drain electrode of bias voltage Iosc2, described transistor P42 and connects the leakage of transistor N42
Pole, the grid of transistor N42 and the grid of transistor N44；
The grid of transistor P43 meets bias voltage Iosc1, and the source electrode of transistor P41 meets described second voltage source LVDD, brilliant
The drain electrode of body pipe P43 connects the source electrode of transistor P44；
The grid of transistor P44 meets bias voltage Iosc2, and the drain electrode of transistor P44 connects the source electrode of transistor P45, crystal
The grid of pipe P45 connects outfan and the input of phase inverter INV45 of phase inverter INV44, and the drain electrode of transistor P45 connects transistor
The drain terminal of N45, described agitator OSC internal capacitance C41 positive pole, the negative input of comparator COMP41 and comparator COMP42
Positive input；
The source electrode of transistor N42 connects the drain electrode of transistor N41, the grid of transistor N41 and the grid of transistor N43；
The source ground of transistor N41, the source ground of transistor N43, the drain electrode of transistor N43 connects transistor N44's
Source electrode；
The source electrode of transistor N45 connects the drain electrode of transistor N44, and the grid of transistor N45 connects the output of phase inverter INV42
End, the input of phase inverter INV43 and an input with door AND41；
The positive input of comparator COMP41 connects the first reference voltage V ref1, the output of comparator COMP41 termination with
Another input of door AND41；
The negative input of comparator COMP42 connects voltage 2 and selects the output reference voltage Vref2 of 1, comparator COMP42's
Output termination and an input of door AND42；
With the input of the output termination phase inverter INV41 of door AND41, the output termination of phase inverter INV41 and door AND42
Another input, with the input of the output termination phase inverter INV42 of door AND42, the output termination of phase inverter INV43 is anti-
The input of phase device INV44, the outfan of phase inverter INV45 forms agitator square-wave signal CLK.
Further, side's wave generation circuit 205 also includes lead-edge-blanking circuit LEB, the input of described lead-edge-blanking circuit LEB
End is connected to square-wave signal PWM end, and is triggered the lead-edge-blanking circuit LEB shielding time by the rising edge of described square-wave signal PWM
Postponing, the outfan of described lead-edge-blanking circuit LEB is connected to an input of NAND gate I22, the outfan of NAND gate I21
Being connected to another input of not gate I22, the outfan of NAND gate I22 is connected to the R end of rest-set flip-flop；Or there is electricity in square wave
Road 205 also includes negative circuit, and the outfan of the first not gate I21 connects the R end of rest-set flip-flop by negative circuit.
Embodiments of the invention provide a kind of pulse width modulating switch power source controller, by the feedback of error amplifier
The sampled signal FB_d size decision-making system load condition of voltage signal FB, so that it is determined that the work of PWM switch power controller
Pattern, then selects module to produce corresponding operating current by current-mode and is used for controlling oscillator operating frequency, it is achieved no
Self adaptation with the lower system operating frequency of load.The operating frequency that can make system reduces, to greatest extent with the reduction of load
Reduction power consumption, raising efficiency.
For convenience of explanation, following discussion is with reference to flyback topologies AC/DC Switching Power Supply, but person of ordinary skill in the field
It is to be understood that it is also possible to apply the invention to other type of PWM mode AC/DC switch power supply system.Simultaneously in order to make this technology
The technical staff in field is more fully understood that technical scheme, below in conjunction with the drawings and embodiments reality to the present invention
Execute example to be described in further detail.
Such as prepulse width modulated switch power-supply controller of electric, including soft starting circuit 201, FB sample circuit 202, current-mode
Formula selection circuit 203, frequency adaptive oscillator 204, CS peak point current comparator COMP22, error comparator COMP23, RS
Trigger, lead-edge-blanking circuit LEB, soft-sphere model circuit Soft Driver, resistance R25, diode D23, transistor N21 and
N22, NAND gate I21 and I22.
From in figure two, soft starting circuit 201 is in each of output square wave CLK of frequency adaptive oscillator 204
Reference current Iref is controlled to electric charge pump PUMP fixing charging a period of time, therefore the output voltage SS of electric charge pump PUMP in cycle
Along with each clk cycle is continuously increased.When SS≤vth1 when, Vref2=SS；When SS ＞ vth1 when, Vref2=
vth1.The output voltage SS of electric charge pump PUMP simultaneously with CS peak point current comparator COMP22 and frequency adaptive oscillator 204
Relevant, therefore all raise along with the voltage of SS at soft start period CS peak point current and adaptive oscillator frequency and increase.FB
The size of sample circuit 202 sample detecting FB end feedback current, and feedback current change is changed into the change in voltage of FB_d, from
And by error comparator COMP23 with CS voltage ratio relatively, thus control the conducting dutycycle of power switch pipe 107, electric current simultaneously
Mode selection circuit 203 produces corresponding oscillator current Iosc1 and Iosc2 according to the voltage range of FB_d and is used for controlling vibration
Device operating frequency, it is achieved the self adaptation of system operating frequency under different loads.The voltage relationship of FB_d with FB end is approximately equal to:
The output square wave CLK of adaptive oscillator 204 triggers soft-sphere model circuit Soft Driver through rest-set flip-flop and drives
GATE functional pin is high, so that power switch pipe 107 turns on.CS peak point current comparator COMP22 and error comparator
Power switch pipe 107 turn-off time point, power switch pipe is controlled after the COMP23 blanking circuit LEB shielding time the most ahead of the curve
The maximum ON time of 107 is determined by the output square wave CLK of adaptive oscillator 204.
Such as the current-mode selection circuit of front control adaptive oscillator frequency, including logic control voltage gating circuit
310, transistor N34, transistor P31, transistor P32, comparator COMP31, hysteresis comparator COMP32, operational amplifier
OP31, operational amplifier OP32, operational amplifier OP33, resistance R31.Operational amplifier OP33 positive input connects the benchmark of 2V
Voltage, its outfan and negative input short circuit form source with amplifier, and be connected to PWM Switching Power Supply 101 RI function is drawn
Foot, and form bias current Iref together with resistance 115:
From in figure, with operational amplifier OP31 and OP32 as core, constitute two negative feedback structures, and and resistance
R31 determines the size of agitator charging and discharging currents together.
Comparator COMP31 and hysteresis comparator COMP32 selects transistor N31, transistor according to the voltage range of FB_d
A conducting in N32, transistor N33, thus form different Vs magnitudes of voltage.Assume that the magnitude of voltage of FB_d becomes from high to low
Change:
When FB_d >=Vref_H when, Vs=Vref H, agitator charging and discharging currents
Agitator sends out ripple with fixing operating frequency；
When Vref_H ＜ FB_d >=Vref_M-Vos when, Vs=FB_d, agitator charging and discharging currentsThe operating frequency of agitator starts to reduce frequency along with the reduction of output loading；
When FB_d ＜ Vref_M-Vos when, Vs=Vref_B, agitator charging and discharging currentsUnder output loading underloading or Light Condition, agitator sends out ripple with minimum frequency of operation intermittence；
Assume that the magnitude of voltage of FB_d changes from low to high:
When FB_d ＜ Vref_M+Vos when, vs=Vref_B, agitator charging and discharging currentsUnder output loading underloading or Light Condition, agitator sends out ripple with minimum frequency of operation intermittence；
When vref_H ＜ FB_d >=Vref_M+Vos when, Vs=FB_d, agitator charging and discharging currentsThe operating frequency of agitator starts to reduce frequency along with the reduction of output loading；
When FB_d >=Vref_H when, Vs=Vref_H, agitator charging and discharging currents
Agitator sends out ripple with fixing operating frequency；
Wherein, magnitude of voltage on the basis of Vref_H, Vref_M, Vref_B and Vref_L, Vos is the sluggishness of comparator COMP32
Magnitude of voltage, enters and exits the sluggish interval of intermittent ripple for arranging the AC/DC Switching Power Supply of a kind of low standby power loss
Vref_H ＞ Vref_M ＞ Vref_M-Vos ＞ Vref_B ＞ Vref_L.
Such as the frequency adaptive oscillator OSC circuit of the AC/DC Switching Power Supply of front low standby power loss, including transistor P41,
Transistor P42, transistor P43, transistor P44, transistor P45, transistor N41, transistor N42, transistor N43, transistor
N44, transistor N45, electric capacity C41, comparator COMP41, comparator COMP42 and door AND41 and door AND42, phase inverter
INV41, phase inverter INV42, phase inverter INV43, phase inverter INV44 and phase inverter INV45.Described agitator passes through transistor
Electric capacity C41 is charged by the oscillator bias current of P43 and transistor P44, and after the voltage of C41 is more than Vref1, CP logic is believed
Number control transistor P45 turn off oscillator bias charging current, simultaneously CN logical signal control transistor N45 oscillator bias put
Electricity electric current, is discharged to electric capacity C41 by the oscillator bias current of transistor N43 and transistor N44, when the voltage of C41 is less than
After Vref2, CP logical signal controls transistor P45 and again turns on oscillator bias charging current, and so move in circles shape
Become concussion output logic signal CLK.It should be noted that Vref2=SS in soft start-up process, so CLK in soft start engineering
Frequency of oscillation raise also as the rising of soft starting circuit output voltage.
The embodiment of the present invention also provides for a kind of Switching Power Supply, Switching Power Supply body is provided with pulse width as the aforementioned and adjusts
Switch power controller processed.
By the sampled signal FB_d size decision-making system load condition of the feedback voltage signal FB of error amplifier, thus
Determine the mode of operation of PWM switch power controller, then select module to produce corresponding operating current by current-mode and use
In controlling oscillator operating frequency, it is achieved the self adaptation of system operating frequency under different loads.The operating frequency of system can be made
Reduce with the reduction of load, reduce power consumption to greatest extent, raising efficiency.
The above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For Yuan, under the premise without departing from the principles of the invention, it is also possible to do some improvements and modifications, these improvements and modifications also should regard
For protection scope of the present invention.
Claims (9)
1. a pulse width modulating switch power source controller, it is characterised in that: include supply voltage pin, grounding pin, anti-
Feedback pin fb, control output end pin gate, current monitoring end pin CS and bias current arrange port RI pin；And
FB sample circuit 202, its input port connects feedback pin fb, and size based on feedback pin fb feedback current, will be anti-
Supply current change changes into sampled voltage FB_d and exports；
Current-mode selection circuit 203, the first input end of current-mode selection circuit 203 connects sampled voltage FB_d outfan,
And according to the voltage range of sampled voltage FB_d, produce corresponding agitator the first electric current Iosc1 and agitator the second electric current
Iosc2；
Side's wave generation circuit 205, including agitator, side's first input end of wave generation circuit 205, the second input, the 3rd defeated
Enter end, four-input terminal, the 5th input, the 6th input, connect the second reference voltage V ref2, current monitoring end pin respectively
CS, sampled voltage FB_d outfan, the first reference voltage V ref1, agitator the first electric current Iosc1 outfan and agitator second
Electric current Iosc2 outfan, the first output logic signal outfan of side's wave generation circuit 205 is connected to the first transistor N21's
Grid end, the second output logic signal outfan of side's wave generation circuit 205 are connected to the grid end of transistor seconds N22, and square wave is sent out
Raw circuit 205 is according to the second reference voltage V ref2, sampled voltage FB_d, the first reference voltage V ref1, agitator the first electric current
Iosc1 and agitator the second electric current Iosc2 obtains the first output logic signal and the second output logic of switch power controller
Signal；
The grid end of the first transistor N21 is also clamped to the breakdown reverse voltage on ground through the first diode D23, the first transistor
The drain terminal of N21 is connected to supply voltage pin vdd terminal, and the source of transistor seconds N22 is connected to ground, the first transistor N21's
Source is connected to control output end pin gate with the drain terminal of transistor seconds N22 after being connected, described control output end is drawn
Foot gate to one the first resistance R25 of ground series connection；Second input termination bias current of current-mode selection circuit 203 arranges end
Mouth RI pin, and obtain reference current Iref accordingly, side's wave generation circuit 205 is always according to the first reference voltage V ref1 and second
Reference voltage V ref2 output clock square wave CLK；
Also include that soft starting circuit 201, the first input end of soft starting circuit 201 connect reference current Iref outfan, soft start
Second input terminated clock square wave CLK outfan of circuit 201, and under the control of output clock square wave CLK, use benchmark electricity
The peak value that stream Iref charging makes the outfan of soft starting circuit 201 rise to current monitoring end pin CS input voltage limits electricity
Pressure vth1.
Pulse width modulating switch power source controller the most according to claim 1, it is characterised in that soft starting circuit 201
Including electric charge pump PUMP circuit, described electric charge pump PUMP circuit input end is by agitator output square-wave signal CLK and reference current
Iref co-controlling, electric charge pump PUMP circuit output voltage SS is connected to soft start and terminates the forward input of comparator COMP21
End, selects control signal with the output of COMP21 negative input voltage result of the comparison, and 2 select the first input end of 1 selector to connect
Select control signal outfan, and according to selecting the control signal peak value limit from the current monitoring end pin CS input voltage of input
Voltage vth1 processed and electric charge pump PUMP circuit output voltage SS selects, exports the second reference voltage V ref2.
Pulse width modulating switch power source controller the most according to claim 1, it is characterised in that FB sample circuit 202
Also include the second diode D21, the 3rd diode D22, the second resistance R21, the 3rd resistance R22, the 4th resistance R23, the 5th electricity
Resistance R24, the negative pole of described second diode D21 connects feedback pin fb, and is connected with the negative pole of the second resistance R21, the two or two pole
The positive pole of pipe D21 connects the negative pole of the 3rd resistance R22, and is connected with the positive pole of the 3rd diode D22, and described second resistance R21 is just
Pole is connected with second source LVDD, and the 3rd resistance R22 positive pole is connected with second source LVDD, the positive pole of the 4th resistance R23 and
The negative pole of three diode D22 is connected, and the negative pole of the 4th resistance R23 and the positive pole of the 5th resistance R24 are connected, the 5th resistance R24's
Negative pole is connected to grounding pin.
Pulse width modulating switch power source controller the most according to claim 1, it is characterised in that current-mode selects electricity
Road 203 also includes: logic control voltage gating circuit 310, grounding pin end transistor N34, agitator the first electric current Iosc1 end
Transistor P31, agitator the second electric current Iosc2 end transistor P32, the first comparator COMP31, hysteresis comparator COMP32,
One operational amplifier OP31, the second operational amplifier OP32, the 3rd operational amplifier OP33, the 6th resistance R31, the 3rd computing is put
Big device OP33 positive input is connected to 2V DC voltage, and negative input is connected to RI pin together with outfan, and passes through
The outer meeting resistance R115 of RI pin forms reference current Iref, and the second operational amplifier OP32 positive input is connected to the 4th ginseng
Examining voltage Vref_L, the second operational amplifier OP32 negative input is connected to one end of the 6th resistance R31 together with outfan,
First operational amplifier OP31 positive input is connected to the outfan of logic control voltage gating circuit 310, and the first computing is put
Big device OP31 negative input is connected to the other end and the source of grounding pin end transistor N34 of the 6th resistance R31, the first fortune
The outfan calculating amplifier OP31 is connected to the grid end of grounding pin end transistor N34；The drain terminal of grounding pin end transistor N34
It is connected to source and the grid end of agitator the second electric current Iosc2 end transistor P32, agitator the second electric current Iosc2 end transistor
The drain terminal of P32 is connected to grid end and the source of agitator the first electric current Iosc1 end transistor P31, agitator the first electric current Iosc1
The source and drain end of end transistor P31 is connected to second source LVDD, and logic control voltage gating circuit 310 includes the first comparator
COMP31, and by the first input pin of logic control voltage gating circuit 310 and the outfan phase of the first comparator COMP31
Even；Second input pin is connected with the outfan of hysteresis comparator COMP32；3rd input pin and the first comparator COMP31
Negative input be connected；4th input pin and the positive input of the first comparator COMP31 and hysteresis comparator COMP32
Positive input be connected；5th input pin is connected with the negative input of hysteresis comparator COMP32；Logic control voltage
The outfan of gating circuit 310 and the positive input of the first operational amplifier OP31 are connected；Wherein logic control voltage gating
Circuit 310 is for the voltage range of the positive input sampled voltage FB_d by judging hysteresis comparator COMP32, and output is not
Same magnitude of voltage,
When FB_d >=Vref_H when, Vs=Vref_H, Vref_H are the 3rd reference voltage, agitator charging and discharging currentsAgitator sends out ripple with fixing operating frequency；
When Vref_H ＜ FB_d >=Vref_M-Vos when, Vs=FB_d, Vref_M are the 3rd reference voltage, agitator charge and discharge
Electricity electric currentThe operating frequency of agitator starts to reduce frequency along with the reduction of output loading；
When FB_d ＜ Vref_M-Vos when, Vs=Vref_B, Vref_B are the second reference voltage, agitator charging and discharging currentsUnder output loading underloading or Light Condition, agitator sends out ripple with minimum frequency of operation intermittence,
Vs is the voltage of the outfan of logic control voltage gating circuit 310, and Vos is the hysteresis voltage value of comparator COMP32.
Pulse width modulating switch power source controller the most according to claim 4, it is characterised in that logic control voltage selects
Circuit passband 310 includes: include third transistor N31, the 4th transistor N32, the 5th transistor N33, the first phase inverter INV31,
Second phase inverter INV32, first and door AND31, second and door AND32, the 3rd and door AND33, described third transistor N31
Grid connects the outfan of described first and door AND31, and the source electrode of described third transistor N31 connects the first operational amplifier OP31's
Positive input, the drain electrode of described third transistor N31 connects the 3rd reference voltage V ref_H, the grid of described 4th transistor N32
Pole connects the outfan of described second and door AND32, and the source electrode of described 4th transistor N32 meets described first operational amplifier OP31
Positive input, the drain electrode of described 4th transistor N32 meets the sampled voltage FB_d of described sampled voltage FB_d outfan；Institute
The grid stating the 5th transistor N33 connects the outfan of the described 3rd and door AND33, and the source electrode of described 5th transistor N33 meets institute
Stating the positive input of the first operational amplifier OP31, the drain electrode of described 5th transistor N33 meets the second reference voltage Vref _ B；
The outfan of described first phase inverter INV31 and the second phase inverter INV32 connect respectively second with the input of door AND32 and the
The input of three and door AND33；The output of described first comparator COMP31 terminates the input of described first phase inverter INV31
With an input of described first Yu door AND31, the output of described hysteresis comparator COMP32 terminates described second phase inverter
Another input of the input of INV32, described first and door AND31 and another input of described second and door AND32
End.
Pulse width modulating switch power source controller the most according to claim 1, it is characterised in that side's wave generation circuit
205 include:
CS peak point current comparator COMP22 positive input receives 2 the second reference voltages selecting 1 selector output in succession
Vref2, negative input connects the current monitoring end pin CS, described current monitoring end pin CS of PWM switch power controller
The outfan of peak point current comparator COMP22 is connected to an input of the first NAND gate I21；Error comparator COMP23 is just
Being connected to sampled voltage FB_d outfan to input, negative input connects current monitoring end pin CS, described application condition
The outfan of device COMP23 is connected to another input of the first NAND gate I21；The outfan of the first not gate I21 passes through logic device
Part connects the R end of rest-set flip-flop, and described rest-set flip-flop outfan controls soft-sphere model circuit Soft Driver, soft-sphere model circuit
Soft Driver output logic is connected respectively to the first transistor N21 grid end and the grid end of transistor seconds N22；
The input of described agitator and the first reference voltage V ref1, the second reference voltage V ref2, agitator the first electric current
Iosc1 and agitator the second electric current Iosc2 signal connect, and the output of described agitator is connected to the S end of rest-set flip-flop, agitator
Utilize agitator the first electric current Iosc1 and agitator the second electric current Iosc2 that agitator internal capacitance C41 is charged, work as agitator
When internal capacitance C41 voltage is more than Vref1, the first electric current Iosc1 and the second electric current Iosc2 starts agitator internal capacitance
C41 discharges, and when agitator internal capacitance C41 voltage is less than Vref2, the first electric current Iosc1 and the second electric current Iosc2 starts again
Charging agitator internal capacitance C41, so circulation makes to be output as shaking square-wave signal；Described agitator also determines described
The maximum functional dutycycle of switch power controller.
Pulse width modulating switch power source controller the most according to claim 6, it is characterised in that agitator includes: bag
Include the 6th transistor P41, the 7th transistor P42, the 8th transistor P43, the 9th transistor P44, the tenth transistor P45, the tenth
One transistor N41, the tenth two-transistor N42, the 13rd transistor N43, the 14th transistor N44, the 15th transistor N45,
Agitator internal capacitance C41, the second comparator COMP41, the 3rd comparator COMP42, the 4th and door AND41, the 5th and door
AND42, the 3rd phase inverter INV41, the 4th phase inverter INV42, the 5th phase inverter INV43, hex inverter INV44 and the 7th are anti-
Phase device INV45；
The grid of described 6th transistor P41 connects the bias voltage output of current-mode selection circuit 203, described 6th crystal
The drain electrode of pipe P41 connects the source electrode of described second source LVDD, described 6th transistor P41 and connects the leakage of described 7th transistor P42
Pole；
The grid of described 7th transistor P42 connects the bias voltage output of current-mode selection circuit 203, described 7th crystal
The source electrode of pipe P42 connects the drain electrode of described tenth two-transistor N42, the grid and the described 14th of described tenth two-transistor N42
The grid of transistor N44；
The grid of described 8th transistor P43 connects the bias voltage output of current-mode selection circuit 203, described 8th crystal
The drain electrode of pipe P43 meets described second voltage source LVDD, and the source electrode of described 8th transistor P43 connects described 9th transistor P44's
Drain electrode；
The grid of described 9th transistor P44 connects the bias voltage output of current-mode selection circuit 203, described 9th crystal
The source electrode of pipe P44 connects the drain electrode of described tenth transistor P45, and the grid of described tenth transistor P45 connects described hex inverter
The outfan of INV44 and the input of described 7th phase inverter INV45, the source electrode of described tenth transistor P45 connects the described tenth
The drain terminal of five transistor N45, described agitator internal capacitance C41 positive pole, the negative input of described second comparator COMP41
Positive input with described 3rd comparator COMP42；
The source electrode of described tenth two-transistor N42 meets the drain electrode of described 11st transistor N41, described 11st transistor N41
Grid and the grid of described 13rd transistor N43；
The source ground of described 11st transistor N41, the source ground of described 13rd transistor N43, described tenth trimorphism
The drain electrode of body pipe N43 connects the source electrode of described 14th transistor N44；
The source electrode of described 15th transistor N45 meets the drain electrode of described 14th transistor N44, described 15th transistor N45
Source grid connect the outfan of described 4th phase inverter INV42, the input of described 5th phase inverter INV43 and the described 4th with
One input of door AND41；
The positive input of described second comparator COMP41 meets the first reference voltage V ref1, described second comparator COMP41
Output termination the described 4th and another input of door AND41；
The negative input of described 3rd comparator COMP42 connects voltage 2 and selects output second reference voltage V ref2 of 1, and described
The output termination the described 5th of three comparator COMP42 and an input of door AND42；
The output of the described 4th and door AND41 terminates the input of described 3rd phase inverter INV41, described 3rd phase inverter
The output termination the described 5th of INV41 and another input of door AND42, the output of the described 5th and door AND42 terminates institute
Stating the input of the 4th phase inverter INV42, the output of described 5th phase inverter INV43 terminates described hex inverter INV44's
Input, the outfan of described 7th phase inverter INV45 forms agitator square-wave signal CLK.
Pulse width modulating switch power source controller the most according to claim 6, it is characterised in that side's wave generation circuit
205 also include that lead-edge-blanking circuit LEB, the input of described lead-edge-blanking circuit LEB are connected to square-wave signal PWM end, and by
The rising edge of described square-wave signal PWM triggers lead-edge-blanking circuit LEB and shields time delay, described lead-edge-blanking circuit LEB's
Outfan is connected to an input of the second NAND gate I22, and the outfan of the first NAND gate I21 is connected to the second not gate I22
Another input, the outfan of the second NAND gate I22 is connected to the R end of rest-set flip-flop；Or side's wave generation circuit 205 also wraps
Including negative circuit, the outfan of the first not gate I21 connects the R end of rest-set flip-flop by negative circuit.
9. a Switching Power Supply, it is characterised in that: arrange just like claim 1 to 8 any claim on Switching Power Supply body
Described pulse width modulating switch power source controller.
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| CN103368143B (en) * | 2013-08-02 | 2015-07-29 | 成都启臣微电子有限公司 | Current mode switch power supply overpower-protection circuit |
| CN103840687B (en) * | 2013-11-30 | 2016-03-09 | 成都岷创科技有限公司 | Constant-current control circuit |
| CN104753474B (en) * | 2013-12-27 | 2018-01-05 | 展讯通信（上海）有限公司 | N class A amplifier As |
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