CN103208934A - Pulse width modulation switching power supply controller and switching power supply - Google Patents
Pulse width modulation switching power supply controller and switching power supply Download PDFInfo
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- CN103208934A CN103208934A CN2012100076482A CN201210007648A CN103208934A CN 103208934 A CN103208934 A CN 103208934A CN 2012100076482 A CN2012100076482 A CN 2012100076482A CN 201210007648 A CN201210007648 A CN 201210007648A CN 103208934 A CN103208934 A CN 103208934A
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Abstract
The invention provides a pulse width modulation switching power supply controller and a switching power supply and belongs to the technical field of electronic integrated circuits. The pulse width modulation switching power supply controller and the switching power supply are widely applied to a PWM (Pulse Width Modulation) mode AC/DC (Alternating Current/Direct Current) switching power supply system. The PWM controller comprises an FB (Feed Back) sampling circuit, a current mode selecting circuit, a square wave generating circuit and the like. The pulse width modulation switching power supply controller has the advantages of being capable of achieving self-adaption of the system working frequency under different loads and reducing standby power consumption of the switching power supply.
Description
Technical field
The present invention relates to the basic electronic circuit technical field, particularly a kind of pulse width modulating switch power source controller and Switching Power Supply.
Background technology
Under the more and more stronger trend of global environmental consciousness, utilize the energy to become the common recognition in the whole world more efficiently, so electronic product and power supply thereof begin to be subjected to the restriction of energy-saving act in recent years, as California, USA energy commission (California Energy Commission, CEC) energy conservation criteria, and the plan of " Energy Star (Energy Star) " sign etc.Except these energy conservation criterias, another new criteria of being gazed at namely is " stand-by power consumption ".According to statistics, the power consumption of electronic product when standby accounts for the electric power 3%-13% in the whole world, and therefore the power consumption when standby also works up clear and definite standard, and the low standby power loss characteristic maybe will become the essential basic demand of following power supply unit.Switching Power Supply (Switch Mode Power Supply) with its excellent performance and widely the application scenario occupied the pith in current power supply series market.Yet, because there is inevitable loss of energy in the course of the work in Switching Power Supply, comprise switching loss, conduction loss and control circuit loss, and these losses all have much relations with the operating frequency of system, especially when underloading or zero load, adopt with heavy condition under identical switching frequency can reduce useful work largely to the ratio of total work, lower efficiency.And the rising of the Switching Power Supply operating frequency that causes along with the product trend toward miniaturization, the energy of loss also constantly increase, and this has become the main part of switch power supply system energy loss under underloading and holding state.
This shows in the prior art and exist: existing AC/DC Switching Power Supply stand-by power consumption problem of higher.
Summary of the invention
In order to address the above problem, the purpose of this invention is to provide a kind of pulse width modulating switch power source controller and Switching Power Supply, the pulse width modulating switch power source controller comprises:
Supply power voltage pin, grounding pin, feedback pin fb, control output end pin gate, current monitoring end pin cs and bias current arrange port RI pin; And
Current-mode is selected circuit 203, and current-mode selects the first input end of circuit 203 to connect sampled signal FB_d output, and according to the voltage range of voltage sampling signal FB_d, produces corresponding the oscillator first electric current I osc1 and the second electric current I osc2;
Square wave generation circuit 205, the first input end of square wave generation circuit 205, second input, the 3rd input, four-input terminal, the 5th input, the 6th input, meet the peak-limitation voltage vth1 of current monitoring end pin CS input voltage respectively, current monitoring end pin CS, sampled signal FB_d output, the first reference voltage V ref1, the oscillator first electric current I osc1 output and the second electric current I osc2 output, 205 the first output logic signal output, the second output logic signal output, be connected respectively to the grid end of the first transistor N21 and transistor seconds N22, the 205 peak-limitation voltage vth1 according to current monitoring end pin CS input voltage, current monitoring end pin CS signal, sampled signal FB_d, the first reference voltage V ref1, the oscillator first electric current I osc1 and the second electric current I osc2 obtain first output logic signal and second output logic signal of switch power controller;
The grid end of the first transistor N21 is also clamped to the reverse breakdown voltage on ground through the first diode D23, the drain terminal of the first transistor N21 is connected to supply power voltage pin vdd terminal, the source end of transistor seconds N22 is connected to ground, the source end of the first transistor N21 and the control output end GATE function pin that is connected to described PWM switch power controller after the drain terminal of transistor seconds N22 is connected, described GATE function leads ends is to first resistance R 25 of ground series connection.
Further, current-mode is selected the second input termination RI pin of circuit 203, and obtain reference current Iref accordingly, 205 also according to the first reference voltage V ref1 and second reference voltage V ref2 output clock square wave CLK, wherein, the second reference voltage V ref2 is the peak-limitation voltage vth1 of current monitoring end pin CS input voltage, also comprise soft starting circuit 201, the first input end of soft starting circuit 201 connects reference current Iref output, the second input termination clock square wave CLK output of soft starting circuit 201, and under the control of output clock square wave CLK, adopt reference current Iref charging to make output rise to the peak-limitation voltage vth1 of current monitoring end pin CS input voltage.
Further, soft starting circuit 201 comprises charge pump PUMP circuit, described charge pump PUMP circuit input end is controlled jointly by oscillator output square-wave signal CLK and reference current Iref, its output voltage SS is connected to soft start termination comparator C OMP21 and gets positive input, export the selection control signal with COMP21 negative input voltage vth1 result relatively, 2 select the first input end selecting of 1 selector to select the control signal output, and according to selecting control signal from the peak-limitation voltage vth1 of the current monitoring end pin CS input voltage of input and charge pump PUMP circuit input voltage SS, to select, export the second reference voltage V ref2.
Further, FB sample circuit 202 also comprises the second diode D21, the 3rd diode D22, second resistance R 21, the 3rd resistance R 22, the 4th resistance R 23, the 5th resistance R 24, the negative pole of the described second diode D21 meets feedback pin fb, and link to each other with the negative pole of second resistance R 21, the positive pole of the second diode D21 connects the negative pole of the 3rd resistance R 22, and link to each other with the positive pole of the 3rd diode D22, described second resistance R, 21 positive poles link to each other with second source LVDD, the 3rd resistance R 22 positive poles link to each other with second source LVDD, the positive pole of the 4th resistance R 23 links to each other with the negative pole of the 3rd diode D22, the negative pole of the 4th resistance R 23 links to each other with the positive pole of the 5th resistance R 24, and the negative pole of the 5th resistance R 24 is connected to grounding pin.
Further, current-mode selects circuit 203 also to comprise: logic control voltage gating circuit 310, grounding pin end transistor N34, the oscillator first electric current I osc1 end transistor P31, the oscillator second electric current I osc2 end transistor P32, the first comparator C OMP31, hysteresis comparator COMP32, the first operational amplifier OP31, the second operational amplifier OP32, the 3rd operational amplifier OP33, the 6th resistance R 31, the 3rd operational amplifier OP33 positive input is connected to the 2V direct voltage, negative input is connected to the RI pin with output, and the outer meeting resistance R115 that passes through the RI pin forms bias current Iref, the second operational amplifier OP32 positive input is connected to the 4th reference voltage Vref _ L, the second operational amplifier OP32 negative input is connected to an end of the 6th resistance R 31 with output, the first operational amplifier OP31 positive input is connected to the output Vs of logic control voltage gating circuit 310, the first operational amplifier OP31 negative input is connected to the other end of the 6th resistance R 31 and the source end of grounding pin end transistor N34, and the output of the first operational amplifier OP31 is connected to the grid end of grounding pin end transistor N34; The drain terminal of grounding pin end transistor N34 is connected to drain terminal and the grid end Iosc2 of the oscillator second electric current I osc2 end transistor P32, the source end of the oscillator second electric current I osc2 end transistor P32 is connected to grid end and the drain terminal Iosc1 of the oscillator first electric current I osc1 end transistor P31, the source end of the oscillator first electric current I osc1 end transistor P31 is connected to inner low-tension supply LVDD, and first input pin of logic control voltage gating circuit 310 links to each other with the output of COMP31; Second input pin links to each other with the output of COMP32; The 3rd input pin links to each other with the negative input Vref_H of COMP31; The 4th input pin links to each other with the positive input FB_d of COMP31 and COMP32; The 5th input pin links to each other with the negative input Vref_B of COMP32; 310 output links to each other with the positive input of OP31; Wherein logic control voltage gating circuit 310 is used for exporting different magnitudes of voltage by judging the voltage range of FB_d,
In the time of FB_d 〉=Vref_H, Vs=Vref_H, Vref_H are first reference voltage, the oscillator charging and discharging currents
Oscillator is sent out ripple with fixing operating frequency;
In the time of Vref_H＜FB_d 〉=Vref_M-Vos, Vs=FB_d, Vref_M are the 3rd reference voltage, the oscillator charging and discharging currents
The operating frequency of oscillator begins to reduce along with the reduction of output loading frequency;
In the time of FB_d＜Vref_M-Vos, Vs=Vref_B, Vref_B are second reference voltage, the oscillator charging and discharging currents
Under output loading underloading or the Light Condition, oscillator is with the intermittent ripple of sending out of minimum frequency of operation.
Further, logic control voltage gating circuit 310 comprises: comprise the 3rd transistor N31, the 4th transistor N32, the 5th transistor N33, the first inverter INV31, the second inverter INV32, first with the door AND31, second with the door AND32, the 3rd with the door AND33, the grid of described the 3rd transistor N31 connect described first with the door AND31 output, the source electrode of described the 3rd transistor N31 meets the positive input Vs of the first operational amplifier OP31, the drain electrode of described the 3rd transistor N31 meets the 3rd reference voltage V ref_H, the grid of described the 4th transistor N32 connect described second with the door AND32 output, the source electrode of described the 4th transistor N32 meets the positive input Vs of the described first operational amplifier OP31, and the drain electrode of described the 4th transistor N32 meets the sampled voltage FB_d of described sampled signal FB_d output; The grid of described the 5th transistor N33 connect the described the 3rd with the door AND33 output, the source electrode of described the 5th transistor N33 meets the positive input Vs of the described first operational amplifier OP31, and the drain electrode of described the 5th transistor N33 meets the 4th reference voltage V ref_B; The output of the described first inverter INV31 and the second inverter INV32 be connected respectively second with the door AND32 and the 3rd with the door AND33 input; The input of the described first inverter INV31 of output termination of the described first comparator C OMP31 and described first with the door AND31 an input, the input of the described second inverter INV32 of output termination of described hysteresis comparator COMP32, described first with the door AND31 another input and described second with the door AND32 an input.
Further, square wave generation circuit 205 comprises:
Described CS peak current comparator C OMP22 positive input is received the 2 output voltage V ref2 that select 1 selector in succession, negative input connects the current monitoring end pin CS of described PWM switch power controller, and the output of described CS peak current comparator is connected to the input of the first NAND gate I21; Described error comparator COMP23 positive input is connected to sampled signal FB_d output, and negative input connects current monitoring end pin, and the output of described error comparator COMP23 is connected to another input of the first NAND gate I21; The output of the first not gate I21 is held by the R that logical device connects rest-set flip-flop, the moving circuit Soft Driver of described rest-set flip-flop output control floppy drive, and the moving circuit output logic of floppy drive is connected respectively to the grid end of the first transistor N21 and transistor seconds N22;
The input of described oscillator OSC and Vref1, Vref2, Iosc1 is connected with the Iosc2 signal, the output of described oscillator is connected to the S end of rest-set flip-flop, oscillator OSC utilizes bias current Iosc1 and the oscillator OSC of Iosc2 internal capacitance C41 charging, when oscillator OSC internal capacitance C41 voltage during greater than Vref1, bias current Iosc1 and Iosc2 begin oscillator OSC internal capacitance C41 is discharged, when oscillator OSC capacitance voltage during less than Vref2, bias current Iosc1 and Iosc2 begin the charging to oscillator OSC internal capacitance C41 again, and so circulation makes and is output as the concussion square-wave signal.Described oscillator OSC has also determined the maximum functional duty ratio of described PWM switch power controller.
Further, oscillator OSC comprises: comprise the 6th transistor P41, the 7th transistor P42, the 8th transistor P43, the 9th transistor P44, the tenth transistor P45, the 11 transistor N41, the tenth two-transistor N42, the 13 transistor N43, the 14 transistor N44, the 15 transistor N45, oscillator OSC internal capacitance C41, the second comparator C OMP41, the 3rd comparator C OMP42, the 4th with the door AND41, the 5th with the door AND42, the 3rd inverter INV41, the 4th inverter INV42, the 5th inverter INV43, hex inverter INV44 and the 7th inverter INV45;
The grid of described the 6th transistor P41 meets bias voltage Iosc1, and the source electrode of described the 6th transistor P41 meets the described second voltage source LVDD, and the drain electrode of described the 6th transistor P41 connects the source electrode of described the 7th transistor P42;
The grid of described the 7th transistor P42 meets bias voltage Iosc2, and the drain electrode of described the 7th transistor P42 connects the grid of the drain electrode of described the 6th transistor N42, described the 6th transistor N42 and the grid of described the 14 transistor N44;
The grid of described the 8th transistor P43 meets bias voltage Iosc1, and the source electrode of described the 6th transistor P41 meets the described second voltage source LVDD, and the drain electrode of described the 8th transistor P43 connects the source electrode of described the 9th transistor P44;
The grid of described the 9th transistor P44 meets bias voltage Iosc2, the drain electrode of described the 9th transistor P44 connects the source electrode of described the tenth transistor P45, the grid of described the tenth transistor P45 connects the output of described hex inverter INV44 and the input of described the 7th inverter INV45, and the drain electrode of described the tenth transistor P45 connects the drain terminal of described the 15 transistor N45, described oscillator OSC internal capacitance C41 positive pole, the negative input of the described second comparator C OMP41 and the positive input of described the 3rd comparator C OMP42;
The source electrode of described the tenth two-transistor N42 connects the grid of the drain electrode of described the 11 transistor N41, described the 11 transistor N41 and the grid of described the 13 transistor N43;
The source ground of described the 11 transistor N41, the source ground of described the 13 transistor N43, the drain electrode of described the 13 transistor N43 connects the source electrode of described the 14 transistor N44;
The source electrode of described the 15 transistor N45 connects the drain electrode of described the 14 transistor N44, the grid of described the 15 transistor N45 connect the output of described the 4th inverter INV42, described the 5th inverter INV43 input and the described the 4th with the door AND41 an input;
The positive input of the described second comparator C OMP41 meets the first reference voltage V ref1, the output termination the described the 4th of the described second comparator C OMP41 and another input of door AND41;
The negative input of described the 3rd comparator C OMP42 connects voltage 2 and selects 1 the output second reference voltage V ref2, the output termination the described the 5th of described the 3rd comparator C OMP42 and the input of door AND42;
The described the 4th with the input of described the 3rd inverter INV41 of output termination of door AND41, the output termination the described the 5th of described the 3rd inverter INV41 and another input of door AND42, the described the 5th with the input of described the 4th inverter INV42 of output termination of door AND42, the input of the described hex inverter INV44 of output termination of described the 5th inverter INV43, the output of described the 7th inverter INV45 form oscillator square-wave signal CLK.
Further, square wave generation circuit 205 also comprises lead-edge-blanking circuit LEB, the input of described lead-edge-blanking circuit LEB is connected to square-wave signal PWM end, and trigger lead-edge-blanking circuit LEB shielding time delay by the rising edge of described square-wave signal PWM, the output of described lead-edge-blanking circuit LEB is connected to the input of the second NAND gate I22, the output of the first NAND gate I21 is connected to another input of the second not gate I22, and the output of the second NAND gate I22 is connected to the R end of rest-set flip-flop; Or square wave generation circuit 205 also comprises negative circuit, and the output of the first not gate I21 connects the R end of rest-set flip-flop by negative circuit.
The embodiment of the invention also provides a kind of Switching Power Supply, and the Switching Power Supply body is provided with pulse width modulating switch power source controller as the aforementioned.
This pulse width modulating switch power source controller is integrated brand-new frequency conversion mode of operation and discontinuous operation pattern, can make the switching frequency of system can be along with alleviating of load step-down, reduce power consumption to greatest extent.In order to achieve the above object, the present invention is according to the sampled signal FB d size decision-making system load condition of the feedback voltage signal FB of error amplifier, thereby determine the mode of operation of PWM switch power controller, selecting module to produce corresponding operating current by current-mode then is used for the control generator operating frequency, realizes the self adaptation of system works frequency under the different loads.System works frequency self-adaption process is as follows: when system load was heavy condition, the AC/DC Switching Power Supply of described a kind of low standby power loss was operated in the maximum system operating frequency; The supposing the system load begins to reduce load from heavy condition, before load is reduced to the load critical condition that the AC/DC Switching Power Supply of described a kind of low standby power loss sets, the AC/DC Switching Power Supply of described a kind of low standby power loss still is operated in the maximum system operating frequency, after load is reduced to described load critical condition, the AC/DC Switching Power Supply of described a kind of low standby power loss reduces power consumption along with the reduction of load condition begins to reduce switching frequency; In load under the very light or no-load condition, system enters intermittent mode, the AC/DC Switching Power Supply of described a kind of low standby power loss can be closed transducer output fully, only rely on the transformer energy stored to keep loaded work piece, when energy decreases arrives certain value, restarting transducer is the transformer makeup energy, repeats to close the action of transducer output afterwards again, reaches the further purpose that has reduced described Switching Power Supply stand-by power consumption by such method.
Description of drawings
Fig. 1 is the AC/DC switch power supply system application structure block diagram of a kind of low standby power loss of the present invention;
Fig. 2 is a kind of pulse width modulating switch power source controller internal circuit principle assumption diagram of the present invention;
Fig. 3 is the current-mode selecting circuit structure figure for control adaptive oscillator frequency of the present invention;
Fig. 4 is the structure chart of the frequency self-adaption oscillator of the AC/DC Switching Power Supply for a kind of low standby power loss of the present invention.
The main element description of symbols
101: a kind of AC/DC Switching Power Supply of low standby power loss
201: soft starting circuit
The 202:FB sample circuit
203: current-mode is selected circuit
204: the frequency self-adaption oscillator
205: square wave generation circuit
310: logic control voltage gating circuit
Embodiment
Be described in detail below in conjunction with drawings and Examples.
Consult Fig. 1, be the AC/DC switch power supply system application structure block diagram of a kind of low standby power loss of the present invention.It is initial to power on, power switch pipe 107 is closed, and AC power is charged by 103 pairs of electric capacity of starting resistance 104 through bridge rectifier 102, when voltage is higher than chip UVLO_OFF on the electric capacity 104, described PWM Switching Power Supply 101 starts, and sends and enable 107 conductings of signal triggering power switch pipe; The electric current that flows through transformer 106 primary inductances in 107 conduction periods of power tube flows through CS peak current detection resistance 108 with the controlled rate of rise, PWM Switching Power Supply 101 detects the pressure drop that produces on the CS peak current detection resistance 108, thereby control power switch pipe 107 turn-offs; After power tube turn-offs, the crest voltage at 105 pairs of transformers of the clamped circuit of RCD, 106 elementary winding two ends carries out clamped, transformer 106 secondary winding provide energy through 113 pairs of outputs of output rectifier diode, and transformer 106 auxiliary windings provide energy through 114 couples of VDD of VDD rectifier diode simultaneously; Magnitude of voltage and the error amplifier 112 of output voltage sampling resistor 110 and resistance 111 series connection dividing potential drops relatively amplify, error amplifier 112 relatively amplifies later electric current and flows through optical coupling amplifier 109, amplify the FB function leads ends that later electric current flows through PWM Switching Power Supply 101 through optical coupling amplifier 109, PWM Switching Power Supply 101 produces corresponding operating current by the size that detects FB end feedback current and is used for the control generator operating frequency, realizes the self adaptation of system works frequency under the different loads.The operating frequency that can make system reduces and reduces with load, reduces power consumption to greatest extent, promotes efficient.
Consult Fig. 2,3,4, wherein the pulse width modulating switch power source controller comprises:
Supply power voltage pin, grounding pin, feedback pin fb, control output end pin gate, current monitoring end pin cs and bias current arrange port RI pin; And
Current-mode is selected circuit 203, and current-mode selects the first input end of circuit 203 to connect sampled signal FB_d output, and according to the voltage range of voltage sampling signal FB_d, produces corresponding the oscillator first electric current I osc1 and the second electric current I osc2;
Square wave generation circuit 205, the first input end of square wave generation circuit 205, second input, the 3rd input, four-input terminal, the 5th input, the 6th input, meet the peak-limitation voltage vth1 of current monitoring end pin CS input voltage respectively, current monitoring end pin CS, sampled signal FB_d output, the first reference voltage V ref1, the oscillator first electric current I osc1 output and the second electric current I osc2 output, 205 the first output logic signal output, the second output logic signal output, be connected respectively to the grid end of transistor N21 and transistor N22, the 205 peak-limitation voltage vth1 according to current monitoring end pin CS input voltage, current monitoring end pin CS signal, sampled signal FB_d, the first reference voltage V ref1, the oscillator first electric current I osc1 and the second electric current I osc2 obtain first output logic signal and second output logic signal of switch power controller;
The grid end of transistor N21 is also clamped to the reverse breakdown voltage on ground through diode D23, the drain terminal of transistor N21 is connected to supply power voltage pin vdd terminal, the source end of transistor N22 is connected to ground, the source end of transistor N21 and the control output end GATE function pin that is connected to described PWM switch power controller after the drain terminal of transistor N22 is connected, described GATE function leads ends is to resistance R 25 of ground series connection.
Further, current-mode is selected the second input termination RI pin of circuit 203, and obtain reference current Iref accordingly, 205 also according to the first reference voltage V ref1 and second reference voltage V ref2 output clock square wave CLK, wherein, reference voltage V ref2 is the peak-limitation voltage vth1 of current monitoring end pin CS input voltage, also comprise soft starting circuit 201, the first input end of soft starting circuit 201 connects reference current Iref output, the second input termination clock square wave CLK output of soft starting circuit 201, and under the control of output clock square wave CLK, adopt reference current Iref charging to make output rise to the peak-limitation voltage vth1 of current monitoring end pin CS input voltage.
Further, soft starting circuit 201 comprises charge pump PUMP circuit, described charge pump PUMP circuit input end is controlled jointly by oscillator output square-wave signal CLK and reference current Iref, its output voltage SS is connected to soft start termination comparator C OMP21 and gets positive input, export the selection control signal with COMP21 negative input voltage vth1 result relatively, 2 select the first input end selecting of 1 selector to select the control signal output, and according to selecting control signal from the peak-limitation voltage vth1 of the current monitoring end pin CS input voltage of input and charge pump PUMP circuit input voltage SS, to select output reference voltage Vref2.
Further, FB sample circuit 202 also comprises diode D21, diode D22, resistance R 21, resistance R 22, resistance R 23, resistance R 24, the negative pole of described diode D21 meets feedback pin fb, and link to each other with the negative pole of resistance R 21, the negative pole of the anodal connecting resistance R22 of diode D21, and link to each other with the positive pole of diode D22, described resistance R 21 positive poles link to each other with second source LVDD, resistance R 22 positive poles link to each other with second source LVDD, the positive pole of resistance R 23 links to each other with the negative pole of diode D22, the negative pole of resistance R 23 links to each other with the positive pole of resistance R 24, and the negative pole of resistance R 24 is connected to grounding pin.
Further, current-mode selects circuit 203 also to comprise: logic control voltage gating circuit 310, grounding pin end transistor N34, oscillator electric current I osc1 end transistor P31, oscillator electric current I osc2 end transistor P32, comparator C OMP31, hysteresis comparator COMP32, operational amplifier OP31, operational amplifier OP32, operational amplifier OP33, resistance R 31, the 3rd operational amplifier OP33 positive input is connected to the 2V direct voltage, negative input is connected to the RI pin with output, and the outer meeting resistance R115 that passes through the RI pin forms bias current Iref, the second operational amplifier OP32 positive input is connected to direct voltage Vref_L, the second operational amplifier OP32 negative input is connected to an end of the 6th resistance R 31 with output, the first operational amplifier OP31 positive input is connected to the output Vs of logic control voltage gating circuit 310, the first operational amplifier OP31 negative input is connected to the other end of the 6th resistance R 31 and the source end of grounding pin end transistor N34, and the output of the first operational amplifier OP31 is connected to the grid end of grounding pin end transistor N34; The drain terminal of grounding pin end transistor N34 is connected to drain terminal and the grid end Iosc2 of the oscillator second electric current I osc2 end transistor P32, the source end of the oscillator second electric current I osc2 end transistor P32 is connected to grid end and the drain terminal Iosc1 of the oscillator first electric current I osc1 end transistor P31, the source end of the oscillator first electric current I osc1 end transistor P31 is connected to inner low-tension supply LVDD, and first input pin of logic control voltage gating circuit 310 links to each other with the output of COMP31; Second input pin links to each other with the output of COMP32; The 3rd input pin links to each other with the negative input Vref_H of COMP31; The 4th input pin links to each other with the positive input FB_d of COMP31 and COMP32; The 5th input pin links to each other with the negative input Vref_B of COMP32; 310 output links to each other with the positive input of OP31; Wherein logic control voltage gating circuit 310 is used for exporting different magnitudes of voltage by judging the voltage range of FB_d,
In the time of FB_d 〉=Vref_H, Vs=Vref H, Vref_H are first reference voltage, the oscillator charging and discharging currents
Oscillator is sent out ripple with fixing operating frequency;
In the time of Vref_H＜FB_d 〉=Vref_M-Vos, Vs=FB_d, Vref_M are the 3rd reference voltage, the oscillator charging and discharging currents
The operating frequency of oscillator begins to reduce along with the reduction of output loading frequency;
In the time of FB_d＜Vref_M-Vos, Vs=Vref_B, vref_B are second reference voltage, the oscillator charging and discharging currents
Under output loading underloading or the Light Condition, oscillator is with the intermittent ripple of sending out of minimum frequency of operation.
Further, logic control voltage gating circuit 310 comprises: comprise transistor N31, transistor N32, transistor N33, inverter INV31, inverter INV32, with door AND31, with door AND32, with door AND33, the grid of described transistor N31 connects output described and door AND31, the source electrode of described transistor N31 meets the positive input Vs of operational amplifier OP31, the drain electrode of transistor N31 meets direct voltage Vref_H, the grid of described transistor N32 connects output described and door AND32, the source electrode of described transistor N32 meets the positive input Vs of described operational amplifier OP31, and the drain electrode of transistor N32 meets the sampled voltage FB_d of described sampled signal FB_d output; The grid of transistor N33 connects the output with door AND33, and the source electrode of transistor N33 meets the positive input Vs of operational amplifier OP31, and the drain electrode of transistor N33 meets direct voltage Vref_B; The output of inverter INV31 and inverter INV32 be connected respectively with door AND32 and with the input of door AND33; The input of the described inverter INV31 of output termination of described comparator C OMP31 and with the input of door AND31, the input of the described inverter INV32 of output termination of described hysteresis comparator COMP32, with another input of door AND31 and with the input of door AND32.
Further, square wave generation circuit 205 comprises:
Described CS peak current comparator C OMP22 positive input is received the 2 output voltage V ref2 that select 1 selector in succession, negative input connects the current monitoring end pin CS of described PWM switch power controller, and the output of described CS peak current comparator is connected to the input of NAND gate I21; Described error comparator COMP23 positive input is connected to sampled signal FB_d output, and negative input connects current monitoring end pin namely, and the output of error comparator COMP23 is connected to another input of NAND gate I21; The output of not gate I21 is held by the R that logical device connects rest-set flip-flop, the moving circuit Soft Driver of described rest-set flip-flop output control floppy drive, and the moving circuit output logic of floppy drive is connected respectively to the grid end of transistor N21 and transistor N22;
The input of described oscillator OSC and Vref1, Vref2, Iosc1 is connected with the Iosc2 signal, the output of described oscillator is connected to the S end of rest-set flip-flop, oscillator OSC utilizes bias current Iosc1 and the oscillator OSC of Iosc2 internal capacitance C41 charging, when oscillator OSC internal capacitance C41 voltage during greater than Vref1, bias current Iosc1 and Iosc2 begin oscillator OSC internal capacitance C41 is discharged, when oscillator OSC capacitance voltage during less than Vref2, bias current Iosc1 and Iosc2 begin the charging to oscillator OSC internal capacitance C41 again, and so circulation makes and is output as the concussion square-wave signal.Described oscillator OSC has also determined the maximum functional duty ratio of described PWM switch power controller.
Further, oscillator OSC comprises: comprise transistor P41, transistor P42, transistor P43, transistor P44, transistor P45, transistor N41, transistor N42, transistor N43, transistor N44, transistor N45, oscillator OSC internal capacitance C41, comparator C OMP41, comparator C OMP42, with a door AND41, with door AND42, an inverter INV41, inverter INV42, inverter INV43, inverter INV44 and inverter INV45;
The grid of described transistor P41 meets bias voltage Iosc1, and the source electrode of described transistor P41 meets the described second voltage source LVDD, and the drain electrode of described transistor P41 connects the source electrode of described transistor P42;
The grid of described transistor P42 meets bias voltage Iosc2, and the drain electrode of described transistor P42 connects the drain electrode of transistor N42, the grid of transistor N42 and the grid of transistor N44;
The grid of transistor P43 meets bias voltage Iosc1, and the source electrode of transistor P41 meets the described second voltage source LVDD, and the drain electrode of transistor P43 connects the source electrode of transistor P44;
The grid of transistor P44 meets bias voltage Iosc2, the drain electrode of transistor P44 connects the source electrode of transistor P45, the grid of transistor P45 connects the output of inverter INV44 and the input of inverter INV45, and the drain electrode of transistor P45 connects the drain terminal of transistor N45, described oscillator OSC internal capacitance C41 positive pole, the negative input of comparator C OMP41 and the positive input of comparator C OMP42;
The source electrode of transistor N42 connects the drain electrode of transistor N41, the grid of transistor N41 and the grid of transistor N43;
The source ground of transistor N41, the source ground of transistor N43, the drain electrode of transistor N43 connects the source electrode of transistor N44;
The source electrode of transistor N45 connects the drain electrode of transistor N44, the grid of transistor N45 connect inverter INV42 output, inverter INV43 input and with the input of door AND41;
The positive input of comparator C OMP41 meets the first reference voltage V ref1, another input of the output termination of comparator C OMP41 and door AND41;
The negative input of comparator C OMP42 connects voltage 2 and selects 1 output reference voltage Vref2, the input of the output termination of comparator C OMP42 and door AND42;
Input with the output termination inverter INV41 of door AND41, another input of the output termination of inverter INV41 and door AND42, input with the output termination inverter INV42 of door AND42, the input of the output termination inverter INV44 of inverter INV43, the output of inverter INV45 form oscillator square-wave signal CLK.
Further, square wave generation circuit 205 also comprises lead-edge-blanking circuit LEB, the input of described lead-edge-blanking circuit LEB is connected to square-wave signal PWM end, and trigger lead-edge-blanking circuit LEB shielding time delay by the rising edge of described square-wave signal PWM, the output of described lead-edge-blanking circuit LEB is connected to the input of NAND gate I22, the output of NAND gate I21 is connected to another input of not gate I22, and the output of NAND gate I22 is connected to the R end of rest-set flip-flop; Or square wave generation circuit 205 also comprises negative circuit, and the output of the first not gate I21 connects the R end of rest-set flip-flop by negative circuit.
Embodiments of the invention provide a kind of pulse width modulating switch power source controller, the sampled signal FB_d size decision-making system load condition of feedback voltage signal FB by error amplifier, thereby determine the mode of operation of PWM switch power controller, selecting module to produce corresponding operating current by current-mode then is used for the control generator operating frequency, realizes the self adaptation of system works frequency under the different loads.The operating frequency that can make system reduces and reduces with load, reduces power consumption to greatest extent, promotes efficient.
Explain for convenient, below discuss with reference to anti-and swash topological AC/DC Switching Power Supply, but the person of ordinary skill in the field will recognize that the present invention also can be applicable to the PWM Mode A C/DC switch power supply system of other type.In order to make those skilled in the art understand technical scheme of the present invention better, below in conjunction with drawings and embodiments embodiments of the invention are described in further detail simultaneously.
As prepulse width modulated switch power controller, comprise soft starting circuit 201, FB sample circuit 202, current-mode selection circuit 203, frequency self-adaption oscillator 204, CS peak current comparator C OMP22, error comparator COMP23, rest-set flip-flop, lead-edge-blanking circuit LEB, the moving circuit Soft Driver of floppy drive, resistance R 25, diode D23, transistor N21 and N22, NAND gate I21 and I22.
By among Fig. 2 as can be known, soft starting circuit 201 is in the charge pump PUMP of each cycle inner control reference current Iref of the output square wave CLK of frequency self-adaption oscillator 204 fixing charging a period of time, so the output voltage SS of charge pump PUMP is along with each clk cycle constantly increases.In the time of SS≤vth1, Vref2=SS; In the time of SS＞vth1, Vref2=vth1.The output voltage SS of charge pump PUMP is simultaneously relevant with frequency self-adaption oscillator 204 with CS peak current comparator C OMP22, therefore in soft start state CS peak current and adaptive oscillator frequency all along with the voltage rising of SS and increase.The size of FB sample circuit 202 sample detecting FB end feedback current, and feedback current changed the change in voltage change into FB_d, thereby pass through error comparator COMP23 and CS voltage ratio, thereby the conducting duty ratio of control power switch pipe 107, current-mode selects circuit 203 to be used for the control generator operating frequency according to the voltage range generation of FB_d corresponding oscillator electric current I osc1 and Iosc2 simultaneously, realizes the self adaptation of system works frequency under the different loads.The voltage relationship of FB_d and FB end is approximately equal to:
It is high that the output square wave CLK of adaptive oscillator 204 triggers the moving circuit Soft Driver driving of floppy drive GATE function pin through rest-set flip-flop, thereby makes power switch pipe 107 conductings.CS peak current comparator C OMP22 and error comparator COMP23 then control 107 turn-off times of power switch pipe point after the blanking circuit LEB shielding time ahead of the curve, and the maximum ON time of power switch pipe 107 is determined by the output square wave CLK of adaptive oscillator 204.
Current-mode as preceding control adaptive oscillator frequency is selected circuit, comprises logic control voltage gating circuit 310, transistor N34, transistor P31, transistor P32, comparator C OMP31, hysteresis comparator COMP32, operational amplifier OP31, operational amplifier OP32, operational amplifier OP33, resistance R 31.Operational amplifier OP33 positive input connects the reference voltage of 2V, and its output and negative input short circuit form the source with amplifier, and be connected to PWM Switching Power Supply 101 RI function leads ends, and form bias current Iref with resistance 115:
By among the figure as can be known, be core with operational amplifier OP31 and OP32, constitute two negative feedback structures, and determined the size of oscillator charging and discharging currents with resistance R 31.
Comparator C OMP31 and hysteresis comparator COMP32 select a conducting among transistor N31, transistor N32, the transistor N33 according to the voltage range of FB_d, thereby form different Vs magnitudes of voltage.The magnitude of voltage of supposing FB_d changes from high to low:
In the time of FB_d 〉=Vref_H, Vs=Vref H, oscillator charging and discharging currents
Oscillator is sent out ripple with fixing operating frequency;
In the time of Vref_H＜FB_d 〉=Vref_M-Vos, Vs=FB_d, oscillator charging and discharging currents
The operating frequency of oscillator begins to reduce along with the reduction of output loading frequency;
In the time of FB_d＜Vref_M-Vos, Vs=Vref_B, oscillator charging and discharging currents
Under output loading underloading or the Light Condition, oscillator is with the intermittent ripple of sending out of minimum frequency of operation;
The magnitude of voltage of supposing FB_d changes from low to high:
In the time of FB_d＜Vref_M+Vos, vs=Vref_B, oscillator charging and discharging currents
Under output loading underloading or the Light Condition, oscillator is with the intermittent ripple of sending out of minimum frequency of operation;
In the time of vref_H＜FB_d 〉=Vref_M+Vos, Vs=FB_d, oscillator charging and discharging currents
The operating frequency of oscillator begins to reduce along with the reduction of output loading frequency;
In the time of FB_d 〉=Vref_H, Vs=Vref_H, oscillator charging and discharging currents
Oscillator is sent out ripple with fixing operating frequency;
Wherein, Vref_H, Vref_M, Vref_B and Vref_L are reference voltage value, Vos is the hysteresis voltage value of comparator C OMP32, enters and withdraws from intermittence for the AC/DC Switching Power Supply that a kind of low standby power loss is set and send out Vref_H＞Vref_M＞Vref_M-Vos＞Vref_B＞Vref_L between the stagnant regions of ripple.
As the frequency self-adaption oscillator OSC circuit of the AC/DC Switching Power Supply of preceding low standby power loss, comprise transistor P41, transistor P42, transistor P43, transistor P44, transistor P45, transistor N41, transistor N42, transistor N43, transistor N44, transistor N45, capacitor C 41, comparator C OMP41, comparator C OMP42, with a door AND41, with door AND42, an inverter INV41, inverter INV42, inverter INV43, inverter INV44 and inverter INV45.Described oscillator charges to capacitor C 41 by the oscillator bias current of transistor P43 and transistor P44, after the voltage of C41 is greater than Vref1, CP logical signal control transistor P45 turn-offs oscillator biasing charging current, the transistor of CN logical signal control simultaneously N45 oscillator biasing discharging current, oscillator bias current by transistor N43 and transistor N44 is discharged to capacitor C 41, when the voltage of C41 less than after Vref2, CP logical signal control transistor P45 is conducting oscillator biasing charging current again, so moves in circles to form concussion output logic signal CLK.It should be noted that Vref2=SS in soft start-up process, so the frequency of oscillation of CLK also raises along with the rising of soft starting circuit output voltage in the soft start engineering.
The embodiment of the invention also provides a kind of Switching Power Supply, and the Switching Power Supply body is provided with pulse width modulating switch power source controller as the aforementioned.
The sampled signal FB_d size decision-making system load condition of feedback voltage signal FB by error amplifier, thereby determine the mode of operation of PWM switch power controller, selecting module to produce corresponding operating current by current-mode then is used for the control generator operating frequency, realizes the self adaptation of system works frequency under the different loads.The operating frequency that can make system reduces and reduces with load, reduces power consumption to greatest extent, promotes efficient.
The above only is preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also do some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (10)
1. a pulse width modulating switch power source controller is characterized in that: comprise that supply power voltage pin, grounding pin, feedback pin fb, control output end pin gate, current monitoring end pin cs and bias current arrange port RI pin; And
FB sample circuit 202, its input port meets feedback pin fb, and based on the size of feedback pin fb feedback current, feedback current is changed changing into voltage sampling signal FB_d and output;
Current-mode is selected circuit 203, and current-mode selects the first input end of circuit 203 to connect sampled signal FB_d output, and according to the voltage range of voltage sampling signal FB_d, produces corresponding the oscillator first electric current I osc1 and the second electric current I osc2;
Square wave generation circuit 205, the first input end of square wave generation circuit 205, second input, the 3rd input, four-input terminal, the 5th input, the 6th input, meet the peak-limitation voltage vth1 of current monitoring end pin CS input voltage respectively, current monitoring end pin CS, sampled signal FB_d output, the first reference voltage V ref1, the oscillator first electric current I osc1 output and the second electric current I osc2 output, 205 the first output logic signal output, the second output logic signal output, be connected respectively to the grid end of the first transistor N21 and transistor seconds N22, the 205 peak-limitation voltage vth1 according to current monitoring end pin CS input voltage, current monitoring end pin CS signal, sampled signal FB_d, the first reference voltage V ref1, the oscillator first electric current I osc1 and the second electric current I osc2 obtain first output logic signal and second output logic signal of switch power controller;
The grid end of the first transistor N21 is also clamped to the reverse breakdown voltage on ground through the first diode D23, the drain terminal of the first transistor N21 is connected to supply power voltage pin vdd terminal, the source end of transistor seconds N22 is connected to ground, the source end of the first transistor N21 and the control output end GATE function pin that is connected to described PWM switch power controller after the drain terminal of transistor seconds N22 is connected, described GATE function leads ends is to first resistance R 25 of ground series connection.
2. pulse width modulating switch power source controller according to claim 1, it is characterized in that, current-mode is selected the second input termination RI pin of circuit 203, and obtain reference current Iref accordingly, 205 also according to the first reference voltage V ref1 and second reference voltage V ref2 output clock square wave CLK, wherein, the second reference voltage V ref2 is the peak-limitation voltage vth1 of current monitoring end pin CS input voltage, also comprise soft starting circuit 201, the first input end of soft starting circuit 201 connects reference current Iref output, the second input termination clock square wave CLK output of soft starting circuit 201, and under the control of output clock square wave CLK, adopt reference current Iref charging to make output rise to the peak-limitation voltage vth1 of current monitoring end pin CS input voltage.
3. pulse width modulating switch power source controller according to claim 2, it is characterized in that, soft starting circuit 201 comprises charge pump PUMP circuit, described charge pump PUMP circuit input end is controlled jointly by oscillator output square-wave signal CLK and reference current Iref, its output voltage SS is connected to soft start termination comparator C OMP21 and gets positive input, export the selection control signal with COMP21 negative input voltage vth1 result relatively, 2 select the first input end selecting of 1 selector to select the control signal output, and according to selecting control signal from the peak-limitation voltage vth1 of the current monitoring end pin CS input voltage of input and charge pump PUMP circuit input voltage SS, to select, export the second reference voltage V ref2.
4. pulse width modulating switch power source controller according to claim 1, it is characterized in that, FB sample circuit 202 also comprises the second diode D21, the 3rd diode D22, second resistance R 21, the 3rd resistance R 22, the 4th resistance R 23, the 5th resistance R 24, the negative pole of the described second diode D21 meets feedback pin fb, and link to each other with the negative pole of second resistance R 21, the positive pole of the second diode D21 connects the negative pole of the 3rd resistance R 22, and link to each other with the positive pole of the 3rd diode D22, described second resistance R, 21 positive poles link to each other with second source LVDD, the 3rd resistance R 22 positive poles link to each other with second source LVDD, the positive pole of the 4th resistance R 23 links to each other with the negative pole of the 3rd diode D22, the negative pole of the 4th resistance R 23 links to each other with the positive pole of the 5th resistance R 24, and the negative pole of the 5th resistance R 24 is connected to grounding pin.
5. pulse width modulating switch power source controller according to claim 1, it is characterized in that, current-mode selects circuit 203 also to comprise: logic control voltage gating circuit 310, grounding pin end transistor N34, the oscillator first electric current I osc1 end transistor P31, the oscillator second electric current I osc2 end transistor P32, the first comparator C OMP31, hysteresis comparator COMP32, the first operational amplifier OP31, the second operational amplifier OP32, the 3rd operational amplifier OP33, the 6th resistance R 31, the 3rd operational amplifier OP33 positive input is connected to the 2V direct voltage, negative input is connected to the RI pin with output, and the outer meeting resistance R115 that passes through the RI pin forms bias current Iref, the second operational amplifier OP32 positive input is connected to the 4th reference voltage Vref _ L, the second operational amplifier OP32 negative input is connected to an end of the 6th resistance R 31 with output, the first operational amplifier OP31 positive input is connected to the output Vs of logic control voltage gating circuit 310, the first operational amplifier OP31 negative input is connected to the other end of the 6th resistance R 31 and the source end of grounding pin end transistor N34, and the output of the first operational amplifier OP31 is connected to the grid end of grounding pin end transistor N34; The drain terminal of grounding pin end transistor N34 is connected to drain terminal and the grid end Iosc2 of the oscillator second electric current I osc2 end transistor P32, the source end of the oscillator second electric current I osc2 end transistor P32 is connected to grid end and the drain terminal Iosc1 of the oscillator first electric current I osc1 end transistor P31, the source end of the oscillator first electric current I osc1 end transistor P31 is connected to inner low-tension supply LVDD, and first input pin of logic control voltage gating circuit 310 links to each other with the output of COMP31; Second input pin links to each other with the output of COMP32; The 3rd input pin links to each other with the negative input Vref_H of COMP31; The 4th input pin links to each other with the positive input FB_d of COMP31 and COMP32; The 5th input pin links to each other with the negative input Vref_B of COMP32; 310 output links to each other with the positive input of OP31; Wherein logic control voltage gating circuit 310 is used for exporting different magnitudes of voltage by judging the voltage range of FB_d,
In the time of FB_d 〉=Vref_H, Vs=Vref_H, Vref_H are first reference voltage, the oscillator charging and discharging currents
Oscillator is sent out ripple with fixing operating frequency;
In the time of Vref_H＜FB_d 〉=Vref_M-Vos, Vs=FB_d, Vref_M are the 3rd reference voltage, the oscillator charging and discharging currents
The operating frequency of oscillator begins to reduce along with the reduction of output loading frequency;
In the time of FB_d＜Vref_M-Vos, Vs=vref_B, Vref_B are second reference voltage, the oscillator charging and discharging currents
Under output loading underloading or the Light Condition, oscillator is with the intermittent ripple of sending out of minimum frequency of operation.
6. pulse width modulating switch power source controller according to claim 1, it is characterized in that, logic control voltage gating circuit 310 comprises: comprise the 3rd transistor N31, the 4th transistor N32, the 5th transistor N33, the first inverter INV31, the second inverter INV32, first with the door AND31, second with the door AND32, the 3rd with the door AND33, the grid of described the 3rd transistor N31 connect described first with the door AND31 output, the source electrode of described the 3rd transistor N31 meets the positive input vs of the first operational amplifier OP31, the drain electrode of described the 3rd transistor N31 meets the 3rd reference voltage V ref_H, the grid of described the 4th transistor N32 connect described second with the door AND32 output, the source electrode of described the 4th transistor N32 meets the positive input Vs of the described first operational amplifier OP31, and the drain electrode of described the 4th transistor N32 meets the sampled voltage FB_d of described sampled signal FB_d output; The grid of described the 5th transistor N33 connect the described the 3rd with the door AND33 output, the source electrode of described the 5th transistor N33 meets the positive input Vs of the described first operational amplifier OP31, and the drain electrode of described the 5th transistor N33 meets the 4th reference voltage V ref_B; The output of the described first inverter INV31 and the second inverter INV32 be connected respectively second with the door AND32 and the 3rd with the door AND33 input; The input of the described first inverter INV31 of output termination of the described first comparator C OMP31 and described first with the door AND31 an input, the input of the described second inverter INV32 of output termination of described hysteresis comparator COMP32, described first with the door AND31 another input and described second with the door AND32 an input.
7. pulse width modulating switch power source controller according to claim 1 is characterized in that, square wave generation circuit 205 comprises:
Described CS peak current comparator C OMP22 positive input is received the 2 output voltage V ref2 that select 1 selector in succession, negative input connects the current monitoring end pin CS of described PWM switch power controller, and the output of described CS peak current comparator is connected to the input of the first NAND gate I21; Described error comparator COMP23 positive input is connected to sampled signal FB_d output, and negative input connects current monitoring end pin, and the output of described error comparator COMP23 is connected to another input of the first NAND gate I21; The output of the first not gate I21 is held by the R that logical device connects rest-set flip-flop, the moving circuit Soft Driver of described rest-set flip-flop output control floppy drive, and the moving circuit output logic of floppy drive is connected respectively to the grid end of the first transistor N21 and transistor seconds N22;
The input of described oscillator OSC and Vref1, Vref2, Iosc1 is connected with the Iosc2 signal, the output of described oscillator is connected to the S end of rest-set flip-flop, oscillator OSC utilizes bias current Iosc1 and the oscillator OSC of Iosc2 internal capacitance C41 charging, when oscillator OSC internal capacitance C41 voltage during greater than Vref1, bias current Iosc1 and Iosc2 begin oscillator OSC internal capacitance C41 is discharged, when oscillator OSC capacitance voltage during less than Vref2, bias current Iosc1 and Iosc2 begin the charging to oscillator OSC internal capacitance C41 again, and so circulation makes and is output as the concussion square-wave signal.Described oscillator OSC has also determined the maximum functional duty ratio of described PWM switch power controller.
8. pulse width modulating switch power source controller according to claim 7, it is characterized in that oscillator OSC comprises: comprise the 6th transistor P41, the 7th transistor P42, the 8th transistor P43, the 9th transistor P44, the tenth transistor P45, the 11 transistor N41, the tenth two-transistor N42, the 13 transistor N43, the 14 transistor N44, the 15 transistor N45, oscillator OSC internal capacitance C41, the second comparator C OMP41, the 3rd comparator C OMP42, the 4th with the door AND41, the 5th with the door AND42, the 3rd inverter INV41, the 4th inverter INV42, the 5th inverter INV43, hex inverter INV44 and the 7th inverter INV45;
The grid of described the 6th transistor P41 meets bias voltage Iosc1, and the source electrode of described the 6th transistor P41 meets the described second voltage source LVDD, and the drain electrode of described the 6th transistor P41 connects the source electrode of described the 7th transistor P42;
The grid of described the 7th transistor P42 meets bias voltage Iosc2, and the drain electrode of described the 7th transistor P42 connects the grid of the drain electrode of described the 6th transistor N42, described the 6th transistor N42 and the grid of described the 14 transistor N44;
The grid of described the 8th transistor P43 meets bias voltage Iosc1, and the source electrode of described the 6th transistor P41 meets the described second voltage source LVDD, and the drain electrode of described the 8th transistor P43 connects the source electrode of described the 9th transistor P44;
The grid of described the 9th transistor P44 meets bias voltage Iosc2, the drain electrode of described the 9th transistor P44 connects the source electrode of described the tenth transistor P45, the grid of described the tenth transistor P45 connects the output of described hex inverter INV44 and the input of described the 7th inverter INV45, and the drain electrode of described the tenth transistor P45 connects the drain terminal of described the 15 transistor N45, described oscillator OSC internal capacitance C41 positive pole, the negative input of the described second comparator C OMP41 and the positive input of described the 3rd comparator C OMP42;
The source electrode of described the tenth two-transistor N42 connects the grid of the drain electrode of described the 11 transistor N41, described the 11 transistor N41 and the grid of described the 13 transistor N43;
The source ground of described the 11 transistor N41, the source ground of described the 13 transistor N43, the drain electrode of described the 13 transistor N43 connects the source electrode of described the 14 transistor N44;
The source electrode of described the 15 transistor N45 connects the drain electrode of described the 14 transistor N44, the grid of described the 15 transistor N45 connect the output of described the 4th inverter INV42, described the 5th inverter INV43 input and the described the 4th with the door AND41 an input;
The positive input of the described second comparator C OMP41 meets the first reference voltage V ref1, the output termination the described the 4th of the described second comparator C OMP41 and another input of door AND41;
The negative input of described the 3rd comparator C OMP42 connects voltage 2 and selects 1 the output second reference voltage V ref2, the output termination the described the 5th of described the 3rd comparator C OMP42 and the input of door AND42;
The described the 4th with the input of described the 3rd inverter INV41 of output termination of door AND41, the output termination the described the 5th of described the 3rd inverter INV41 and another input of door AND42, the described the 5th with the input of described the 4th inverter INV42 of output termination of door AND42, the input of the described hex inverter INV44 of output termination of described the 5th inverter INV43, the output of described the 7th inverter INV45 form oscillator square-wave signal CLK.
9. pulse width modulating switch power source controller according to claim 7, it is characterized in that, square wave generation circuit 205 also comprises lead-edge-blanking circuit LEB, the input of described lead-edge-blanking circuit LEB is connected to square-wave signal PWM end, and trigger lead-edge-blanking circuit LEB shielding time delay by the rising edge of described square-wave signal PWM, the output of described lead-edge-blanking circuit LEB is connected to the input of the second NAND gate I22, the output of the first NAND gate I21 is connected to another input of the second not gate I22, and the output of the second NAND gate I22 is connected to the R end of rest-set flip-flop; Or square wave generation circuit 205 also comprises negative circuit, and the output of the first not gate I21 connects the R end of rest-set flip-flop by negative circuit.
10. Switching Power Supply, it is characterized in that: the Switching Power Supply body is provided with as the described pulse width modulating switch power source controller of the arbitrary claim of claim 1 to 9.
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