CN103187381B - Lead frame encapsulation structure - Google Patents
Lead frame encapsulation structure Download PDFInfo
- Publication number
- CN103187381B CN103187381B CN201110456501.7A CN201110456501A CN103187381B CN 103187381 B CN103187381 B CN 103187381B CN 201110456501 A CN201110456501 A CN 201110456501A CN 103187381 B CN103187381 B CN 103187381B
- Authority
- CN
- China
- Prior art keywords
- lead frame
- encapsulation structure
- wire portion
- frame encapsulation
- present
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Abstract
The invention discloses a kind of lead frame encapsulation structure, this lead frame encapsulation structure includes: at least one load bearing seat, is used for carrying one chip; And at least one lead frame, the first end comprising electric connection one printed circuit board (PCB), one second end being electrically connected this chip, and connect a wire portion of this first end and this second end; Wherein, the height of this wire portion is lower than the height of this first end and this second end.
Description
Technical field
The present invention relates to a kind of lead frame encapsulation structure, particularly relate to the lead frame encapsulation structure of the low electromagnetism of a kind of tool and low cross-talk.
Background technology
Integrated circuit (integrated circuit, IC) encapsulation can according to the loading material of chip, be divided into leaded package (lead frame package), rigid plastic support plate encapsulation (laminate substratepackage), soft support plate encapsulation (tape package), and ceramic substrate encapsulation (ceramic package).Wherein, leaded package possesses the feature such as low cost and low speed signal transmission requirement (namely inapplicable at high speed transmission of signals interface, as DDR3-1333Mbps, HDMI or USB3).
Please refer to Fig. 1, Fig. 2 and Fig. 3, the vertical view that the schematic appearance that Fig. 1 is existing lead frame encapsulation structure 10, Fig. 2 are existing lead frame encapsulation structure 10, and Fig. 3 is the structural map of existing lead frame encapsulation structure 10.As shown in Figure 1, 2, lead frame encapsulation structure 10 comprises multiple lead frame 100 and chip 11.Lead frame 100 includes outer pin 102, interior pin 104 and wire portion 106.Wherein, outer pin 102 is electrically connected printed circuit board (PCB) (being not shown in figure), interior pin 104 is electrically connected chip 11 by wire bonds mode (gold thread 103 as shown in Figure 2), and wire portion 106 is connected between interior pin 102 and outer pin 104.As shown in Figure 3, lead frame encapsulation structure 10 also includes the load bearing seat 12 for carries chips 11, and is used for the packing colloid (molding) 13 of coated wire frame 100 and chip 11.
From the above, lead frame encapsulation structure 10 non-multilayer type structure (multi-layer), therefore not there is reference ground plane (the reference ground plane) design on picture printed circuit board (PCB), thus there is impedance Control difficulty, cross-talk (crosstalk) problem, and the disappearance such as the height circulation inductance value (loop inductance) of distribution network (power distributionnetwork, PDN).For solving above-mentioned disappearance, in the prior art, lead frame encapsulation structure 10 is provided with an earth connection between each lead frame 100, but this mode can reduce the magnitude setting of lead frame 100, and the quantity thus causing signal to export (pin out) reduces.
Summary of the invention
Therefore, main purpose of the present invention is to provide a kind of conducting wire frame structure, uses and solves the problem.
The present invention discloses a kind of lead frame encapsulation structure, and this lead frame encapsulation structure includes: at least one load bearing seat, is used for carrying one chip; And at least one lead frame, the first end comprising electric connection one printed circuit board (PCB), one second end being electrically connected this chip, and connect a wire portion of this first end and this second end; Wherein, the height of this wire portion is lower than the height of this first end and this second end.
Accompanying drawing explanation
Fig. 1 is the outside drawing of an existing lead frame encapsulation structure.
Fig. 2 is the vertical view of an existing lead frame encapsulation structure.
Fig. 3 is the structural map of an existing lead frame encapsulation structure.
Fig. 4 is the schematic diagram of the embodiment of the present invention one lead frame encapsulation structure.
Fig. 5 is the schematic diagram that the embodiment of the present invention one lead frame encapsulation structure is arranged on printed circuit board (PCB).
Fig. 6 is the schematic diagram of the embodiment of the present invention one signal entrance loss.
Fig. 7 is the schematic diagram of the embodiment of the present invention one signal reflex loss.
Fig. 8 is the schematic diagram of the long-range cross-talk of the embodiment of the present invention one.
Fig. 9 is the schematic diagram of the embodiment of the present invention one near-end crosstalk interference.
Wherein, description of reference numerals is as follows:
10,40 lead frame encapsulation structure
100,400 lead frames
11,41 chips
12,42 load bearing seats
13,43 packing colloids
102,402 outer pins
104, pin in 404
106,406 wire portions
103,403 gold threads
50 ground planes
Port 1 first end
Port 2 second end
Port 3 the 3rd end
Port 4 the 4th end
CL current cycle
Embodiment
Please refer to Fig. 4, Fig. 4 is the schematic diagram of the embodiment of the present invention one lead frame encapsulation structure 40.Lead frame encapsulation structure 40 comprises lead frame 400, chip 41, load bearing seat 42 and packing colloid 43.Lead frame 400 includes outer pin 402, interior pin 404 and wire portion 406.Wherein, outer pin 402 is electrically connected printed circuit board (PCB) (not indicating in the diagram), interior pin 404 is electrically connected chip 41 by gold thread 403, and wire portion 406 is electrically connected interior pin 402 and outer pin 404.Load bearing seat 42 is used for carries chips 41.Packing colloid 43 is used for coated wire frame 400 and chip 41.In this embodiment, outer pin 402 can be sea-gull aerofoil profile (Gull-Wing) pin.
It should be noted that wire portion 406 height of the embodiment of the present invention need lower than the height of outer pin 402 and interior pin 404, to form the wire portion 406 of concave shape.Please simultaneously comparison diagram 3 and Fig. 4, can know the wire portion 406 finding out the embodiment of the present invention, be in the shape to lower recess compared to existing wire portion 106.Separately please refer to Fig. 5, Fig. 5 is the schematic diagram that the lead frame encapsulation structure 40 of the embodiment of the present invention is arranged on printed circuit board (PCB).As shown in Figure 5, when lead frame encapsulation structure 40 is arranged on printed circuit board (PCB), wire portion 406 is compared to existing wire portion 106, more press close to the ground plane 50 on printed circuit board (PCB), therefore, current cycle (current loop) CL that signal flows and formed on wire portion 406 is concentrated in the flowing underneath of wire portion 406, uses and reduces cross-talk (crosstalk).In addition, because wire portion 406 comparatively presses close to the ground plane 50 of printed circuit board (PCB), the field regime that wire portion 406 produces also comparatively concentrates between wire portion 406 and ground plane 50, therefore can reduce the impact on peripheral guidewires frame 400, and reduce electromagnetic interference.In simple terms, the lead frame encapsulation structure 40 of the embodiment of the present invention utilizes the ground plane 50 of printed circuit board (PCB) as the ground connection of lead frame 400, uses and reduce signal and electromagnetic interference.
Please refer to Fig. 6, Fig. 7, Fig. 8 and Fig. 9, Fig. 6 is the schematic diagram of the embodiment of the present invention one signal entrance loss (Insertion Loss), Fig. 7 is the schematic diagram of the embodiment of the present invention one signal reflex loss (ReturnLoss), Fig. 8 is the schematic diagram of long-range string news (Far-End Crosstalk) of the embodiment of the present invention one, and Fig. 9 is the schematic diagram of embodiment of the present invention near-end crosstalk news (Near-End Crosstalk).In figure 6, suppose that signal transfers to the second end Port 2 from the first end Port 1 of lead frame 400.As shown in Figure 6, compared to the structure of existing lead frame 100, the signal entrance loss of the lead frame 400 of the embodiment of the present invention is a little less than the signal entrance loss of existing lead frame 100.In the figure 7, compared to the structure of existing lead frame 100, the lead frame 400 of the embodiment of the present invention also loses lower than the signal reflex of existing lead frame 100 in the signal reflex loss of first end Port 1.For example, under frequency 3000MHz, the signal reflex loss late of lead frame 400 about reduces 6dB.In addition, in fig. 8, suppose that signal transfers to the second end Port 2 from the first end Port 1 of lead frame 400.In lead frame encapsulation structure 40, another lead frame 400 of most adjacent wires frame 400 can be subject to cross-talk; In another lead frame 400, the 3rd end Port 3 of the first end Port 1 of adjacent wires frame 400 is called near-end in string news phenomenon, and is called long-range in string news phenomenon from the 4th end Port 4 away from first end Port 1.As shown in Figure 8, compared to the structure of existing lead frame 100, the lead frame 400 of the embodiment of the present invention is in the long-range cross-talk of long-range cross-talk lower than existing lead frame 100.For example, under frequency 1500MHz, long-range cross-talk about reduces 10dB.In addition, in fig .9, the lead frame 400 of the embodiment of the present invention in the cross-talk of near-end also lower than existing lead frame 100.For example, under frequency 1500MHz, near-end crosstalk interference about reduces 3dB.
From the above, wire portion 106 compared to existing lead frame 100 is pin 104 and outer pin 102 in level connection joint, thus cannot arrange the ground plane of printed circuit, cause the problems such as string news and electromagnetic interference, the wire portion 406 of the lead frame 400 of the embodiment of the present invention is pin 104 and outer pin 102 in concave shape connection, lead frame 400 can be arranged and press close to ground plane, and then effectively reduce the problems such as string news and electromagnetic interference.It should be noted that at encapsulating structure in appearance, the lead frame encapsulation structure 40 of the embodiment of the present invention can be identical with the outward appearance of existing lead frame encapsulation structure, and do not need the making mould changing current lead frame, therefore can save cost of manufacture.For example, after producing lead frame 100, punching press can be carried out to wire portion 106, to form the wire portion 406 to recessed folding.
In sum, the present invention proposes a kind of new lead frame encapsulation structure, and compared to known conducting wire frame structure, the lead frame of the embodiment of the present invention is depressed the ground plane of printed circuit board (PCB), therefore circulation inductance value can effectively be reduced, to reduce the problems such as string news, electromagnetic interference.
The foregoing is only the preferred embodiments of the present invention, be not limited to the present invention, for a person skilled in the art, the present invention can have various modifications and variations.Within the spirit and principles in the present invention all, any amendment done, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (3)
1. a lead frame encapsulation structure, includes:
At least one load bearing seat, is used for carrying one chip; And
At least one lead frame, is comprised a first end of electric connection one printed circuit board (PCB), is electrically connected one second end of this chip by a gold thread, and connect a wire portion of this first end and this second end;
Wherein, this wire portion has a length, and this length is the length extending to this gold thread from this first end;
Wherein, in this length, the height of this wire portion, lower than the height of this first end and this gold thread, makes the reference ground plane of a ground plane as this at least one lead frame of this printed circuit board (PCB), to reduce cross-talk;
Wherein, this first end is a sea-gull aerofoil profile pin.
2. lead frame encapsulation structure as claimed in claim 1, is characterized in that, this wire portion carrys out the height of height of formation lower than this first end and this second end by an impact style.
3. lead frame encapsulation structure as claimed in claim 1, it is characterized in that, this second end is electrically connected this chip by a wire bonds mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110456501.7A CN103187381B (en) | 2011-12-30 | 2011-12-30 | Lead frame encapsulation structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110456501.7A CN103187381B (en) | 2011-12-30 | 2011-12-30 | Lead frame encapsulation structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103187381A CN103187381A (en) | 2013-07-03 |
| CN103187381B true CN103187381B (en) | 2015-09-16 |
Family
ID=48678473
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110456501.7A Expired - Fee Related CN103187381B (en) | 2011-12-30 | 2011-12-30 | Lead frame encapsulation structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103187381B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5157480A (en) * | 1991-02-06 | 1992-10-20 | Motorola, Inc. | Semiconductor device having dual electrical contact sites |
| CN1153997A (en) * | 1995-12-29 | 1997-07-09 | Lg半导体株式会社 | Improved integrated chip package with reduced dimensions |
| US6865804B2 (en) * | 1999-08-20 | 2005-03-15 | Cardiac Pacemakers, Inc. | Method for integrated EMI shielding |
| CN1697172A (en) * | 2004-05-12 | 2005-11-16 | 宏连国际科技股份有限公司 | Die set for wire frame of wafer |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100427749B1 (en) * | 2002-05-07 | 2004-04-28 | 엠케이전자 주식회사 | Au-Ag alloy bonding wire for semiconductor device |
-
2011
- 2011-12-30 CN CN201110456501.7A patent/CN103187381B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5157480A (en) * | 1991-02-06 | 1992-10-20 | Motorola, Inc. | Semiconductor device having dual electrical contact sites |
| CN1153997A (en) * | 1995-12-29 | 1997-07-09 | Lg半导体株式会社 | Improved integrated chip package with reduced dimensions |
| US6865804B2 (en) * | 1999-08-20 | 2005-03-15 | Cardiac Pacemakers, Inc. | Method for integrated EMI shielding |
| CN1697172A (en) * | 2004-05-12 | 2005-11-16 | 宏连国际科技股份有限公司 | Die set for wire frame of wafer |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103187381A (en) | 2013-07-03 |
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| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20150916 Termination date: 20201230 |