CN103179809A - Method of fabricating circuit board - Google Patents

Method of fabricating circuit board Download PDF

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Publication number
CN103179809A
CN103179809A CN2012102756620A CN201210275662A CN103179809A CN 103179809 A CN103179809 A CN 103179809A CN 2012102756620 A CN2012102756620 A CN 2012102756620A CN 201210275662 A CN201210275662 A CN 201210275662A CN 103179809 A CN103179809 A CN 103179809A
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CN
China
Prior art keywords
conductor layer
mentioned
circuit board
layer
wiring
Prior art date
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Pending
Application number
CN2012102756620A
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Chinese (zh)
Inventor
村松正树
和泉正郎
西尾贤治
佐藤裕纪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Niterra Co Ltd
Original Assignee
NGK Spark Plug Co Ltd
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Filing date
Publication date
Application filed by NGK Spark Plug Co Ltd filed Critical NGK Spark Plug Co Ltd
Publication of CN103179809A publication Critical patent/CN103179809A/en
Pending legal-status Critical Current

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/465Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer having channels for the next circuit layer
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/48After-treatment of electroplated surfaces
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25DPROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D3/00Electroplating: Baths therefor
    • C25D3/02Electroplating: Baths therefor from solutions
    • C25D3/38Electroplating: Baths therefor from solutions of copper
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/02Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
    • H05K2203/025Abrading, e.g. grinding or sand blasting
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/04Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
    • H05K3/045Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by making a conductive layer having a relief pattern, followed by abrading of the raised portions

Abstract

The invention provides a method of fabricating a circuit board, which is capable of suppressing excessive cutting or lack of cutting of a conductor layer to serve as a wiring layer. According to the method of fabricating a circuit board of the invention, the circuit board includes at least one insulation layer and at least one wiring layer, the method including a first step of forming a wiring trench in a surface of the insulation layer, a second step of forming a conductor layer serving as the wiring layer in the wiring trench such that at least a portion of the conductor layer is embedded in the wiring trench, and a third step of cutting a surface of the conductor layer with a cutting tool to form the wiring layer.

Description

The manufacture method of circuit board
Technical field
The present invention relates to a kind of manufacture method of circuit board, particularly relate to a kind of wiring trench that forms wiring use in insulating barrier, form the manufacture method of the circuit board of conductor layer in this wiring trench.
Background technology
As the manufacture method of circuit board, for example known for a long time have a semi-additive process.In semi-additive process, utilize vacuum hotpressing machine to carry out pressurized, heated with epoxy resin as the sandwich that the membranaceous dielectric resin material of main component forms to overlapping on core substrate, carry out crimping while making membranaceous dielectric resin material hot curing, utilize Ear Mucosa Treated by He Ne Laser Irradiation etc. to form via on this membranaceous dielectric resin material, form the electroless plating layer on the membranaceous dielectric resin material of this via inwall comprising afterwards.Afterwards, form anti-coating with target shape on this electroless plating layer, this anti-coating is plated as mask the wiring pattern that obtains target shape by electrolysis.
But in recent years, the miniaturization development of wiring pattern adopts above-mentioned semi-additive process to be difficult to tackle this miniaturization.In semi-additive process, form wiring pattern on membranaceous dielectric resin material, but in this case, the lower surface of wiring is contacted with membranaceous dielectric resin material.Therefore, wiring pattern is got over miniaturization, and the contact area of itself and membranaceous dielectric resin material more reduces, and therefore, bonding force dies down, and might peel off in manufacturing process halfway.In addition, for anti-coating, be also that wiring pattern is got over miniaturization, the contact area of itself and membranaceous dielectric resin material more reduces, and bonding force dies down, and therefore, might peel off in manufacturing process halfway.
Therefore, as solution to the problems described above, proposed to form wiring (for example with reference to patent documentation 1) by inlaying process (also referred to as trench fill (Trench Filling) method).In the described inlaying process of patent documentation 1, utilize photoetching process and be etched in the wiring trench that becomes target shape on membranaceous dielectric resin material, utilize to electroplate in wiring trench and membranaceous dielectric resin material surface on formed conductor layer, afterwards by CMP(Chemical Mechanical Polishing: cmp) the membranaceous dielectric resin material of grinding surface, removed unnecessary conductor layer in addition in wiring trench.
As mentioned above, adopt inlaying process, form wiring in wiring trench, therefore, state, the i.e. wiring that connects with lower surface and the both side surface of wiring and the inwall that is formed at the ditch of membranaceous dielectric resin material is embedded to the state formation in ditch, therefore, can reduce the possibility of peeling off in wiring or anti-coating manufacturing process halfway.
Patent documentation 1: TOHKEMY 2008-85373 communique
As mentioned above, adopt inlaying process, can tackle the miniaturization of wiring pattern.But CMP is subjected to the impact of abradant surface shape, and is therefore different according to the position, produces the zone of conductor layer over-lapping or the deficiency of conductor layer grinding on the contrary.In addition, even in the situation that utilize method, for example wet etching beyond CMP to remove unnecessary conductor layer, the thickness of the plated film of formation is also inhomogeneous, therefore, produces same problem.
In the situation that the conductor layer over-lapping, the attenuation of wiring thickness might produce the problem of the current flowing that can't make regulation.On the other hand, in the situation that the grinding deficiency of conductor layer, might produce because of grind not enough remaining conductor layer cause connecting up between the problem of electrical short.
Summary of the invention
The present invention makes in order to tackle above-mentioned situation, and its purpose is to provide the manufacture method of the not enough circuit board of a kind of excessive cutting, cutting of the conductor layer that can suppress to become wiring layer.
In order to achieve the above object, the present invention is a kind of manufacture method of circuit board, and this circuit board has the above insulating barrier of one deck and the above wiring layer of one deck, and wherein, the manufacture method of this circuit board has: the 1st operation forms wiring trench in above-mentioned insulating barrier; The 2nd operation, the mode that is embedded in above-mentioned wiring trench with at least a portion of the conductor layer that will become above-mentioned wiring layer forms this conductor layer; And the 3rd operation, cut the surface of above-mentioned conductor layer with cutting tools, thereby form above-mentioned wiring layer.
Adopt the present invention, the mode that is embedded in the wiring trench that is formed at insulating barrier with at least a portion of the conductor layer that will become wiring layer forms this conductor layer, cuts the surface of the conductor layer of this formation with cutting tools.Therefore, when cutting conductor layer surperficial, be difficult to be subject to the impact of the shape (for example concavo-convex) of insulating barrier, conductor layer, can suppress conductor layer excessive cutting, cutting is not enough.In addition, owing to utilizing cutting to process, therefore, that sees when being difficult to produce attrition process on the metal material of conductor layer sink.And, due to the impact of the shape that is difficult to be subject to insulating barrier, conductor layer (for example concavo-convex), therefore, cut face become smooth (smooth).Therefore, even in the situation that stacked multilayer dielectric layer and wiring layer, it is smooth that substrate surface also becomes, and defocuses in the time of can being suppressed at exposure (Defocus).
In addition, as cutting tools, can use diamond tool.Because diamond tool has very high mar proof, therefore, can use for a long time.In addition, because the surface roughness after cutting is lower, therefore, can be suppressed at produce on the wiring layer surface concavo-convex.Therefore, can be reduced in the electric noise of wiring layer place's generation.In addition, because this diamond tool ground hardness is higher, therefore, can carries out cut at a high speed and boost productivity.
In addition, in a technical scheme of the present invention, in the 3rd operation, can cut the surface of insulating barrier in the surface of cutting conductor layer, thereby form matsurface on insulating barrier.By form matsurface on insulating barrier, improve this insulating barrier and the adaptation that is layered in the insulating barrier on the cutting face.In addition, because the surface of insulating barrier is cut, therefore, needn't utilize etching to remove the lip-deep wiring material that is attached to insulating barrier when forming wiring layer.Therefore, manufacturing process that can the simplified wiring substrate.
In addition, in another technical scheme of the present invention, in the 3rd operation, can cut several times.By cutting is divided into repeatedly, can carry out accurate cut.In addition, even in the situation that conductor layer is thicker also can cut.
In addition, in another technical scheme of the present invention, the 2nd operation can be divided into and utilize electroless plating to form the operation of the 1st conductor layer in wiring trench and utilize cathode copper to be plated in the operation that forms the 2nd conductor layer on the 1st conductor layer and implement.By carry out electroless plating on insulating barrier, can utilize film forming speed electrolysis faster to plate to form conductor layer.Therefore, improve the productivity ratio of circuit board.
As mentioned above, adopt the present invention, the manufacture method of the not enough circuit board of a kind of excessive cutting, cutting of the conductor layer that can suppress to become wiring layer is provided.
Description of drawings
Fig. 1 is the cutaway view of the circuit board of execution mode.
Fig. 2 is the manufacturing procedure picture (core substrate operation) of the circuit board of execution mode.
Fig. 3 is the manufacturing procedure picture (lamination operation) of the circuit board of execution mode.
Fig. 4 is the manufacturing procedure picture (lamination operation) of the circuit board of execution mode.
Fig. 5 is the manufacturing procedure picture (lamination operation) of the circuit board of execution mode.
Fig. 6 is the manufacturing procedure picture (solder mask operation) of the circuit board of execution mode.
Fig. 7 is the manufacturing procedure picture (rear end operation) of the circuit board of execution mode.
Fig. 8 means the figure of the grinding example that adopts CMP.
Fig. 9 is the SEM photo in the cutting face of embodiment.
Embodiment
Below, the execution mode that present invention will be described in detail with reference to the accompanying.In addition, in the following description, the explanation embodiments of the present invention as an example of the circuit board that is formed with the lamination layer on core substrate example, but can be also the circuit board with core substrate.
Execution mode
Fig. 1 is the cutaway view of the circuit board 1 of execution mode.Circuit board 1 comprises core substrate 2, is formed on two lip-deep lamination layer 3(face side of core substrate 2), lamination layer 13(rear side), be formed on the solder mask 4(face side on lamination layer 3), be formed on the solder mask 14(rear side on lamination layer 13), be formed on the solder projection 5(face side on the splicing ear T1 of lamination layer 3) and be formed on solder ball 15(rear side on the splicing ear T11 of lamination layer 13).
Core substrate 2 is the tabular resin substrates that are made of heat-resistant resin plate (such as the bismaleimide-triazine resin plate), fiber-reinforced resin plate (such as glass reinforced epoxy) etc.Be formed with respectively the core conductor layer 21,22 that forms metal line L1, L11 on the surface of core substrate 2 and the back side.In addition, be formed with on core substrate 2 and utilize drill bit etc. to run through the through hole 23 that forms is set, wall is formed be used to the via conductors 24 that makes core conductor layer 21,22 mutual conductings within it.And through hole 23 is filled by the resin buried via hole materials such as epoxy resin 25.
The structure of face side
Lamination layer 3 by the resin insulating barrier 31 of the face side that is layered in core substrate 2,33 and the wiring layer 32,34 that is respectively formed on resin insulating barrier 31,33 consist of.Resin insulating barrier 31 is made of the heat-curing resin constituent.On resin insulating barrier 31, be formed with wiring trench 31a and via 31b with target shape, in this wiring trench 31a and via 31b, utilize galvanoplastic to be formed with and be used to form the wiring layer 32 of metal line L2 and core conductor layer 21 and wiring layer 32 are electrically connected to the via conductor 35 of getting up.
Resin insulating barrier 33 is made of the heat-curing resin constituent.On resin insulating barrier 33, be formed with wiring trench 33a and via 33b with target shape, in this wiring trench 33a and via 33b, utilize galvanoplastic to be formed with and have the wiring layer 34 of splicing ear T 1 and wiring layer 32 and wiring layer 34 are electrically connected to the via conductor 36 of getting up.Splicing ear T1 is for example the splicing ear that is connected with semiconductor chip.In addition, on the surface of splicing ear T1, utilize electroless plating and be coated with nickel (Ni), and on nickel (Ni), utilize electroless plating and be coated with gold (Au).
Solder mask 4 is by forming on the surface that membranaceous or aqueous solder mask layer is stacked in lamination layer 3.Be formed with the opening 4a that the part be used to the surface that makes each splicing ear T1 exposes on solder mask 4.Therefore, each splicing ear T1 is in the state that its surperficial part utilizes opening 4a to expose from solder mask 4.That is, the opening 4a of solder mask 4 becomes the SMD(solder mask define that the part on the surface that makes each splicing ear T1 exposes, and solder mask limits) shape.
Form in opening 4a the solder projection 5 that consists of such as the scolder that is not contained in fact Pb by Sn-Ag, Sn-Cu, Sn-Ag-Cu, Sn-Sb etc. is electrically connected to splicing ear T1.In addition, to the surperficial mounting semiconductor chip of circuit board 1 etc. the time, reflux by the solder projection 5 that makes circuit board 1, the splicing ear of the splicing ear T1 of circuit board 1 and semiconductor chip etc. is electrically connected to.
The structure of rear side
Lamination layer 13 by the resin insulating barrier 131 of the rear side that is layered in core substrate 2,133 and the wiring layer 132,134 that is respectively formed on resin insulating barrier 131,133 consist of.Resin insulating barrier 131 is made of the heat-curing resin constituent.On resin insulating barrier 131, be formed with wiring trench 131a and via 131b with target shape, in this wiring trench 131a and via 131b, utilize galvanoplastic to be formed with and be used to form the wiring layer 132 of metal line L12 and core conductor layer 22 and wiring layer 132 are electrically connected to the via conductor 135 of getting up.
Resin insulating barrier 133 is made of the heat-curing resin constituent.On resin insulating barrier 133, be formed with wiring trench 133a and via 133b with target shape, in this wiring trench 133a and via 133b, utilize galvanoplastic to be formed with and have the wiring layer 134 of splicing ear T11 and wiring layer 132 and wiring layer 134 are electrically connected to the via conductor 136 of getting up.Splicing ear T11 is such as being the splicing ear that is connected with motherboard, slot etc. (below be called motherboard etc.).In addition, on the surface of splicing ear T11, utilize electroless plating and be coated with nickel (Ni), and on nickel (Ni), utilize electroless plating and be coated with gold (Au).
Solder mask 14 is by forming on the surface that membranaceous or aqueous solder mask layer is stacked in lamination layer 13.Be formed with the opening 14a that the part be used to the surface that makes each splicing ear T11 exposes on solder mask 14.Therefore, each splicing ear T11 is in the state that its surperficial part utilizes opening 14a to expose from solder mask 14.That is, the opening 14a of solder mask 14 becomes the SMD shape that the part on the surface that makes each splicing ear T11 exposes.
Form in opening 14a such as making and do not contain in fact by Sn-Ag, Sn-Cu, Sn-Ag-Cu, Sn-Sb etc. the solder ball 15 that the scolder of Pb consists of and be electrically connected to splicing ear T11.In addition, when motherboard etc. is installed to the back side of circuit board 1, reflux by the solder ball 15 that makes circuit board 1, the splicing ear of the splicing ear T11 of circuit board 1 and motherboard etc. is electrically connected to.
The manufacture method of circuit board 1
Fig. 2~Fig. 4 is for the figure of explanation with reference to the manufacturing process of the circuit board 1 of Fig. 1 explanation.Below, the manufacture method of circuit board 1 is described with reference to Fig. 2~Fig. 4.
Core substrate operation: Fig. 2
Preparation is pasted with the copper-clad laminated board of Copper Foil on the surface of tabular resin substrate and the back side.In addition, use drill bit to carry out perforate processing to copper-clad laminated board, become in advance the through hole of through hole 23 in the pre-position.Then, by carrying out electroless plating copper and electrolytic copper plating in accordance with known method in the past, form via conductors 24 at the inwall place of through hole 23, form copper coating (with reference to (a) of Fig. 2) on two surfaces of copper-clad laminated board.
Afterwards, utilize in 25 pairs of via conductors 24 of resin buried via hole material such as epoxy resin and fill.And, the copper coating that is formed on the Copper Foil on copper-clad laminated board two surfaces is etched into target shape, be formed for respectively becoming the core conductor layer 21,22 of metal line L1, L11 on the surface of copper-clad laminated board and the back side, obtain core substrate 2(with reference to Fig. 2 (b)).In addition, after being desirably in the operation that forms through hole 23, removing the de-smear of the glue slag of processing part and process.
Lamination operation: Fig. 3~Fig. 5
Be configured as overlappingly respectively on the surface of core substrate 2 and the back side resin insulating barrier 31,131, with the membranaceous dielectric resin material of epoxy resin as main component.Then, utilize vacuum hotpressing machine to this sandwich pressurized, heated, while make membranaceous dielectric resin material hot curing carry out crimping.Then, come irradiating laser with in the past known laser processing device, form respectively wiring trench 31a, 131a and via 31b, 131b(with reference to Fig. 3 (a) in resin insulating barrier 31,131).After having formed wiring trench 31a, 131a and via 31b, 131b, carry out the processing with wiring trench 31a, 131a and via 31b, 131b surface roughening.In addition, also can form wiring trench 31a, 131a and via 31b, 131b by exposure, development.
Then, carry out electroless plating to comprising wiring trench 31a, 131a and via 31b, 131b on interior resin insulating barrier 31,131 surface, form electrolytic copper free coating (the 1st conductor layer) C1 in the inside of the inside that comprises wiring trench 31a, 131a and via 31b, 131b on interior resin insulating barrier 31,131 surface.Then, carry out the electrolysis plating, form electrolytic copper plating layer (the 2nd conductor layer) C2(with reference to Fig. 3 (b) on electrolytic copper free coating C1).
Then, use diamond tool to cut several times the conductor layer that is consisted of by electrolytic copper free coating C1 and electrolytic copper plating layer C2 on thickness direction, remove unnecessary electrolytic copper free coating C1 and electrolytic copper plating layer C2(with reference to Fig. 4 (a)), obtain wiring layer 32,132 and via conductor 35,135(with reference to (b) of Fig. 4).In addition, after Fig. 4 (a), electrolytic copper free coating C1 and electrolytic copper plating layer C2 are put down in writing as one deck.
In (a) of Fig. 4, divide unnecessary electrolytic copper free coating C1 and electrolytic copper plating layer C2 to be cut to respectively the position of cutting face A1~A3 with predetermined thickness respectively from face side three times.In addition, in working angles for the third time, when cutting electrolytic copper free coating C1 and electrolytic copper plating layer C2 surperficial, also cut the resin insulating barrier 31 as insulating barrier, 131 surface, form matsurface on resin insulating barrier 31,131 surface.
By cutting several times, can more critically carry out cut.In addition, by being divided into repeatedly, even in the situation that electrolytic copper free coating C1 and electrolytic copper plating layer C2 are thicker also can cut.And, by form matsurface on resin insulating barrier 31,131 surface, improved this resin insulating barrier 31,131 and be layered in the resin insulating barrier 33 on resin insulating barrier 31,131,133 adaptation.In addition, because resin insulating barrier 31,131 surface are cut, therefore, can omit the operation of utilizing etching to remove to be attached to resin insulating barrier 31,131 lip-deep wiring material (copper), thus manufacturing process that can simplified wiring substrate 1.In addition, can also cut electrolytic copper free coating C1 and electrolytic copper plating layer C2 with the FS8910 of the topping machanism of selling on the market, for example DISCO company system.
Be configured as overlappingly respectively on the resin insulating barrier 31,131 that has carried out surface roughening resin insulating barrier 33,133, with the membranaceous dielectric resin material of epoxy resin as main component.Then, utilize vacuum hotpressing machine to this sandwich pressurized, heated, while make membranaceous dielectric resin material hot curing carry out crimping.Then, use in the past known laser processing device irradiating laser, form respectively wiring trench 33a, 133a and via 33b, 133b(with reference to Fig. 5 (a) in resin insulating barrier 33,133).After being formed with wiring trench 33a, 133a and via 33b, 133b, make the processing of wiring trench 33a, 133a and via 33b, 133b surface roughening.In addition, also can form wiring trench 33a, 133a and via 33b, 133b by exposure, development.
Then, with obtain wiring layer 32,132 and via conductor 35,135 o'clock same, electroless plating is carried out on interior resin insulating barrier 33,133 surface in the inside of the inside that comprises wiring trench 33a, 133a and via 33b, 133b, and then carries out the electrolysis plating.Afterwards, use diamond tool cutting electrolytic copper free coating and electrolytic copper plating layer, remove unnecessary electrolytic copper free coating and electrolytic copper plating layer, obtain wiring layer 34,134 and via conductor 36,136(with reference to (b) of Fig. 5).
In addition, in this case, also cut preferred similarly being divided into repeatedly during with cutting electrolytic copper free coating C1 and electrolytic copper plating layer C2, also preferably also cut the resin insulating barrier 33 as insulating barrier, 133 surface forms matsurface.By forming matsurface in resin insulating barrier 33,133 surface, improve this resin insulating barrier 33,133 and solder mask 4,14 adaptation.
Solder mask operation: Fig. 6
To the stacked membranaceous solder resist of difference punching press on the lamination layer 3,13 that has respectively splicing ear T1, T11 on the top layer.Make the membranaceous solder resist exposure that is layered in respectively on lamination layer 3,13, develop, obtained to be formed with the solder mask 4,14 of opening 4a, the 14a of the SMD shape that exposes be used to a part that makes each splicing ear T1, T11.Then, utilize electroless plating to be coated with nickel (Ni) and gold (Au) on the surface of splicing ear T1, T11.
Rear end operation: Fig. 7
After the surface that utilizes solder printing to be formed in solder mask 4,14 opening 4a, splicing ear T1, T11 that 14a exposes to idiomorphism has applied solder cream, reflux with predetermined temperature and time, form the solder projection 5 and the solder ball 15 that are electrically connected to splicing ear T1, T11.
As mentioned above, due to the circuit board 1 of execution mode be use the diamond tool cutting to become wiring layer 32,34,132,134 copper coating (conductor layer) forms, therefore, be not easy to be subject to the wiring layer 32,34,132,134, resin insulating barrier 31,33,131 as the cutting object, the impact of 133 shape (for example concavo-convex).Therefore, can suppress to become that the cutting of wiring layer 32,34,132,134 conductor layer is not enough, excessively cutting.
Particularly in the situation that utilize CMP to grind, when being formed on the conductor layer that has on the ditch that is of a size of the above rectangular-shaped base surface area of 7mm * 5mm on in-plane and removing, easily produce recess on the wiring layer upper surface after grinding.Its reason is, as shown in Fig. 8 (a), be formed in the most situation of conductor layer 203 that has on the ditch 202 that is of a size of the above rectangular-shaped base surface area 201 of 7mm * 5mm on in-plane and be formed with recess 204 on the surface thereon, when utilizing CMP to grind, the impact of the shape of the conductor layer 203 before being subject to grinding, therefore, can't remove this recess 204(recess 204 and self diminish, but can't remove).Therefore, as shown in Fig. 8 (b), when utilizing CMP to grind, residual recess 204 on wiring layer 205 upper surfaces of meeting after grinding.In addition, if ditch 202 has the base surface area of above-mentioned size at least, even the flat shape of ditch 202 is rectangular-shaped circle, ellipses in addition, this recess 204 also can be residual.
On the other hand, in the situation that use diamond tool to cut, as mentioned above, be difficult to be subject to the impact as the shape (for example concavo-convex) of the conductor layer 203 of cutting object as the circuit board 1 of this execution mode.Therefore, as shown in Fig. 8 (c), can obtain following wiring layer 205: have hardly recess 204 on the upper surface after cutting, even perhaps there is recess 204, this recess 204 also has the following degree of depth of 0.5 μ m.
In addition, owing to utilizing cutting to process, therefore, that sees when being difficult to produce attrition process in the metal material of conductor layer sink.And, owing to being not easy to be subject to as the cutting object, impact that become wiring layer 32,34,132,134 conductor layer, resin insulating barrier 31,33,131,133 shape, therefore, cut face become smooth (smooth).Therefore, even in the situation that stacked multi-layer resinous insulating barrier and wiring layer, it is smooth that substrate surface also becomes, and is not easy to defocus (Defocus) when exposure.
And, owing to using diamond tool as cutting tools, therefore can use for a long time this cutting tools.In addition, because the surface roughness after cutting is lower, therefore, can be suppressed at wiring layer 32,34,132,134 upper produce concavo-convex in surface.Therefore, can be reduced in the electric noise that produces on wiring layer 32,34,132,134.In addition, because the hardness of this diamond tool is higher, therefore can carries out cut at a high speed, thereby boost productivity.
In addition, when cutting becomes wiring layer 32,34,132,134 conductor layer surperficial, also cut resin insulating barrier 31,33,131,133 surface, form matsurface on resin insulating barrier 31,33,131,133.Therefore, can improve and stacked resin insulating barrier 33,133, solder mask 4,14 adaptation.In addition, because resin insulating barrier 31,33,131,133 surface are cut, therefore, needn't utilize etching to remove to be attached to resin insulating barrier 31,33,131,133 lip-deep wiring material (copper coating).Therefore, manufacturing process that can simplified wiring substrate 1.
And, cut owing to being divided into repeatedly, therefore, can carry out accurate cut.In addition, even the copper coating (conductor layer) that forms is thicker also can be cut in the situation that utilization is electroplated.And, utilizing after electroless plating formed electrolytic copper free coating, utilize film forming speed electrolysis faster plating to form electrolytic copper plating layer.Therefore, improved the productivity ratio of circuit board 1.
Embodiment
Then, embodiment is described.
In this embodiment, based on above-mentioned manufacture method, making utilizes mode that diamond tool cuts to bury underground to be formed on the sample that the copper coating in the wiring trench of resin insulating barrier forms, and utilizes SEM(scanning electron microscope) device observes the cutting face of this sample.
The making of sample
Inventor etc. on the surface of the tabular resin substrate that becomes core substrate the stacked epoxy resin that is configured to as the membranaceous dielectric resin material of main component, utilize vacuum hotpressing machine to this sandwich pressurized, heated, while make membranaceous dielectric resin material hot curing carry out crimping.Afterwards, use the laser processing device irradiating laser, form wiring trench on the dielectric resin material of hot curing, carry out electroless plating and electrolysis plating, form copper coating comprising wiring trench on the surface of interior dielectric resin material.Afterwards, cut copper coating with the FS8910 of DISCO company system, form wiring layer in wiring trench.In addition, cut with diamond tool.
The cutting face of sample
Fig. 9 is the SEM photo in cutting face.As shown in Figure 9 as can be known, in the cutting face (the copper coating X that particularly material is different and the boundary of dielectric resin material Y) do not see concavo-convexly, be good state.In addition, so-called grinding not occuring yet sink.As mentioned above as can be known, adopt the manufacture method of the circuit board 1 of execution mode, be difficult to be subject to the impact that the shape (for example concavo-convex) of the conductor layer of object, resin insulating barrier is cut in conduct, can obtain not have irregular good cutting face.
Other execution modes
Above, enumerate concrete example and describe the present invention in detail, but the present invention is not limited to foregoing, only otherwise depart from the scope of the present invention, can carry out all distortion, change.For example in the above-described embodiment, illustrated that circuit board 1 is the mode of the BGA substrate of motherboard etc. that is connected in by solder ball 15, but also circuit board 1 can be made alternative solders ball 15 and be provided with pin or pad, so-called PGA(Pin Grid Array) substrate or LGA(Land Grid Array) substrate, circuit board 1 is connected in motherboard etc.
In addition, in the above-described embodiment, the opening shape of solder mask is that SMD(solder mask that the part on the surface of splicing ear exposes, so-called is limited) shape, but can be also make the surface of splicing ear that all expose, so-called NSMD(Non Solder Mask Defined, non-solder mask limits) shape.And in the above-described embodiment, minute three cutting conductor layers are not limited to three times but cut number of times, can set best cutting number of times.
Description of reference numerals
1, circuit board; 2, core substrate; 3, lamination layer; 4, solder mask; 4a, opening; 5, solder ball; 13, lamination layer; 14, solder mask; 14a, opening; 15, solder ball; 21,22, core conductor layer; 23, through hole; 24, via conductors; 25, resin buried via hole material; 31,33, resin insulating barrier; 31a, 33a, wiring trench; 32,34, wiring layer; 35,36, via conductor; 131,133, resin insulating barrier; 131a, 133a, wiring trench; 132,134, wiring layer; 135,136, via conductor; 201, base surface area; 202, ditch; 203, conductor layer; 204, recess; 205, wiring layer; L1, L2, metal line; L11, L12, metal line; T1, T11, splicing ear.

Claims (9)

1. the manufacture method of a circuit board, this circuit board have the above insulating barrier of one deck and the above wiring layer of one deck, wherein,
The manufacture method of this circuit board has:
The 1st operation forms wiring trench in above-mentioned insulating barrier;
The 2nd operation, the mode that is embedded in above-mentioned wiring trench with at least a portion of the conductor layer that will become above-mentioned wiring layer forms this conductor layer; And
The 3rd operation is cut the surface of above-mentioned conductor layer with cutting tools, thereby forms above-mentioned wiring layer.
2. the manufacture method of circuit board according to claim 1, is characterized in that,
Above-mentioned the 3rd operation uses diamond tool as above-mentioned cutting tools.
3. the manufacture method of circuit board according to claim 1 and 2, is characterized in that,
The surface of above-mentioned the 3rd operation by cutting the surperficial of above-mentioned conductor layer and cutting above-mentioned insulating barrier, thus matsurface formed on above-mentioned insulating barrier.
4. the manufacture method of circuit board according to claim 1 and 2, is characterized in that,
Above-mentioned the 3rd operation is cut several times.
5. the manufacture method of circuit board according to claim 3, is characterized in that,
Above-mentioned the 3rd operation is cut several times.
6. the manufacture method of circuit board according to claim 1 and 2, is characterized in that,
Above-mentioned the 2nd operation has following operation:
Utilize electroless plating to form the 1st conductor layer in above-mentioned wiring trench; And
Utilize electrolysis to be plated in and form the 2nd conductor layer on above-mentioned the 1st conductor layer.
7. the manufacture method of circuit board according to claim 3, is characterized in that,
Above-mentioned the 2nd operation has following operation:
Utilize electroless plating to form the 1st conductor layer in above-mentioned wiring trench; And
Utilize electrolysis to be plated in and form the 2nd conductor layer on above-mentioned the 1st conductor layer.
8. the manufacture method of circuit board according to claim 4, is characterized in that,
Above-mentioned the 2nd operation has following operation:
Utilize electroless plating to form the 1st conductor layer in above-mentioned wiring trench; And
Utilize electrolysis to be plated in and form the 2nd conductor layer on above-mentioned the 1st conductor layer.
9. the manufacture method of circuit board according to claim 5, is characterized in that,
Above-mentioned the 2nd operation has following operation:
Utilize electroless plating to form the 1st conductor layer in above-mentioned wiring trench; And
Utilize electrolysis to be plated in and form the 2nd conductor layer on above-mentioned the 1st conductor layer.
CN2012102756620A 2011-08-03 2012-08-03 Method of fabricating circuit board Pending CN103179809A (en)

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JP2011170245 2011-08-03
JP2011-170245 2011-08-03
JP2012-123031 2012-05-30
JP2012123031A JP2013051397A (en) 2011-08-03 2012-05-30 Method for manufacturing wiring board

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