CN103178039A - Semiconductor package and manufacturing method thereof - Google Patents
Semiconductor package and manufacturing method thereof Download PDFInfo
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- CN103178039A CN103178039A CN2013100361683A CN201310036168A CN103178039A CN 103178039 A CN103178039 A CN 103178039A CN 2013100361683 A CN2013100361683 A CN 2013100361683A CN 201310036168 A CN201310036168 A CN 201310036168A CN 103178039 A CN103178039 A CN 103178039A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16104—Disposition relative to the bonding area, e.g. bond pad
- H01L2224/16105—Disposition relative to the bonding area, e.g. bond pad the bump connector connecting bonding areas being not aligned with respect to each other
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
- H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
- H01L2224/8114—Guiding structures outside the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8134—Bonding interfaces of the bump connector
- H01L2224/81345—Shape, e.g. interlocking features
Abstract
Disclosed are a semiconductor package and a manufacturing method thereof. The semiconductor package comprises a substrate, a first conducting protrusion, a crystalline grain, a conducting pad and solder. The substrate is provided with a substrate surface. The first conducting protrusion is located on the substrate and projects from the substrate surface. The first conducting protrusion is provided with a lower conducting portion and an upper conducting portion. The lower conducting portion is provided with an upper surface. The upper conducting portion projects from the upper surface of the lower conducting portion. The upper conducting portion is provided with a trapezoidal surface or slanting surface adjacently connected to the upper surface of the lower conducting portion. The crystalline grain is provided with a crystalline grain surface. The conducting pad is located on the crystalline grain. The crystalline grain surface is perpendicular to the substrate surface. The first conducting protrusion is physically and electrically connected to the conducting pad through the solder.
Description
Technical field
The invention relates to a kind of semiconductor packages and manufacture method thereof, and particularly relevant for a kind of with the crystal grain vertical type be bonded on encapsulating structure and manufacture method thereof on substrate.
Background technology
Now, the development and Design of electronic product has compact, the multi-functional and high-speed trend that focuses on.Therefore, after Electronic Packaging industry positive input and research and development, encapsulation technology and the product of various types are come out one after another.The Electronic Packaging industry except take the development requirement of supporting electronic product as mission, how constantly to improve the I/O (I/O) of various encapsulating products closeness, reduce production costs, increase production efficiency, making product have more advantage and competitiveness, is one of its target of endeavouring in fact.
Summary of the invention
According to the present invention, a kind of semiconductor packages is proposed.Semiconductor packages comprises a substrate, one first conductive bumps thing, a crystal grain, a conductive pad and a scolder.Substrate has a substrate surface.The first conductive bumps thing position is on substrate and protrude substrate surface.The first conductive bumps thing has current-carrying part on current-carrying part and.Lower current-carrying part has a upper surface.Upper current-carrying part protrudes from the upper surface of lower current-carrying part.Upper current-carrying part has the upper surface of a step surface or the lower current-carrying part of inclined surface adjacency.Crystal grain has a grain surface.The conductive pad position is on crystal grain.Grain surface is perpendicular to substrate surface.The first conductive bumps thing links and electrically connect by scolder and conductive pad physics.
According to the present invention, a kind of semiconductor packages is proposed.Semiconductor packages comprises a substrate, one first conductive bumps thing, a crystal grain, a conductive pad, one second conductive bumps thing and a scolder.Substrate has a substrate surface.The first conductive bumps thing position is on substrate and protrude substrate surface.Crystal grain has a grain surface.The conductive pad position is on crystal grain.The second conductive bumps thing position is on conductive pad and protrude from the grain surface of crystal grain.Grain surface is perpendicular to substrate surface.The first conductive bumps thing links and the electrically connect conductive pad by scolder and the second conductive bumps thing physics.
According to the present invention, a kind of semiconductor packages is proposed.Semiconductor packages comprises a substrate, one first conductive pad, a scolder, a crystal grain, one second conductive pad and a conductive layer.Substrate has a substrate surface.The first conductive pad is configured on substrate.Scolder is disposed on the first conductive pad and protrudes substrate surface.Crystal grain has a grain surface and a Cutting Road.The second conductive pad position is on crystal grain.Conductive layer penetrates crystal grain from the grain surface of Cutting Road.The second conductive pad and conductive layer are connected with each other.Grain surface is perpendicular to substrate surface.The first conductive pad is to link and electrically connect by scolder and the second conductive pad physics.
According to the present invention, a kind of manufacture method of semiconductor packages is proposed.Method comprises the following steps.One substrate is provided.Substrate has a substrate surface.Configure one first conductive bumps thing on substrate and protrude substrate surface.The first conductive bumps thing has current-carrying part on current-carrying part and.Lower current-carrying part has a upper surface.Upper current-carrying part protrudes from the upper surface of lower current-carrying part.Upper current-carrying part has the upper surface of a step surface or the lower current-carrying part of inclined surface adjacency.One crystal grain is provided.Crystal grain has a conductive pad thereon.Crystal grain has a grain surface.Configure a scolder on conductive pad.With the direction of grain surface perpendicular to substrate surface, link and electrically connect the first conductive bumps thing and conductive pad by scolder physics.
According to the present invention, a kind of manufacture method of semiconductor packages is proposed.Method comprises the following steps.One substrate is provided.Substrate has a substrate surface.Configure one first conductive bumps thing on substrate and protrude substrate surface.Configure a scolder on the first conductive bumps thing.One crystal grain is provided.Crystal grain has a conductive pad thereon.Crystal grain has a grain surface.Configure one second conductive bumps thing on conductive pad and protrude from the grain surface of crystal grain.With the direction of grain surface perpendicular to substrate surface, link and electrically connect the first conductive bumps thing and conductive pad by scolder and the second conductive bumps thing physics.
According to the present invention, a kind of manufacture method of semiconductor packages is proposed.Method comprises the following steps.One substrate is provided.Substrate has one first conductive pad thereon.Substrate has a substrate surface.Configure a scolder on the first conductive pad and protrude substrate surface.One wafer is provided.Wafer has the blind hole of a plurality of crystal grain presumptive areas and a plurality of filled conductive materials.In the Cutting Road of blind hole between the crystal grain presumptive area.Form several the second conductive pads positions on the crystal grain presumptive area and with the blind hole electrically connect.Form a plurality of crystal grain along Cutting Road and blind hole cutting crystal wafer.Blind hole after cutting is to form a plurality of conductive layers to penetrate crystal grain from a grain surface of the Cutting Road of crystal grain.With the direction of grain surface perpendicular to substrate surface, by scolder, the first conductive pad and the second conductive pad physics are linked and electrically connect.
For foregoing of the present invention can be become apparent, embodiment cited below particularly, and coordinate appended graphicly, be described in detail below:
Description of drawings
Figure 1A illustrates the profile according to the semiconductor packages of an embodiment.
Figure 1B is according to looking schematic diagram on the semiconductor packages of an embodiment.
Fig. 1 C is according to the first conductive bumps thing of an embodiment and the schematic diagram of the second conductive bumps thing.
Fig. 2 is according to the first conductive bumps thing of an embodiment and the schematic diagram of the second conductive bumps thing.
Fig. 3 A to Fig. 3 B illustrates the manufacture method according to the semiconductor packages of an embodiment.
Fig. 4 A illustrates the schematic diagram according to the semiconductor packages of an embodiment.
Fig. 4 B is according to looking schematic diagram on the semiconductor packages of an embodiment.
Fig. 4 C is the schematic diagram according to the crystal grain of an embodiment and the second conductive bumps thing.
Fig. 5 is the schematic diagram according to the crystal grain of an embodiment and the second conductive bumps thing.
Fig. 6 is the schematic diagram according to the crystal grain of an embodiment and the second conductive bumps thing.
Fig. 7 is the schematic diagram according to the crystal grain of an embodiment and the second conductive bumps thing.
Fig. 8 is the schematic diagram according to the crystal grain of an embodiment and the second conductive bumps thing.
Fig. 9 A to Fig. 9 C illustrates the manufacture method according to the semiconductor packages of an embodiment.
Figure 10 illustrates the profile according to the semiconductor packages of an embodiment.
Figure 11 illustrates the top view according to the wafer of an embodiment.
Figure 12 A illustrates the profile according to the crystal grain of an embodiment.
Figure 12 B illustrates the profile according to the crystal grain of an embodiment.
Figure 13 A illustrates the profile according to the crystal grain of an embodiment.
Figure 13 B illustrates the profile according to the crystal grain of an embodiment.
Figure 14 A illustrates the profile according to the crystal grain of an embodiment.
Figure 14 B illustrates the profile according to the crystal grain of an embodiment.
Figure 15 A illustrates the profile according to the crystal grain of an embodiment.
Figure 15 B illustrates the profile according to the crystal grain of an embodiment.
Figure 16 is the schematic diagram according to the semiconductor packages of an embodiment.
Figure 17 is the schematic diagram according to the semiconductor packages of an embodiment.
Figure 18 is the schematic diagram according to the semiconductor packages of an embodiment.
The main element symbol description:
102,302,802～substrate; 104,304,804～substrate surface; 106,206,306～the first conductive bumps things; 806～scolder; 108,308,808,1308,1362～crystal grain; 110,310,810,836,838,1310,1338,1364,1368～grain surface; 112,312,412,512,612,712～the second conductive bumps things; 114,214～lower current-carrying part; 116,216～upper current-carrying part; 118,218～upper surface; 120～inclined surface; 122～surface; 124,224～upper surface; 226～step surface; 128,328～conductive pad; 834～the first conductive pads; 730～T word shape part; 732～linear parts; 839～blind hole; 840,940,1040,1140,1360,1366～conductive layer; 842～the second conductive pads; 844～wafer; 846～crystal grain presumptive area; 848～Cutting Road; 1050,1150～rectangular portion; 1052,1152～terminal part; 1254,1256～dielectric layer; 1258～the 3rd conductive layers; 370～scolder; H
11, H
12, H
13, H
21, H
22, H
41, H
71～highly; L
71～length; W
11, W
12, W
21, W
22, W
41～width.
Embodiment
Figure 1A illustrates the profile according to the semiconductor packages of an embodiment.Substrate 102 has substrate surface 104.Substrate 102 can comprise silicon substrate, circuit board for example multilayer circuit board, flexible circuit board (Flexible Circuit Board; FCB) or other suitable substrates.The first conductive bumps thing 106 is configured on the substrate surface 104 of substrate 102 and protrudes substrate surface 104.In an embodiment, the first conductive bumps thing 106 is (but being not limited to) conductive fingers (finger).
Please refer to Figure 1A, crystal grain 108 has grain surface 110.Crystal grain 108 can comprise the crystal grain that obtains via the Cutting Road cutting from wafer.In an embodiment, conductive pad (pad) 128 is arranged on crystal grain 108.Conductive pad 128 comprises for example I/O conductive pad.For instance, grain surface 110 is the surface of conductive pad 128.The second conductive bumps thing 112 is configured on conductive pad 128 and protrudes grain surface 110.In an embodiment, the second conductive bumps thing 112 is (but being not limited to) solder projections (bump).In embodiment, the substrate surface 104 of substrate 102 is perpendicular to the grain surface 110 of crystal grain 108.In addition, conductive pad 128 is to link and electrically connect by the second conductive bumps thing 112 (for example scolder) and the first conductive bumps thing 106 (for example conductive finger) physics.
Although Figure 1A only shows single the first conductive bumps thing 106, single the second conductive bumps thing 112, single conductive pad 128, this exposure is not limited to this.In an embodiment, look schematic diagram on please refer to that Figure 1B illustrates, semiconductor packages is to have most corresponding the first conductive bumps things 106 separated from each other, most the second conductive bumps things 112 separated from each other and most conductive pads 128 separated from each other.The first conductive bumps thing 106 corresponding to each group and conductive pad 128 are via the second conductive bumps thing 112 between being arranged on physics link and electrically connect each other.In some embodiment, the first conductive bumps thing 106 is conductive fingers.The second conductive bumps thing 112 is scolders.
Fig. 1 C illustrates the first conductive bumps thing 106 of semiconductor packages of Figure 1A and the schematic diagram of the second conductive bumps thing 112, has wherein omitted substrate 102, crystal grain 108 and conductive pad 128.The first conductive bumps thing 106 has lower current-carrying part 114 and upper current-carrying part 116.Upper current-carrying part 116 protrudes from the upper surface 118 of lower current-carrying part 114.The inclined surface 120 of the upper current-carrying part 116 of the first conductive bumps thing 106 can laser engraving (laser carve) mode form.
Please refer to Fig. 1 C, according to the first conductive bumps thing 106 of some embodiment and the design of the second conductive bumps thing 112, for instance, the upper current-carrying part 116 of the first conductive bumps thing 106 has inclined surface 120 in abutting connection with the upper surface 118 of lower current-carrying part 114.The second conductive bumps thing 112 has surface 122 between the upper surface 124 of the upper surface 118 of lower current-carrying part 114 and upper current-carrying part 116, for example the surface 122 of the second conductive bumps thing 112 touches the upper surface 118 of lower current-carrying part 114, and perhaps surface 122 touches inclined surface 120.The height H of upper current-carrying part 116
12Height H to lower current-carrying part 114
11Ratio be 0.2 to 0.5.In addition, the width W of upper current-carrying part 116
11It is the width W of the first conductive bumps thing 106
1230%～40%.For instance, the height H of lower current-carrying part 114
1120 μ m.The height H of upper current-carrying part 116
125 μ m.The width W of the first conductive bumps thing 106
1250 μ m.The second conductive bumps thing 112 is from the height H of grain surface 110 (Figure 1A) protrusion of crystal grain 108
13Be 58 μ m, wherein have when spherical height H when the second conductive bumps thing 112
13Can be considered bulb diameter.according to the first conductive bumps thing 106 of embodiment and the design of the second conductive bumps thing 112, when configuring crystal grain 108 on substrate 102 time with grain surface 110 perpendicular to the direction of substrate surface 104, the first conductive bumps thing 106 more can touch the second conductive bumps thing 112, for example touch the upper surface 118 of the lower current-carrying part 114 of the inclined surface 120 of the second conductive bumps thing 112 or second surface protrusion 112, in other words, between the first conductive bumps thing 106 and the second conductive bumps thing 112, contact area and chance are larger, therefore in fuse step, the first conductive bumps thing 106 can fuse with the second conductive bumps thing 112 (scolder) efficiently, and improve the rate that engages of crystal grain 108 (conductive pad 128) and substrate 102, and raising product yield.
Fig. 2 illustrates according to the first conductive bumps thing 206 of the semiconductor packages of an embodiment and the schematic diagram of the second conductive bumps thing 112, does not wherein illustrate substrate 102, crystal grain 108 and conductive pad 128 (Figure 1A).The difference of Fig. 2 and Fig. 1 is, the upper current-carrying part 216 of the first conductive bumps thing 206 has step surface 226 in abutting connection with the upper surface 218 of lower current-carrying parts 214.In an embodiment, the first conductive bumps thing 206 can utilize lithography process to form.
Please refer to Fig. 2, according to the first conductive bumps thing 206 of some embodiment and the design of the second conductive bumps thing 112, for instance, the upper current-carrying part 216 of the first conductive bumps thing 206 has step surface 226 in abutting connection with the upper surface 218 of lower current-carrying part 214.The second conductive bumps thing 112 has surface 122 between the upper surface 224 of the upper surface 218 of lower current-carrying part 214 and upper current-carrying part 216, for example the surface 122 of the second conductive bumps thing 112 touches the upper surface 218 of lower current-carrying part 214, and perhaps surface 122 touches step surface 226.The height H of upper current-carrying part 216
22Height H to lower current-carrying part 214
21Ratio be 0.2 to 0.5.In addition, the width W of upper current-carrying part 216
21It is the width W of the first conductive bumps thing 206
2230%～40%.For instance, the height H of lower current-carrying part 214
2120 μ m.The height H of the first conductive bumps thing 206
225 μ m.The width W of the first conductive bumps thing 206
2250 μ m.The second conductive bumps thing 112 is from the height H of grain surface 110 (Figure 1A) protrusion of crystal grain 108
1358 μ m.according to the first conductive bumps thing 206 of embodiment and the design of the second conductive bumps thing 112, when configuring crystal grain 108 (Figure 1A) on substrate 102 time with grain surface 110 perpendicular to the direction of substrate surface 104, the first conductive bumps thing 206 more can touch the second conductive bumps thing 112, in other words, between the first conductive bumps thing 206 and the second conductive bumps thing 112, contact area and chance are larger, therefore in fuse step, the first conductive bumps thing 206 can fuse with the second conductive bumps thing 112 (scolder) efficiently, and improve the rate that engages of crystal grain 108 and substrate 102, and raising product yield.
Fig. 3 A to Fig. 3 B illustrates the manufacture method according to the semiconductor packages of an embodiment.
Please refer to Fig. 3 A, configuration the first conductive bumps thing 106 on the substrate surface 104 of substrate 102.The formation method of the first conductive bumps thing 106 comprises lithography process, laser engraving technique etc.The inclined surface 120 of the upper current-carrying part 116 of the first conductive bumps thing 106 is towards paper (reader).In addition, configuration the second conductive bumps thing 112 on the conductive pad 128 on crystal grain 108.Owing to being easier to fusion between tin, gold copper-base alloy, therefore in one embodiment, the first conductive bumps thing 106 can be included in plated with gold layer on the copper matrix surface, with the fusion between the second conductive bumps thing 112 that improves tin projection for example.
Please refer to Fig. 3 B, with the direction of grain surface 110 perpendicular to substrate surface 104, crystal grain 108 is configured on substrate 102, according to the first conductive bumps thing 106 of embodiment, the design of the second conductive bumps thing 112, after crystal grain 108 arranged perpendicular were on substrate 102, the first conductive bumps thing 106 was to touch the second conductive bumps thing 112.
In an embodiment, after crystal grain 108 arranged perpendicular are on substrate 102, be fusion the first conductive bumps thing 106 and the second conductive bumps thing 112, to engage crystal grain 108 and substrate 102.According to the first conductive bumps thing 106 of embodiment and the design of the second conductive bumps thing 112, the first conductive bumps thing 106 and the second conductive bumps thing 112 contacts area and chance are larger, therefore in fuse step, the first conductive bumps thing 106 can fuse with the second conductive bumps thing 112 (scolder) efficiently, and improve the rate that engages of crystal grain 108 and substrate 102 and raising product yield.The mode of fusion can comprise heat fused, hot pressing (Thermal Compression Bonding; TCB) etc.The temperature of fusion is for example 240 ℃.In an embodiment, can be at the upper scaling powder (flux) that forms of the first conductive bumps thing 106 (finger), to improve the fusion of the first conductive bumps thing 106 and the second conductive bumps thing 112 (scolder).
Fig. 4 A illustrates the schematic diagram according to the semiconductor packages of an embodiment.Substrate 302 has substrate surface 304.In an embodiment, substrate 302 can comprise silicon substrate, circuit board for example multilayer circuit board, flexible circuit board (Flexible Circuit Board; FCB) or other suitable substrates.The first conductive bumps thing 306 is configured on substrate 302 and protrudes substrate surface 304.In an embodiment, the first conductive bumps thing 306 is (but being not limited to) conductive fingers.Scolder (Solder Paste) 370 is configured on the first conductive bumps thing 306.
Please refer to Fig. 4 A, crystal grain 308 has grain surface 310.Crystal grain 108 can comprise the crystal grain that obtains via the Cutting Road cutting from wafer.In an embodiment, conductive pad 328 is arranged on crystal grain 308.Conductive pad 328 comprises for example I/O conductive pad.For instance, grain surface 310 is the surface of conductive pad 328.The second conductive bumps thing 312 is configured on conductive pad 328 and protrudes grain surface 310.In an embodiment, the second conductive bumps thing 312 is (but being not limited to) metal couplings, can comprise gold, copper, aluminium etc.In embodiment, conductive pad 328 is to link and electrically connect to the first conductive bumps thing 306 (for example conductive finger) by the second conductive bumps thing 312 (for example metal coupling) and scolder 370 physics.
Although Fig. 4 A only shows single the first conductive bumps thing 306, single the second conductive bumps thing 312, single conductive pad 328, single scolder 370, this exposure is not limited to this.In an embodiment, please refer to Fig. 4 B on look schematic diagram, semiconductor packages is to have most corresponding the first conductive bumps things 306 separated from each other, most scolders 370 separated from each other, most the second conductive bumps things 312 separated from each other, most conductive pads 328 separated from each other.The first conductive bumps thing 306 corresponding to each group and conductive pad 328 are via the scolder 370 between being arranged on and the second conductive bumps thing 312 physics link and electrically connect each other.In some embodiment, the first conductive bumps thing 306 is conductive fingers.The second conductive bumps thing 312 is metal couplings.
Fig. 4 C illustrates crystal grain 308 and the second conductive bumps thing 312 of the semiconductor packages of Fig. 4 A, wherein omits to illustrate substrate 302, the first conductive bumps thing 306 and scolder 370.In this embodiment, the second conductive bumps thing 312 be shaped as T word shape.The mode that the second conductive bumps thing 312 can routing engages (wire bonding, W/B) forms.In other embodiment, the shape of the second conductive bumps thing 312 can be spherical.
The semiconductor packages difference of the semiconductor packages of Fig. 5 and Fig. 4 C is, the second conductive bumps thing 412 be shaped as column.For instance, the height H of the second conductive bumps thing 412
41Can greater than, equal the width W of windowing of conductive pad 328
41Two minutes one times.The crystal grain 308 of this embodiment and the second conductive bumps thing 412 also can design substrate 302, the first conductive bumps thing 306 and scolder 370 in collocation Fig. 4 A.
The semiconductor packages difference of the semiconductor packages of Fig. 6 and Fig. 4 C is, the second conductive bumps thing 512 be shaped as column.The crystal grain 308 of this embodiment and the second conductive bumps thing 512 also can design substrate 302, the first conductive bumps thing 306 and the first conductive bumps thing 306 in collocation Fig. 4 A.
The semiconductor packages difference of the semiconductor packages of Fig. 7 and Fig. 4 C is, the second conductive bumps thing 612 be shaped as the arched door wire.The crystal grain 308 of this embodiment and the second conductive bumps thing 612 also can design substrate 302, the first conductive bumps thing 306 and the first conductive bumps thing 306 in collocation Fig. 4 A.
The semiconductor packages difference of the semiconductor packages of Fig. 8 and Fig. 4 C is, the second conductive bumps thing 712 comprises T word shape part 730 and linear parts 732, and wherein linear parts 732 is to extend from T word shape part 730.For instance, the development length L of linear parts 732
71Can greater than, equal the height H of T word shape part 730
71The crystal grain 308 of this embodiment and the second conductive bumps thing 712 also can design substrate 302, the first conductive bumps thing 306 and the first conductive bumps thing 306 in collocation Fig. 4 A.
Fig. 9 A to Fig. 9 C illustrates the manufacture method according to the semiconductor packages of an embodiment.
Please refer to Fig. 9 A, configuration the first conductive bumps thing 306 on the substrate surface 304 of substrate 302.Configuration scolder 370 on the first conductive bumps thing 306.In addition, configuration the second conductive bumps thing 312 on the grain surface 310 of crystal grain 308.Embodiment does not limit the second conductive bumps thing 312, can use the second conductive bumps thing 412 (Fig. 5), 512 (Fig. 6), 612 (Fig. 7), 712 (Fig. 8) of other designs yet.
Please refer to Fig. 9 B, with the direction of grain surface 310 perpendicular to substrate surface 304, crystal grain 308 is configured on substrate 302.According to the design of scolder 370, the first conductive bumps thing 306 and the second conductive bumps thing 312 of embodiment, after crystal grain 308 arranged perpendicular were on substrate 302, the second conductive bumps thing 312 was the scolders 370 that touch on the first conductive bumps thing 306.
Please refer to Fig. 9 C, utilize for example brazier technique, fuse the scolder 370 between the first conductive bumps thing 306 and the second conductive bumps thing 312, engaging the first conductive bumps thing 306 on the second conductive bumps thing 312 and the substrate 302 on crystal grain 308, and the formation signal is connected between crystal grain 308 and substrate 302.Design according to scolder 370 and the second conductive bumps thing 312 of embodiment, scolder 370 and the second conductive bumps thing 312 contacts area and chance are larger, therefore in fuse step, scolder 370 can fuse with the second conductive bumps thing 312 efficiently, and improve the rate that engages of crystal grain 308 and substrate 302 and raising product yield.
Figure 10 illustrates the profile according to the semiconductor packages of an embodiment.Substrate 802 has substrate surface 804.Substrate 802 can comprise silicon substrate, circuit board for example multilayer circuit board, flexible circuit board (Flexible Circuit Board; FCB) or other suitable substrates.The first conductive pad 834 is configured on substrate 802.Scolder 806 is configured on the first conductive pad 834 and protrudes substrate surface 804.Scolder 806 can be electrically connected to the first conductive pad 834.
In an embodiment, with the direction of grain surface 810 perpendicular to substrate surface 804, crystal grain 808 is configured on substrate 802, so that conductive layer 840 (and second conductive pad 842) touches scolder 806, make the first conductive pad 834 to link and electrically connect by scolder 806 and conductive layer 840 (and second conductive pad 842) physics.Wherein grain surface 836 is towards substrate 802, and grain surface 838 substrate dorsad, and the second conductive pad 842 can be by for example mode and conductive layer 840 electrically connects of re-distribution layer (RDL), so the design of the second conductive pad 842 elasticity more.
Please refer to Figure 11, crystal grain 808 can comprise the crystal grain 808 that obtains via cutting from wafer 844.Wafer 844 has the blind hole 839 of a plurality of crystal grain presumptive areas 846 and a plurality of filled conductive materials.In the Cutting Road of blind hole 839 between crystal grain presumptive area 846 848.For instance, blind hole 839 can utilize the gold-tinted lithography process to form the photoresistance (not shown) of patterning on wafer 844, then utilize the photoresistance of patterning as shade, go out hole from the surface of wafer 844 toward etched inside, then utilize the mode filled conductive material for example electroplated in hole and form.The second conductive pad 842 be formed on crystal grain presumptive area 846 and with blind hole 839 electrically connects.In an embodiment, be to form crystal grain 808 with blind hole 839 cutting crystal wafers 844 along Cutting Road 848, the blind hole 839 after cutting is to form conductive layer 840 (Figure 10) to penetrate crystal grain 808 from the grain surface 810 of the Cutting Road 848 of crystal grain 808.
In an embodiment, crystal grain 808 can be as shown in Figure 12 A along the profile of AB line in Cutting Road 848, can be as shown in Figure 12 B along the profile of CD line.For instance, do not cut crystal grain 808 front blind holes 839 and have the shape of circular cone, therefore, after cutting crystal grain 808, please refer to Figure 12 A, from the direction towards grain surface 836, the section of conductive layer 840 has triangle, the conductive layer 840 of Figure 12 B demonstration also has the section of triangle in addition, and the second conductive pad 842 is couple conductive layer 840 and extend on the grain surface 810 of crystal grain presumptive area 846.。
In an embodiment, crystal grain 808 can be as shown in FIG. 13A along the profile of AB line, can be as shown in Figure 13 B along the profile of CD line.The semiconductor packages difference that the semiconductor packages that Figure 13 A, Figure 13 B illustrate and Figure 12 A, Figure 12 B illustrate is, the section of conductive layer 940 is rectangle.
In an embodiment, crystal grain 808 can be as shown in Figure 14 A along the profile of AB line, can be as shown in Figure 14B along the profile of CD line.The semiconductor packages difference that the semiconductor packages that Figure 14 A, Figure 14 B illustrate and Figure 12 A, Figure 12 B illustrate is, the rectangular portion 1050 that conductive layer 1040 has an adjacency and triangle shaped tip section 1052.
In an embodiment, crystal grain 808 can be as shown in Figure 15 A along the profile of AB line, can be as shown in Figure 15 B along the profile of CD line.The semiconductor packages difference that the semiconductor packages that Figure 15 A, Figure 15 B illustrate and Figure 12 A, Figure 12 B illustrate is, conductive layer 1140 has the rectangular portion 1150 and curved surface terminal part 1152 of adjacency.
Figure 16 is the schematic diagram according to the semiconductor packages of an embodiment.Conductive layer 840 can penetrate crystal grain 808 from grain surface 810.
The direction of the grain surface 810 of past crystal grain 808, the second conductive pad 842 is to couple conductive layer 840.For instance, the second conductive pad 842 can be formed in dielectric layer 1254, and extends toward the direction of crystal grain presumptive area 846 (Figure 11).For instance, but form the dielectric material (not shown) on grain surface 810, then form the photoresistance (not shown) of patterning on dielectric material, utilize the photoresistance of patterning as shade, come dielectric material that etching removes part to form dielectric layer 1254, then in the hole of dielectric layer 1254 definition the filled conductive material to form the second conductive pad 842.
The second conductive pad 842 is to couple the 3rd conductive layer 1258 that is formed in dielectric layer 1256.For instance, the 3rd conductive layer 1258 can be formed in crystal grain presumptive area 846 (Figure 11).For instance, but form the dielectric material (not shown) on dielectric layer 1254 and the second conductive pad 842, then form the photoresistance (not shown) of patterning on dielectric material, utilize the photoresistance of patterning as shade, come dielectric material that etching removes part to form dielectric layer 1256, then in the hole of dielectric layer 1256 definition the filled conductive material to form the 3rd conductive layer 1258.
Figure 17 is the schematic diagram according to the semiconductor packages of an embodiment.The conductive layer 1360 that crystal grain 1308 can expose by the grain surface 1338 of substrate (not shown) dorsad is coupled to the conductive layer 1366 that the grain surface 1364 of another crystal grain 1362 exposes.In this embodiment, on crystal grain 1308, single conductive layer 1360 can be coupled to single conductive layer 1366 on crystal grain 1362.Perhaps, on crystal grain 1308, two conductive layers 1360 can be coupled to single conductive layer 1366 on crystal grain 1362 jointly.In an embodiment, for instance, crystal grain 1308 can vertical direction stack with crystal grain 1362, that is grain surface 1368 is the tops that are positioned at grain surface 1310, and grain surface 1368 is to be parallel to grain surface 1310.
The semiconductor packages difference that the semiconductor packages that Figure 18 illustrates and Figure 17 illustrate is, on crystal grain 1308, single conductive layer 1360 can be coupled to single conductive layer 1366 on crystal grain 1362.Perhaps, on crystal grain 1362, two conductive layers 1366 can be coupled to single conductive layer 1360 on crystal grain 1308 jointly.
Though abovely be configured in single the embodiment on substrate with single crystal grain and explain, so this exposure is not limited to this, in other embodiment, can on single substrate most upright crystal grain of configuration, the grain surface of crystal grain can be parallel to each other.
In sum, although the present invention discloses as above with embodiment, so it is not to limit the present invention.The persond having ordinary knowledge in the technical field of the present invention, without departing from the spirit and scope of the present invention, when being used for a variety of modifications and variations.Therefore, protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (10)
1. semiconductor packages comprises:
One substrate has a substrate surface;
One first conductive bumps thing, the position is on this substrate and protrude this substrate surface, and wherein this first conductive bumps thing has:
Once current-carrying part, have a upper surface; And
Current-carrying part on one protrudes from this upper surface of this time current-carrying part, wherein should have a step surface or inclined surface by upper current-carrying part, and this step surface or inclined surface are this upper surfaces in abutting connection with this time current-carrying part;
One crystal grain has a grain surface;
One conductive pad, the position is on this crystal grain; And
One scolder, wherein this grain surface is perpendicular to this substrate surface, and this first conductive bumps thing links and electrically connect by this scolder and this conductive pad physics.
2. semiconductor packages as claimed in claim 1, wherein this first conductive bumps thing comprises a plurality of conductive fingers, this conductive pad has a plurality of conductive pads, this scolder links between this conductive finger and this conductive pad, and this scolder is in separated from one another between this conductive finger and this scolder is separated from one another between this conductive pad.
3. semiconductor packages as claimed in claim 1, height that wherein should upper current-carrying part is 0.2 to 0.5 to the ratio of the height of this time current-carrying part.
4. semiconductor packages comprises:
One substrate has a substrate surface;
One first conductive bumps thing, the position is on this substrate and protrude this substrate surface;
One crystal grain has a grain surface;
One conductive pad, the position is on this crystal grain;
One second conductive bumps thing, position are on this conductive pad and protrude from this grain surface of this crystal grain; And
One scolder, wherein this grain surface is perpendicular to this substrate surface, and this first conductive bumps thing links and this conductive pad of electrically connect by this scolder and this second conductive bumps thing physics.
5. semiconductor packages as claimed in claim 4, wherein this first conductive bumps thing comprises a plurality of conductive fingers, it is surperficial that this conductive finger has a conductive finger, this conductive pad has a surface, this surface that this grain surface is this conductive pad, this the second conductive bumps thing comprises metal coupling, and this conductive pad is by this second conductive bumps thing and this scolder and the link of this conductive finger physics and electrically connect.
6. semiconductor packages as claimed in claim 4, wherein the shape of this second conductive bumps thing comprises spherical, column, wire, T word shape.
7. semiconductor packages comprises:
One substrate has a substrate surface;
One first conductive pad is configured on this substrate;
One scolder is disposed on this first conductive pad and protrudes this substrate surface,
One crystal grain has a grain surface and a Cutting Road;
One second conductive pad, the position is on this crystal grain; And
One conductive layer, penetrate this crystal grain from this grain surface of this Cutting Road, wherein this second conductive pad and this conductive layer are connected with each other, and this grain surface is perpendicular to this substrate surface, and this first conductive pad is to link and electrically connect by this scolder and this second conductive pad physics.
8. the manufacture method of a semiconductor packages comprises:
One substrate is provided, and this substrate has a substrate surface;
Configure one first conductive bumps thing on this substrate and protrude this substrate surface, wherein this first conductive bumps thing has:
Once current-carrying part, have a upper surface; And
Current-carrying part on one protrudes from this upper surface of this time current-carrying part, wherein should have a step surface or inclined surface by upper current-carrying part, and this step surface or inclined surface are this upper surfaces in abutting connection with this time current-carrying part;
One crystal grain is provided, and this crystal grain has a conductive pad thereon, and this crystal grain has a grain surface;
Configure a scolder on this conductive pad; And
With the direction of this grain surface perpendicular to this substrate surface, link and this first conductive bumps thing of electrically connect and this conductive pad by this scolder physics.
9. the manufacture method of a semiconductor packages comprises:
One substrate is provided, and this substrate has a substrate surface;
Configure one first conductive bumps thing on this substrate and protrude this substrate surface;
Configure a scolder on this first conductive bumps thing;
One crystal grain is provided, and this crystal grain has a conductive pad thereon, and this crystal grain has a grain surface;
Configure one second conductive bumps thing on this conductive pad and protrude from this grain surface of this crystal grain; And
With the direction of this grain surface perpendicular to this substrate surface, link and this first conductive bumps thing of electrically connect and this conductive pad by this scolder and this second conductive bumps thing physics.
10. the manufacture method of a semiconductor packages comprises:
One substrate is provided, and this substrate has one first conductive pad thereon, and this substrate has a substrate surface;
Configure a scolder on this first conductive pad and protrude this substrate surface;
One wafer is provided, and this wafer has the blind hole of a plurality of crystal grain presumptive areas and a plurality of filled conductive materials, wherein in the Cutting Road of those blind holes between those crystal grain presumptive areas;
Form several the second conductive pads, the position on this crystal grain presumptive area and with those blind hole electrically connects;
Cut this wafer along this Cutting Road and those blind holes and form a plurality of crystal grain, those blind holes after cutting are to form a plurality of conductive layers to penetrate this crystal grain from a grain surface of this Cutting Road of this crystal grain; And
With the direction of this grain surface perpendicular to this substrate surface, by this scolder, this first conductive pad and this second conductive pad physics are linked and electrically connect.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013100361683A CN103178039A (en) | 2013-01-30 | 2013-01-30 | Semiconductor package and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2013100361683A CN103178039A (en) | 2013-01-30 | 2013-01-30 | Semiconductor package and manufacturing method thereof |
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| US5963793A (en) * | 1996-05-29 | 1999-10-05 | Mcnc | Microelectronic packaging using arched solder columns |
| US20020063319A1 (en) * | 2000-11-30 | 2002-05-30 | Siliconware Precision Industries Co.,Ltd. | Direct-downset flip-chip package assembly and method of fabricating the same |
| CN1411010A (en) * | 2001-10-05 | 2003-04-16 | 株式会社村田制作所 | Method for mfg. laminated ceramic electronic device, assembly electronic device and laminated ceramic electronic device |
| CN1841689A (en) * | 2005-03-28 | 2006-10-04 | 富士通株式会社 | Semiconductor device and semiconductor-device manufacturing method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5963793A (en) * | 1996-05-29 | 1999-10-05 | Mcnc | Microelectronic packaging using arched solder columns |
| US20020063319A1 (en) * | 2000-11-30 | 2002-05-30 | Siliconware Precision Industries Co.,Ltd. | Direct-downset flip-chip package assembly and method of fabricating the same |
| CN1411010A (en) * | 2001-10-05 | 2003-04-16 | 株式会社村田制作所 | Method for mfg. laminated ceramic electronic device, assembly electronic device and laminated ceramic electronic device |
| CN1841689A (en) * | 2005-03-28 | 2006-10-04 | 富士通株式会社 | Semiconductor device and semiconductor-device manufacturing method |
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Application publication date: 20130626 |