CN103151332B - A kind of ONO antifuse unit structure and preparation method thereof - Google Patents
A kind of ONO antifuse unit structure and preparation method thereof Download PDFInfo
- Publication number
- CN103151332B CN103151332B CN201310097579.3A CN201310097579A CN103151332B CN 103151332 B CN103151332 B CN 103151332B CN 201310097579 A CN201310097579 A CN 201310097579A CN 103151332 B CN103151332 B CN 103151332B
- Authority
- CN
- China
- Prior art keywords
- layer
- masking layer
- antifuse
- substrate
- silicon nitride
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The present invention relates to a kind of ONO antifuse unit structure and preparation method thereof, belong to microelectronic technical field.According to technical scheme provided by the invention, described ONO antifuse unit structure, comprises lower electrode plate, and described lower electrode plate comprises substrate, and the top of described substrate is provided with an oxygen and N+ diffusion region; Arrange the antifuse hole of through injection masking layer and corrosion masking layer directly over described N+ diffusion region, on the N+ diffusion region that described injection masking layer covers substrate top and field oxygen, corrosion masking layer is covered in and injects on masking layer; Described corrosion masking layer arranges ono dielectric layer, and described ono dielectric layer covers on corrosion masking layer, and is filled in antifuse hole, and the N+ diffusion region contacts bottom ono dielectric layer and antifuse hole, ono dielectric layer is coated with electric pole plate.Present invention process step is simple, can improve the uniformity of fuse cell puncture voltage, and reduce programming time and the rear fuse on-resistance of programming, processing compatibility is good, safe and reliable.
Description
Technical field
The present invention relates to a kind of antifuse unit structure and preparation method, especially a kind of ONO antifuse unit structure and preparation method thereof, belongs to microelectronic technical field.
Background technology
Antifuse memory cell is natural radioresistance assembly, have non-volatile, high reliability, volume are little, speed is fast, the advantage such as low in energy consumption, at present, antifuse technology has had in fields such as computer, communication, automobile, satellite and Aero-Space and has applied extremely widely.Antifuse unit structure is sandwich structure, forms, its dielectric layer wide variety: SiO primarily of upper/lower electrode and the antifuse dielectric layer be between upper/lower electrode
2(as patent US.pat.NO.4543594), Si
3n
4(as patent US.pat.NO.3423646), amorphous silicon (as patent US.pat.NO.4499557), SiO
2/ Si
3n
4/ SiO
2-ONO composite films (as patent US.pat.NO.4943538) etc., select corresponding dielectric layer according to different demands.When not programming, anti-fuse cell performance high-impedance state, can up to 10
10ohm, add suitable voltage programming between upper/lower electrode after, antifuse shows good Ohmic resistance characteristic.
Affect ONO antifuse memory cell reliability of structure factor a lot, as bottom oxide layer (tunnel oxidation layer), Si
3n
4, the coating growth technique such as top layer oxide layer, the techniques such as antifuse pitting corrosion.Patent US.pat.NO.6307248 adopts plain layer polysilicon film as the masking layer of antifuse hole window, than traditional Si
3n
4more easily control the sidewall profile in antifuse hole with photoresist, reduce the impact of pitting corrosion technique on antifuse memory cell reliability.
Summary of the invention
The object of the invention is to overcome the deficiencies in the prior art, provide a kind of ONO antifuse unit structure and preparation method thereof, its processing step is simple, the uniformity of fuse cell puncture voltage can be improved, reduce programming time and the rear fuse on-resistance of programming, processing compatibility is good, safe and reliable.
According to technical scheme provided by the invention, described ONO antifuse unit structure, comprises lower electrode plate, and described lower electrode plate comprises substrate, and the top of described substrate is provided with an oxygen and N+ diffusion region; Arrange the antifuse hole of through injection masking layer and corrosion masking layer directly over described N+ diffusion region, on the N+ diffusion region that described injection masking layer covers substrate top and field oxygen, corrosion masking layer is covered in and injects on masking layer; Described corrosion masking layer arranges ono dielectric layer, and described ono dielectric layer covers on corrosion masking layer, and is filled in antifuse hole, and the N+ diffusion region contacts bottom ono dielectric layer and antifuse hole, ono dielectric layer is coated with electric pole plate.
Described corrosion masking layer is amorphous silicon layer, and injection masking layer is silicon dioxide layer.
A preparation method for ONO antifuse unit structure, the preparation method of described antifuse unit structure comprises the steps:
A, provide substrate, and field oxygen needed for making over the substrate and active area;
B, on above-mentioned substrate thermal oxide growth inject masking layer;
C, utilization are injected masking layer and on substrate, are injected N-type ion, to obtain N+ diffusion region on substrate;
D, injection masking layer on deposit corrosion masking layer, and etching corrosion masking layer and inject masking layer obtain antifuse hole, the through corrosion masking layer in described antifuse hole and inject masking layer, at the bottom of the hole in antifuse hole with N+ diffusion region contacts;
E, tunnel oxidation cleaning is carried out to above-mentioned substrate;
F, utilize low-pressure oxidized technique to grow tunnel oxidation layer, described tunnel oxidation layer covers on corrosion masking layer, and covers sidewall and the diapire in antifuse hole;
G, on above-mentioned tunnel oxidation layer, adopt the silicon nitride film of LPCVD deposit richness-N;
H, high-temperature oxydation is carried out to above-mentioned silicon nitride film layer, obtain top layer oxide layer;
I, in top layer oxide layer deposit top electrode.
Described step a comprises the steps:
A1, at Grown
the first silicon dioxide layer;
A2, on above-mentioned first silicon dioxide layer deposit silicon nitride layer, the thickness of described silicon nitride layer is
The first silicon dioxide layer on a3, the above-mentioned substrate of photoetching and silicon nitride layer, to make required active area;
A4, utilize above-mentioned silicon nitride layer for masking layer, thermal oxidation is produced
the second silicon dioxide layer, to obtain the field oxygen be positioned on substrate;
A5, remove the first silicon dioxide layer inside the oxygen of above-mentioned field and silicon nitride layer.
In described step c, during described injection N-type ion, first inject P ion, reinject As ion, and wherein, P/As implantation dosage is: 1.0E15 ~ 7.0E15/cm
2, P/As Implantation Energy is: 50 ~ 80kev, and annealing process temperature is 900 ~ 1050 DEG C, degeneration atmosphere N
2.
In described steps d, corrosion masking layer is amorphous silicon layer, and the thickness of corrosion masking layer is
the temperature of deposit corrosion masking layer is 490 ~ 580 DEG C, and pressure is 250 ~ 450mtorr.
In described step f, the pressure 50 ~ 100torr of described growth tunnel oxidation layer (16), O
2flow control is at 8 ~ 15SLM, and temperature is 680 ~ 820 DEG C, and directly over N+ diffusion region (13), the thickness of tunnel oxidation layer (16) is
In described step g, the pressure of LPCVD deposition silicon nitride film is 250 ~ 450mtorr, DCS:NH
3=1:5 ~ 1:10, technological temperature is 680 ~ 780 DEG C, Si
3n
4thicknesses of layers is
In described step h, wet-oxygen oxidation growth is adopted to obtain
top layer oxide layer, temperature is 900 ~ 1050 DEG C; And adopt N
2o anneals, N
2o annealing process pressure 50 ~ 100torr, technological temperature 800 ~ 900 DEG C.
The thickness of described electric pole plate is 3000 ~ 5000A polysilicon layer, and passes through POCL
3doping, makes the sheet resistance of electric pole plate be 20 ~ 27 Ω/.
Advantage of the present invention: adopt uniformity in the thickness stability of low-pressure oxidized technology controlling and process tunnel oxidation layer and disk, adopts the injection sequencing of fixing P/As ion, controls the technology stability of the tunnel oxidation layer in the growth of bottom crown N+ diffusion region.Adopt and regulate DCS and NH
3ratio, make the silicon nitride film in ONO have richness-N, reduce programming time, improve the uniformity of fuse cell puncture voltage in silica-based disk.Amorphous silicon layer as the corrosion masking layer in antifuse hole, to control the sidewall profile in antifuse hole better.Adopt low pressure N
2o anneals, and reduces the defect because of dangling bonds generation in top layer oxide layer, improves fuse cell puncture voltage uniformity.
The present invention utilizes N under the high temperature conditions
2n with dangling bonds can be shifted out top oxide layer by the oxygen atom that O decomposes, and contributes to the compactness strengthening top layer oxide layer like this.Adopt the device making technics flow process that industry is conventional, compatible with MOS technological process, technique is simple, controlled.Compare with the ONO anti-fuse structures of routine, have that fuse cell puncture voltage uniformity is good, fuse on-resistance is low after programming time and programming advantage.
Accompanying drawing explanation
Fig. 1 ~ Fig. 3 is the present invention's concrete implementing process step cutaway view, wherein
Fig. 1 is the cutaway view after the present invention obtains antifuse hole.
Fig. 2 is the cutaway view after the present invention obtains top layer oxide layer.
Fig. 3 is the cutaway view after the present invention obtains electric pole plate.
Description of reference numerals: 11-substrate, 12-field oxygen, 13-N+ diffusion region, 14-inject masking layer, 15-corrosion masking layer, 16-tunnel oxidation layer, 17-silicon nitride film, 18-top layer oxide layer, 19-electric pole plate and 20-antifuse hole.
Embodiment
Below in conjunction with concrete drawings and Examples, the invention will be further described.
As shown in Figure 3: in order to puncture voltage uniformity, the reduction programming time of anti-fuse cell and rear fuse on-resistance of programming can be optimized, the present invention includes lower electrode plate, described lower electrode plate comprises substrate 11, and the top of described substrate 11 is provided with an oxygen 12 and N+ diffusion region 13; Arrange the antifuse hole 20 of through injection masking layer 14 and corrosion masking layer 15 directly over described N+ diffusion region 13, on the N+ diffusion region 13 that described injection masking layer 14 covers substrate 11 top and field oxygen 12, corrosion masking layer 15 is covered in and injects on masking layer 14; Described corrosion masking layer 15 arranges ono dielectric layer, and described ono dielectric layer covers on corrosion masking layer 15, and is filled in antifuse hole 20, and ono dielectric layer contacts with the N+ diffusion region 13 bottom antifuse hole 20, ono dielectric layer is coated with electric pole plate 19.
Particularly, described ono dielectric layer comprises the tunnel oxidation layer 16 of bottom, the top layer oxide layer 18 being covered in the silicon nitride film 17 on described tunnel oxidation layer 16 and being covered on described silicon nitride film 17, injecting masking layer 14 is silicon dioxide layer, and corrosion masking layer 15 is amorphous silicon layer.
As shown in FIG. 1 to 3: the ONO antifuse unit structure of said structure, can be prepared by following processing step, described preparation technology comprises following concrete steps:
A, provide substrate 11, and field oxygen 12 needed for making on described substrate 11 and active area;
Wherein, described step a comprises the steps:
A1, to grow on the substrate 11
the first silicon dioxide layer; Described substrate 11 is silicon substrate, and the crystalline phase of substrate 11 is <100>;
A2, on above-mentioned first silicon dioxide layer deposit silicon nitride layer, the thickness of described silicon nitride layer is
in the embodiment of the present invention, the first silicon dioxide layer and silicon nitride layer are all prepared by conventional technique and obtain.
The first silicon dioxide layer on a3, the above-mentioned substrate 11 of photoetching and silicon nitride layer, to make required active area;
A4, utilize above-mentioned silicon nitride layer for masking layer, thermal oxidation is produced
the second silicon dioxide layer, to obtain the field oxygen 12 be positioned on substrate 11; Being isolated by the active area on field oxygen 12 pairs of substrates 11, is the routine techniques means of the art.
A5, remove the first silicon dioxide layer inside above-mentioned field oxygen 12 and silicon nitride layer.Namely the first silicon dioxide layer on active area and silicon nitride layer is removed, to carry out follow-up operation to active area.
B, on above-mentioned substrate 11 thermal oxide growth inject masking layer 14;
In the embodiment of the present invention, described injection masking layer 14 is silicon dioxide layer, and the thickness injecting masking layer 14 is
injecting masking layer 14 covers on oxygen 12 on the scene and active area;
C, utilization are injected masking layer 14 and are injected N-type ion on the substrate 11, to obtain N+ diffusion region 13 on the substrate 11;
In the embodiment of the present invention, when injecting N-type ion, needing on injection masking layer 14, to apply photoresist, then corresponding region on photoetching active area, carrying out required ion implantation, injecting masking layer 14 and photoresist sheltering as ion implantation; During described injection N-type ion, first inject P ion, reinject As ion, and wherein, P/As implantation dosage is: 1.0E15 ~ 7.0E15/cm
2, P/As Implantation Energy is: 50 ~ 80kev, and annealing process temperature is 900 ~ 1050 DEG C, degeneration atmosphere N
2, annealing time is 30 ~ 60 minutes, activates implanted dopant, forms N+ diffusion region 13.In the embodiment of the present invention, in substrate 11, form the impedance that N+ diffusion region 13 can reduce lower electrode plate.
D, injection masking layer 14 on deposit corrosion masking layer 15, and etching corrosion masking layer 15 and injection masking layer 14 obtain antifuse hole 20, the through corrosion masking layer 15 in described antifuse hole 20 and injection masking layer 14, the Di YuN+ diffusion region, hole 13 in antifuse hole 20 contacts;
In the embodiment of the present invention, corrosion masking layer 15 is amorphous silicon layer, and the thickness of corrosion masking layer 15 is
the temperature of deposit corrosion masking layer 15 is 490 ~ 580 DEG C, and pressure is 250 ~ 450mtorr(millitorr).When etching antifuse hole 20, need to apply photoresist on corrosion masking layer 15, then photoetching photoresist, etching window is obtained needing the position forming antifuse hole 20, utilize etching window corrosion masking layer 15 and injection masking layer 14 can be etched, obtain antifuse hole 20, after obtaining antifuse hole 20, remove above-mentioned photoresist.In the embodiment of the present invention, using the masking layer technique that amorphous silicon layer corrodes as antifuse hole 20, the sidewall profile more contributing to antifuse hole 20 compared with conventional lithography glue controls.Obtain the structure behind antifuse hole 20 as shown in Figure 1.
E, tunnel oxidation cleaning is carried out to above-mentioned substrate 11;
In the embodiment of the present invention, needed to clean, wherein before preparing ono dielectric layer, first SPM and APM cleaning will be carried out, then adopt concentration be 0.5% ~ 2% the drift of HF solution remove at the bottom of hole, antifuse hole 20 natural oxidizing layer, therefore, described step e comprises the steps:
E1, utilize the SPM(Surfuric/PeroxideMix of 90 ~ 140 DEG C) solution cleaning 3 ~ 10 minutes, wherein, SPM solution is H
2sO
4with H
2o
2mixed liquor, H
2sO4 and H
2o2 volume ratio is 3:1 ~ 4:1, H
2sO4 concentration is 96% ~ 98%, H
2o
2concentration is 30% ~ 32%;
E2, recycling 40 ~ 80 DEG C of APM(Ammonia/PeroxideMix) cleaning 5 ~ 15 minutes in cleaning fluid, wherein, APM solution is NH
4oH, H
2o
2and H
2o mixed liquor, NH
4oH, H
2o
2and H
2the volume ratio of O is NH
4oH:H
2o
2: H
2o=1:20:70 ~ 1:2:7, H
2sO4 concentration is 96% ~ 98%, H
2o2 concentration is 30% ~ 32%, NH
4oH concentration is 30% ~ 33%;
E3, concentration is utilized to be the natural oxidizing layer that the drift of 0.5% ~ 2%HF solution is gone at the bottom of hole, antifuse hole 20.
F, utilize low-pressure oxidized technique to grow tunnel oxidation layer 16, described tunnel oxidation layer 16 covers on corrosion masking layer 15, and covers sidewall and the diapire in antifuse hole 20;
After completing the cleaning of above-mentioned tunnel oxidation, tunnel oxidation technique need be done immediately, if when employing atmospheric processes grows the tunnel oxidation layer 16 at the bottom of hole, because process rate is fast, easily cause technology controlling and process unstable; Therefore, in the embodiment of the present invention, adopt low-pressure oxidized technique to make tunnel oxidation layer 16, can contribute to reducing oxidation rate, and oxide layer is finer and close, meanwhile, the uniformity in more easy to control, between sheet, between stove.In the embodiment of the present invention, the pressure 50 ~ 100torr of described growth tunnel oxidation layer 16, O
2flow control is at 8 ~ 15SLM(StandardLitersperMinute), temperature is 680 ~ 820 DEG C, and directly over N+ diffusion region 13, the thickness of tunnel oxidation layer 16 is
G, on above-mentioned tunnel oxidation layer 16, adopt the silicon nitride film 17 of LPCVD deposit richness-N;
After completing the technique of tunnel oxidation layer 16, need on tunnel oxidation layer 16, adopt LPCVD(low-pressure chemical vapor deposition immediately) silicon nitride film 17 of deposit one deck richness-N, the pressure of technique is 250 ~ 450mtorr, DCS:NH
3=1:5 ~ 1:10, technological temperature is 680 ~ 780 DEG C, Si
3n
4thicknesses of layers is
H, high-temperature oxydation is carried out to above-mentioned silicon nitride film layer 17, obtain top layer oxide layer 18;
Adopt high temperature thermal oxidation metallization processes to carry out thermal oxidation to above-mentioned silicon nitride film 17, form top oxide layer 18, the mode of oxidation adopts wet-oxygen oxidation (H
2/ O
2), formed
top layer thermal oxide layer 18, technological temperature is 900 ~ 1050 DEG C; Because top oxidation is that therefore top layer oxide layer 18 easily produces defect in oxidizing process, therefore, present invention employs low pressure N with silicon nitride film 17 for base heat growth top layer oxide layer 18
2o annealing way is repaired or is reduced the defect in the oxide layer of top, its N
2o annealing process pressure 50 ~ 100torr, technological temperature 800 ~ 900 DEG C, as shown in Figure 2.
I, in top layer oxide layer 18 deposit electric pole plate 19.
The thickness of described electric pole plate 19 is
polysilicon layer, and pass through POCL
3doping, makes the sheet resistance of electric pole plate 19 be 20 ~ 27 Ω/ (square resistances), as shown in Figure 3.
The present invention adopts uniformity in the thickness stability of low-pressure oxidized technology controlling and process tunnel oxidation layer 16 and disk, adopts the injection sequencing of fixing P/As ion, controls the technology stability of the tunnel oxidation layer 16 in the growth of bottom crown N+ diffusion region 13.Adopt and regulate DCS and NH
3ratio, make the silicon nitride film 17 in ONO have richness-N, reduce programming time, improve the uniformity of fuse cell puncture voltage in silica-based disk.Amorphous silicon layer as the corrosion masking layer 15 in antifuse hole 20, to control the sidewall profile in antifuse hole better.Adopt low pressure N
2o anneals, and reduces the defect because of dangling bonds generation in top layer oxide layer 18, improves fuse cell puncture voltage uniformity.
The present invention utilizes N under the high temperature conditions
2n with dangling bonds can be shifted out top oxide layer by the oxygen atom that O decomposes, and contributes to the compactness strengthening top layer oxide layer 18 like this.Adopt the device making technics flow process that industry is conventional, compatible with MOS technological process, technique is simple, controlled.Compare with the ONO anti-fuse structures of routine, have that fuse cell puncture voltage uniformity is good, fuse on-resistance is low after programming time and programming advantage.
Claims (2)
1. a preparation method for ONO antifuse unit structure, is characterized in that, the preparation method of described antifuse unit structure comprises the steps:
(a), substrate (11) is provided, and described substrate (11) is upper make needed for field oxygen (12) and active area;
(b), inject masking layer (14) at the upper thermal oxide growth of above-mentioned substrate (11);
C (), utilization inject masking layer (14) at substrate (11) upper injection N-type ion, to obtain N+ diffusion region (13) on substrate (11);
(d), deposit corrosion masking layer (15) in injection masking layer (14), and etching corrosion masking layer (15) and injection masking layer (14) obtain antifuse hole (20), the through corrosion masking layer (15) of described antifuse hole (20) and injection masking layer (14), Di YuN+ diffusion region, hole (13) contact of antifuse hole (20);
(e), tunnel oxidation cleaning is carried out to above-mentioned substrate (11);
(f), utilize low-pressure oxidized technique to grow tunnel oxidation layer (16), described tunnel oxidation layer (16) covers in corrosion masking layer (15), and covers sidewall and the diapire in antifuse hole (20);
(g), at the upper silicon nitride film (17) adopting LPCVD deposit richness-N of above-mentioned tunnel oxidation layer (16);
(h), high-temperature oxydation is carried out to above-mentioned silicon nitride film layer (17), obtain top layer oxide layer (18);
(i), at the upper deposit electric pole plate (19) of top layer oxide layer (18);
Described step (a) comprises the steps:
(a1), at the first silicon dioxide layer of the upper growth 250 ~ 600 of substrate (11);
(a2), on above-mentioned first silicon dioxide layer deposit silicon nitride layer, the thickness of described silicon nitride layer is 1000 ~ 1500;
(a3) the first silicon dioxide layer, on the above-mentioned substrate of photoetching (11) and silicon nitride layer, to make required active area;
(a4), utilize above-mentioned silicon nitride layer for masking layer, second silicon dioxide layer of 5000 ~ 7000 is produced in thermal oxidation, to obtain the field oxygen (12) be positioned on substrate (11);
(a5) the first silicon dioxide layer and the silicon nitride layer of inner side, above-mentioned field oxygen (12), is removed;
In described step (c), during described injection N-type ion, first inject P ion, reinject As ion, and wherein, P/As implantation dosage is: 1.0E15 ~ 7.0E15/cm
2, P/As Implantation Energy is: 50 ~ 80kev, and annealing process temperature is 900 ~ 1050 DEG C, degeneration atmosphere N
2;
In described step (d), corrosion masking layer (15) is amorphous silicon layer, and the thickness of corrosion masking layer (15) is 500 ~ 2000, and the temperature of deposit corrosion masking layer (15) is 490 ~ 580 DEG C, and pressure is 250 ~ 450mtorr;
In described step (f), the pressure 50 ~ 100torr of described growth tunnel oxidation layer (16), O
2flow control is at 8 ~ 15SLM, and temperature is 680 ~ 820 DEG C, and directly over N+ diffusion region (13), the thickness of tunnel oxidation layer (16) is 15 ~ 45;
In described step (g), the pressure of LPCVD deposition silicon nitride film (17) is 250 ~ 450mtorr, DCS:NH
3=1:5 ~ 1:10, technological temperature is 680 ~ 780 DEG C, Si
3n
4thicknesses of layers is 40 ~ 100;
In described step (h), adopt wet-oxygen oxidation growth to obtain the top layer oxide layer (18) of 10 ~ 35, temperature is 900 ~ 1050 DEG C; And adopt N
2o anneals, N
2o annealing process pressure 50 ~ 100torr, technological temperature 800 ~ 900 DEG C.
2. the preparation method of ONO antifuse unit structure according to claim 1, it is characterized in that, the thickness of described electric pole plate (19) is 3000 ~ 5000 polysilicon layers, and passes through POCL
3doping, makes the sheet resistance of electric pole plate (19) be 20 ~ 27 Ω/.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310097579.3A CN103151332B (en) | 2013-03-25 | 2013-03-25 | A kind of ONO antifuse unit structure and preparation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310097579.3A CN103151332B (en) | 2013-03-25 | 2013-03-25 | A kind of ONO antifuse unit structure and preparation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103151332A CN103151332A (en) | 2013-06-12 |
| CN103151332B true CN103151332B (en) | 2016-01-06 |
Family
ID=48549312
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310097579.3A Active CN103151332B (en) | 2013-03-25 | 2013-03-25 | A kind of ONO antifuse unit structure and preparation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103151332B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9735103B1 (en) | 2016-07-20 | 2017-08-15 | International Business Machines Corporation | Electrical antifuse having airgap or solid core |
| US9793207B1 (en) | 2016-07-20 | 2017-10-17 | International Business Machines Corporation | Electrical antifuse including phase change material |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR3050319B1 (en) * | 2016-04-14 | 2018-05-11 | Stmicroelectronics Sa | MEMORY CONFIGURABLE MEMORY |
| CN106169461B (en) * | 2016-09-22 | 2018-10-30 | 中国电子科技集团公司第五十八研究所 | Radioresistance PIP type ONO anti-fuse structures and CMOS technology Integration Method |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5242851A (en) * | 1991-07-16 | 1993-09-07 | Samsung Semiconductor, Inc. | Programmable interconnect device and method of manufacturing same |
| US5619063A (en) * | 1993-07-07 | 1997-04-08 | Actel Corporation | Edgeless, self-aligned, differential oxidation enhanced and difusion-controlled minimum-geometry antifuse and method of fabrication |
| US5661071A (en) * | 1996-04-01 | 1997-08-26 | Chartered Semiconductor Manufacturing Pte Ltd | Method of making an antifuse cell with tungsten silicide electrode |
| US5856234A (en) * | 1993-09-14 | 1999-01-05 | Actel Corporation | Method of fabricating an antifuse |
| US6307248B1 (en) * | 1996-04-08 | 2001-10-23 | Chartered Semiconductor Manufacturing Company | Definition of anti-fuse cell for programmable gate array application |
| CN102270578A (en) * | 2011-08-01 | 2011-12-07 | 无锡中微晶园电子有限公司 | Process for growing ultra-thin SiO2 on doped substrate |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7016225B2 (en) * | 2002-11-26 | 2006-03-21 | Tower Semiconductor Ltd. | Four-bit non-volatile memory transistor and array |
-
2013
- 2013-03-25 CN CN201310097579.3A patent/CN103151332B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5242851A (en) * | 1991-07-16 | 1993-09-07 | Samsung Semiconductor, Inc. | Programmable interconnect device and method of manufacturing same |
| US5619063A (en) * | 1993-07-07 | 1997-04-08 | Actel Corporation | Edgeless, self-aligned, differential oxidation enhanced and difusion-controlled minimum-geometry antifuse and method of fabrication |
| US5856234A (en) * | 1993-09-14 | 1999-01-05 | Actel Corporation | Method of fabricating an antifuse |
| US5661071A (en) * | 1996-04-01 | 1997-08-26 | Chartered Semiconductor Manufacturing Pte Ltd | Method of making an antifuse cell with tungsten silicide electrode |
| US6307248B1 (en) * | 1996-04-08 | 2001-10-23 | Chartered Semiconductor Manufacturing Company | Definition of anti-fuse cell for programmable gate array application |
| CN102270578A (en) * | 2011-08-01 | 2011-12-07 | 无锡中微晶园电子有限公司 | Process for growing ultra-thin SiO2 on doped substrate |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9735103B1 (en) | 2016-07-20 | 2017-08-15 | International Business Machines Corporation | Electrical antifuse having airgap or solid core |
| US9793207B1 (en) | 2016-07-20 | 2017-10-17 | International Business Machines Corporation | Electrical antifuse including phase change material |
| US9899318B2 (en) | 2016-07-20 | 2018-02-20 | International Business Machines Corporation | Method for providing electrical antifuse including phase change material |
| US9941203B2 (en) | 2016-07-20 | 2018-04-10 | International Business Machines Corporation | Method of making electrical antifuse |
| US9991201B2 (en) | 2016-07-20 | 2018-06-05 | International Business Machines Corporation | Electrical antifuse including phase change material of tantalum |
| US10056330B2 (en) | 2016-07-20 | 2018-08-21 | International Business Machines Corporation | Electrical antifuse having airgap or solid core |
| US10177088B2 (en) | 2016-07-20 | 2019-01-08 | International Business Machines Corporation | Electrical antifuse having solid core |
| US10236251B2 (en) | 2016-07-20 | 2019-03-19 | International Business Machines Corporation | Method for providing electrical antifuse including phase change material |
| US10236250B2 (en) | 2016-07-20 | 2019-03-19 | International Business Machines Corporation | Method for providing electrical antifuse including phase change material |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103151332A (en) | 2013-06-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103151332B (en) | A kind of ONO antifuse unit structure and preparation method thereof | |
| CN107464855A (en) | Silica-based solar cell N-type surface tunnel oxide passivation contact for producing method | |
| US8043981B2 (en) | Dual frequency low temperature oxidation of a semiconductor device | |
| CN107026218B (en) | The method for manufacturing solar battery | |
| CN103928344A (en) | Method for improving N-typed DiMOSFET channel mobility based on N-typed nanometer thin layer | |
| CN104701160B (en) | Manufacture the method and semiconductor structure of semiconductor structure | |
| CN107482078A (en) | Silica-based solar cell p-type surface tunnel oxide passivation contact for producing method | |
| CN106876256A (en) | SiC double flute UMOSFET devices and preparation method thereof | |
| CN103915334A (en) | Method for manufacturing high-performance double-layer polysilicon bipolar transistor | |
| CN105895511A (en) | SiC MOSFET manufacturing method based on self-aligning technology | |
| CN103887178B (en) | A kind of manufacture method straining vertical MOS device | |
| US20140209995A1 (en) | Non-Volatile Memory Cells Having Carbon Impurities and Related Manufacturing Methods | |
| CN106783607A (en) | A kind of trench gate IGBT device and preparation method thereof | |
| CN103451611B (en) | Be applicable to the low-leakage current HfO of gate dielectric layer 2the preparation method of film | |
| WO2019007189A1 (en) | Single-sided polo cell and manufacturing method thereof | |
| TW200408074A (en) | Method of manufacturing a flash memory cell | |
| CN208889671U (en) | A kind of solar battery | |
| CN114883185A (en) | Manufacturing method of IGBT chip with high current density | |
| CN101399209B (en) | Method for producing non-volatility memory | |
| CN106328523B (en) | The production method of radio frequency lateral direction bilateral diffusion MOS device | |
| CN100552921C (en) | Semiconductor device and manufacture method thereof | |
| JP2002016152A (en) | Manufacturing method of semiconductor device | |
| EP1709672A1 (en) | Structure and method for low vss resistance and reduced dibl in a floating gate memory cell | |
| JPH09223752A (en) | Manufacture of nonvolatile semiconductor storage device | |
| CN101950722A (en) | Method for manufacturing microwave power device by using double level polysilicon device structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CB03 | Change of inventor or designer information |
Inventor after: Liu Guozhu Inventor after: Xu Jing Inventor after: Chen Zhengcai Inventor after: Hong Genshen Inventor after: Wang Dong Inventor after: Luo Jing Inventor before: Liu Guozhu Inventor before: Xu Jing Inventor before: Chen Zhengcai Inventor before: Hong Gensheng Inventor before: Wang Dong Inventor before: Luo Jing |
|
| COR | Change of bibliographic data |