CN103109367A - 可堆叠的模塑微电子封装 - Google Patents

可堆叠的模塑微电子封装 Download PDF

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Publication number
CN103109367A
CN103109367A CN2011800442779A CN201180044277A CN103109367A CN 103109367 A CN103109367 A CN 103109367A CN 2011800442779 A CN2011800442779 A CN 2011800442779A CN 201180044277 A CN201180044277 A CN 201180044277A CN 103109367 A CN103109367 A CN 103109367A
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conductive pole
substrate
microelectronics packaging
sealant
opening
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CN103109367B (zh
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贝勒卡西姆·哈巴
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Adeia Semiconductor Solutions LLC
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Tessera LLC
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Abstract

微电子封装具有覆盖或安装至基板(100)的第一表面(102)的微电子元件(110)，及在第一表面上突出、或在基板远离第一表面的第二表面(104)上突出的基本为刚性的导电柱(106)。在基板的与上方有导电柱突出的基板表面相对的表面暴露的导电元件(108)，与微电子元件电互连。密封剂(130)覆盖微电子元件(110)及导电柱(106)从其上突出的基板(100)表面(102)的至少一部分，密封剂具有凹陷(336)或复数个开口(136、236)，每个开口允许与至少一个导电柱形成至少一个电连接。至少一些导电柱(106)彼此电绝缘，且设置为同时承载不同电位。在特定实施例中，密封剂(130)内的开口(136、140、146、236)至少部分地暴露与柱接合的导电块(144)、完全暴露柱(106)的顶面(126)并部分地暴露柱的边缘表面(138)、或只部分地暴露柱的顶面(126)。

Description

可堆叠的模塑微电子封装
相关申请的交叉引用
本申请要求专利申请号为12/838974、申请日为2010年7月19日的美国专利申请的申请日之利益，其公开的内容通过援引加入本文。
技术领域
本发明涉及微电子封装及制造或检测微电子封装的方法。
背景技术
微电子器件如半导体芯片，通常需要许多与其他电子元器件的输入和输出连接。半导体芯片或其他可类比的器件的输入与输出触点通常以大体上覆盖器件表面的格栅状图案的形式分布（一般称为“面阵”）；或可以平行并邻近于器件正面的每个边缘延伸的细长排的形式分布；或位于正面的中心。通常，器件如芯片必须物理地安装在基板如印刷电路板上，且器件的触点必须与电路板上的导电特征电连接。
半导体芯片一般设置在封装内，在加工过程及在把芯片安装在如电路板或其他电路面板的外部基板上的过程中，封装方便对芯片进行处理。例如，许多半导体芯片设置在适于表面安装的封装内。为了各种应用，已推出了大量的这种普通类型的封装。最常见的，这种封装包括一般称为“芯片载体”的介电元件，介电元件具有如在电介质上电镀或蚀刻金属结构而形成的端子。这些端子通常与芯片自身的触点，通过如沿芯片载体自身延伸的薄迹线，及在芯片触点与端子或迹线之间延伸的精细引脚或引线等导电特征而连接。在表面安装操作中，封装放置在电路板上，使得封装上的每个端子与电路板上相对应的接触垫对齐。在端子与接触垫之间设置焊料或其他结合材料。通过加热组件使得焊料熔融或“回流”或以其他方式使结合材料起作用，封装可永久地结合定位。
许多封装包括附接至封装的端子上的以焊料球形式的焊料块，焊料块通常具有约0.1毫米与约0.8毫米（5密耳及30密耳）的直径。具有从其底面突出的焊料球的阵列的封装，一般称为球格栅阵列封装或“BGA”封装。称为格栅阵列封装(land grid array)或“LGA”封装的其他封装，通过焊料形成的薄层或面而固定至基板上。这种类型的封装可非常紧凑。一般称为“芯片级封装”的某些封装，占据电路板的面积等于或仅稍大于纳入封装内的器件的面积。这对降低组件的总体尺寸，及在基板上的各器件之间允许使用较短的互连来说是有利的，互连反过来限定器件间的信号延迟时间，因此便于组件在高速下工作。
包括封装的组件可经受由器件与基板之间热膨胀与热收缩的差异所施加的应力。在工作过程中，以及在制造过程中，半导体芯片膨胀及收缩的量倾向于与电路板膨胀及收缩的量不同。封装的端子相对芯片或其他器件是固定的，如通过应用焊料，这些作用倾向于致使端子相对电路板上的接触垫移动。这可对连接端子与电路板的接触垫的焊料施加应力。正如专利号为5679977、5148266、5148265、5455390、5518964的美国专利的某些优选实施例中所公开的，半导体芯片封装可具有相对于纳入封装的芯片或其他器件可移动的端子，其公开的内容通过援引加入本文。这种移动可补偿显著程度的膨胀和收缩差异。
封装器件的检测引起另一难以克服的问题。在一些制造过程中，使封装器件的端子与检测夹具之间建立临时连接，并通过这些连接来操作器件，以确定器件是功能齐全的是必要的。一般地，这些临时连接必须形成为没有封装端子与检测夹具的结合。确保所有端子与检测夹具的导电元件可靠连接是非常重要的。但是，通过把封装压向具有平面接触垫的简单检测夹具如普通电路板，而形成连接是困难的。如果封装的各端子没有共面，或如果检测夹具的导电元件不共面，则一些端子将不与检测夹具上与它们相对应的接触垫接触。例如，在BGA封装内，附接在端子上的焊料球直径的不同、及芯片载体的非平面性，都可导致这些焊料球处于不同的高度。
通过应用具有设置非平面性补偿的导电特征的特殊结构的检测夹具，这些问题可缓解。但是，这种导电特征增加了检测夹具的成本，且在一些情况下，带来了检测夹具自身的一些不可靠性。这是尤其不理想的，因为检测夹具及器件与检测夹具间的接合，应当是比封装器件自身的更可靠，才能提供有意义的检测。此外，用于高频率工作的器件典型地通过应用高频信号来检测。这种要求对检测夹具内信号通道的电气特性施加了约束，其进一步使检测夹具的结构复杂化。
另外，当检测具有与端子连接的焊料球的封装器件时，焊料倾向于在检测夹具的与焊料球接合的那些部分上累积。这种焊料残渣的积累可缩短检测夹具的使用寿命，并损害其可靠性。
为解决上述问题已推出各种方案。上述专利中公开的某些封装具有可相对微电子器件移动的端子。在检测时这种移动可补偿端子的一些程度上的非平面度。
专利号为5196726与5214308的美国专利，申请人都为Nishiguchi等，公开了一种BGA类型的方法，其中芯片面上的凸点引脚容纳在基板上杯状的插口内，并通过低熔点材料而在插入内结合。申请人为Beaman等的专利号为4975079的美国专利，公开了一种用于芯片的检测插口,其中检测基板上的圆屋顶形状的触点位于锥形滑槽内。芯片被压向基板，使得焊料球进入锥形滑槽内，并与基板上圆屋顶形状的插脚接合。施加充足的力，使得圆屋顶形状的插脚使芯片的焊料球实际上变形。
BGA插口的进一步的示例可在共同转让的专利号为5802699、授权日为1998年9月8日的美国专利中发现，其公开的内容通过援引加入本文。’699专利公开了一种具有复数个孔的板状连接体。每个孔都设置有至少一个从孔上方向孔内延伸的弹性薄片触点。BGA装置的凸点引脚可进入孔内，使得凸点引脚与触点接合。可检测组件，如果合格，凸点引脚可与触点永久地结合。
共同转让的专利号为6202297、授权日为2001年3月20日的美国专利，公开了一种用于微电子器件的具有凸点引脚的连接体，及制造和应用连接体的方法，其公开的内容通过援引加入本文。在’297专利的一个实施例中，介电基板具有复数个从正面向上延伸的柱。各柱可布置为柱群的阵列，每个柱群都限定其间的一间隙。大致为薄片的触点从每个柱的顶部延伸。为检测器件，器件的凸点引脚都插入至相应的间隙内，从而与触点接合，当凸点引脚继续插入时触点与凸点引脚摩擦。典型地，当凸点引脚插入至间隙内时，触点的末梢部分朝着基板向下并从间隙中心向外偏斜。
共同转让的专利号为6177636的美国专利，公开了一种在微电子器件与支撑基板之间提供互连的方法及装置，其公开的内容通过援引加入本文。在’636专利的一个优选实施例中，制造用于微电子器件的互连元器件的方法包括，提供具有第一表面和第二表面的柔性芯片载体，并使导电板与芯片载体的第一表面耦合。然后选择性地蚀刻导电板以生成复数个基本为刚性的柱。柔性层可设置在支撑结构的第二表面上，且微电子器件如半导体芯片与柔性层接合，使得柔性层位于微电子器件与芯片载体之间，并留下从芯片载体的暴露表面突出的柱。柱与微电子器件电连接。柱形成突出的封装端子，可与基板如电路面板的导电特征在插口内接合或焊料结合。因为柱可相对微电子器件移动，当器件应用时，这种封装可实质上调节器件与支撑基板之间的热膨胀系数的不协调。此外，各柱的顶端可为共面的或接近共面的。
尽管在本领域内有上述进展，在制造或检测微电子封装方面的进一步改进仍是必要的。
发明内容
微电子封装具有覆盖或安装至基板的第一表面的微电子元件，及在第一表面上突出、或在基板的远离第一表面的第二表面上突出的基本为刚性的导电柱。在基板的与其上有导电柱突出的基板表面相对的表面暴露的导电元件，与微电子元件电互连。密封剂覆盖微电子元件及导电柱从其上突出的基板表面的至少一部分，密封剂具有凹陷或复数个开口，每个凹陷或开口允许形成与至少一个导电柱的至少一个电连接。至少一些导电柱彼此电绝缘，且适于同时承载不同电位。在特定实施例中，密封剂内的开口至少部分地暴露与柱接合的导电块、完全暴露柱的顶面并部分地暴露柱的边缘表面、或只部分地暴露柱的顶面。
在一个实施例中，导电柱在第一表面或第二表面中至少一个之上突出至第一高度，密封剂与导电柱接触且具有主表面，主表面位于与导电柱从其上突出的基板同一表面上方的第二高度，第二高度大于第一高度，密封剂的开口为在主表面内的开口。
在特定实施例中，导电柱可在第一表面上突出，且导电元件可在第二表面暴露。
在一个实施例中，第一表面可具有第一区域和从第一区域延伸的第二区域。微电子元件可覆盖第一区域，各柱可与第二区域对齐。
在特定实施例中，导电柱可在第二表面上突出，导电元件可在第一表面暴露。
密封剂的主表面可为基本平坦的表面。密封剂可进一步具有在第一表面上方的第三高度覆盖微电子元件的第二表面，第三高度与第二高度不同，例如比第二高度更高。
在一个实施例中，密封剂的主表面可为基本平坦的表面，其在至少基本均一的第二高度覆盖第一表面的第一区域和第二区域，并覆盖微电子元件。
在一个变例中，至少一个导电柱可包括远离微电子元件的顶部区域及位于顶部区域下方且更邻近基板的第二区域。第二区域和顶部区域可分别具有凹的外周面。至少一个柱可主要由金属组成，且具有一水平尺寸，在顶部区域内水平尺寸为竖直位置的第一函数，且在第二区域内水平尺寸为竖直位置的第二函数。
在一个实施例中，导电元件包括导电柱或导电结合材料块中的至少一个，密封剂的一部分覆盖第二表面。这个部分可具有在高于第二表面的一高度的主表面，且在主表面内具有凹陷或一个或多个开口中的至少一种。凹陷或一个或多个开口可至少部分地暴露至少一个用于电连接的导电元件。至少一些导电元件可彼此电绝缘，且适于同时承载不同的电位。
在一个或多个实施例中，至少两个导电柱的表面或至少两个导电块的表面至少部分地暴露在单个开口内。
根据一个实施例，提供了一种制造微电子封装的方法。这种方法可包括提供微电子组件，其包括基板、安装至基板的微电子元件、及具有远离基板的顶面的基本为刚性的导电柱。导电柱中的第一导电柱和第二导电柱可通过基板的导电特征与微电子元件电连接，用于在第一导电柱承载第一信号电位，并同时在第二导电柱承载第二电位，第二电位与第一信号电位不同。然后密封剂层可形成为覆盖微电子元件的至少一部分，并覆盖导电柱的顶面。然后可在密封剂层内形成凹陷或一个或多个开口中的至少一种。每个凹陷或开口可与导电柱中至少一个对齐，且每个凹陷或开口允许形成与至少一个导电柱的电连接。
在一个实施例中，密封剂层可与导电柱接触，每个凹陷或开口可至少部分地暴露至少一个导电柱。
在一个实施例中，至少一个单独的开口可至少部分地暴露两个或更多的导电柱。
微电子组件可进一步包括与相应的导电柱接合的导电块。形成在密封剂层内的每个凹陷或开口可至少部分地暴露至少一个导电块。在特定的实施例中，至少一个单独的开口可至少部分地暴露两个或更多的导电块。
密封剂层可形成为具有基本平坦的表面，凹陷或开口可从基本平坦的表面延伸或形成在基本平坦的表面内。
在一个实施例中，导电柱可具有从顶面向外延伸的边缘表面，至少一个导电柱的边缘表面可至少部分地暴露在至少一个开口内。
在特定的实施例中，可至少制造第一微电子封装和第二微电子封装，然后第二微电子封装可堆叠在第一微电子封装的顶上，并应用第一微电子封装和第二微电子封装中至少一个的导电柱，而使第一微电子封装和第二微电子封装电互连在一起。
在进一步的示例中，形成密封剂层的步骤可包括，在基板表面的上方形成密封剂层的基本平坦的第一表面和第二表面。第一表面可覆盖基板与微电子元件对齐的至少一部分，且第二表面可覆盖基板的超出微电子元件边缘的另一部分。从基板表面向上，第一表面和第二表面可具有不同高度。
附图说明
图1A是说明图1B中的微电子组件沿线1A-1A进行剖切时的剖视图。
图1B是说明图1A所示微电子组件的俯视图。
图1C是说明根据本发明实施例形成的导电柱的局部剖视图。
图1D是说明根据图1C所示柱的变例的柱的局部剖视图。
图1E是说明形成图1D所示柱的方法的局部剖视图。
图1F、图1G、图1H及图1I是说明与形成柱相关的制造方法中各阶段的局部剖视图。
图2是进一步说明图1I所示柱的部分局部剖视图。
图3是说明根据本发明实施例微电子封装制造方法中模塑阶段的剖视图。
图4是说明制造方法中图3所示阶段随后的阶段的剖视图。
图5是说明根据本发明实施例微电子封装的剖视图。
图5A是说明根据图5所示本发明实施例的变例的微电子封装的剖视图。
图5B是说明根据图5所示本发明实施例的进一步的变例的微电子封装的剖视图。
图6是说明根据图5所示本发明实施例的变例的微电子封装的剖视图。
图7是说明根据图5所示本发明实施例的变例的微电子封装的剖视图。
图8是说明根据图5所示本发明实施例的变例的微电子封装的剖视图。
图9是说明根据图3所示实施例的变例的微电子封装制造方法中模塑阶段的剖视图。
图10是说明根据图6所示实施例的变例的微电子封装的剖视图。
图11是说明根据图7所示实施例的变例的微电子封装的剖视图。
图12是说明根据本发明实施例的堆叠微电子组件的剖视图。
图13是说明根据图8所示实施例的变例的微电子封装的剖视图。
具体实施方式
参照图1A，根据本发明的一个实施例，微电子封装包括基板100，基板具有邻近微电子元件110的面114的第一表面或顶面102，及与其相对的第二表面或底面104。微电子元件110可为具有面向上朝向图1A顶部的正面113、及朝向相反的向后方向的背面114的第一半导体芯片。背面114大致与正面113平行。平行于正面113的方向本文称为“水平”或“横向”方向；而垂直于正面的方向本文称为向上或向下的方向，在本文还称为“竖直”方向。本文所指的方向是在参照结构的参照系中。因此，这些方向可设置在常规或重力参照系中的任意方向。声明一个特征与另一特征相比，位于“表面上方”较高的高度，意味着这两个特征都以同一正交方向偏离该表面，但沿该同一正交方向该一个特征比该另一个特征距该表面的距离更远。相反地，声明一个特征与另一个特征相比，位于“表面上方”较低高度，意味着这两个特征都以同一正交方向偏离该表面，但沿该同一正交方向该一个特征比该另一个特征距该表面的距离更近。
微电子元件110包括位于邻近正面113的相对薄的层内的有源电路元件。有源电路元件可包括如晶体管、二级管及其他元件等的器件，以及包含这些器件的电路。典型地，有源电路元件具有的尺寸在几微米或更小的量级(order)。
基板100包括在顶面102暴露的第一导电柱106及在基板100第二表面104暴露的导电元件108。在本文中应用的，导电元件“暴露在”介电元件的表面，可以是与这样的：与表面平齐、相对于该表面凹陷、或者从该表面突出，只要该导电元件可与以垂直于该表面的方向向该表面移动的一个理论点接触即可。
在图1A所示的示例中，导电元件108为导电垫。基板100可为柔性的，且在一个实施例中可由介电材料如聚酰亚胺制成。基板通常具有导电特征，导电特征还可具有在顶面102上的、底面104上的和/或在顶面与底面之间延伸的导电迹线（未示出）。微电子元件110如半导体芯片，附接至基板100的第一表面102。从图1A至图1B中可以看出，微电子元件的触点117可应用如结合引线等的导电元件112与一个或多个导电垫105电互连。相应地，导电垫105可与导电柱106连接。至少一些导电柱彼此电绝缘，并适于承载不同电位，例如，不同信号、或不同电压，例如电源、地面、或其组合。粘接剂115可用于把微电子元件的背面114粘在基板上，背面与正面即承载触点的面相对。
当从基板顶面102上方来看时，每个导电柱的基底107可具有与结合层接触的区域，该区域可比柱的顶面126大。例如，基底107可为圆形的、椭圆形的、长方形的或其他矩形的或多边形的形状。顶面126可限定柱的顶端或顶点。位于基板的顶面102上方的顶面或顶端，可具有比基底小的面积。典型地，当从顶面102上方来看时，顶端具有与基底相同的形状。柱的形状是相当随意的，不仅可为截头圆锥，即截去头端的圆锥体，其为圆锥体的一部分，该圆锥体的尖端被沿与其底部平面平行或大致平行的面切去，如图所示。替代地，导电柱还可具有圆柱体、圆锥体、或任意其他类似形状，如圆顶锥(cone with round top)或平台形状(plateau shape)。此外，除了具有圆形横截面的，如截头圆锥等被称为“旋转体”的三维（3D）形状以外，或者并不是具有圆形横截面的三维（3D）形状，柱130可具有任意形状，如具有多边形水平截面的任意三维形状。典型地，该形状可通过改变耐蚀图案、蚀刻条件、或形成柱的原始层或金属箔的厚度而调整。尽管柱106的尺寸也为任意的，且不限制于任意特定的范围，通常，柱可形成为从基板100的暴露表面上突出50微米至300微米，如果柱具有圆形横截面，直径可设置在几十微米及更大的范围内。在特定实施例中，柱的直径的范围可为0.1毫米与10毫米之间。在特定实施例中，柱106的材料可为铜或铜合金。铜合金可包括铜与任何其他金属或多种金属的合金。制造柱及具有柱的基板的结构与细节可为如专利申请公开号为2007-0148822的美国专利申请中所描述的。
典型地，柱可通过蚀刻金属层，如各向同性地层压至基板的金属箔而形成，掩模14（图1C）放置在金属箔上或金属箔的上方，蚀刻过程从金属箔的与掩模14接触的表面，沿金属箔厚度10的方向，即朝向下方的基板顶面的方向向下进行。蚀刻可继续进行，直至基板100的在各柱之间的顶面102被完全暴露，从而每个柱的顶面126（图1A）从基板的顶面102向上具有相同高度，且各顶面126共平面。掩模14的宽度12通常比导电柱106在其与掩模接触的表面处的宽度大。
沿基板延伸的横向方向111、113，顶端的宽度135（图2）可为相同的或不同的。当在这两个方向上宽度相同时，宽度可代表顶端的直径。同样的，沿金属箔的横向方向111和113，基底的宽度137可为相同的或不同的，当是相同的时，宽度137可代表基底的直径。在一个实施例中，顶端可具有第一直径，基底可具有第二直径，其中第一直径与第二直径之间的差异可比在柱的顶端与基底之间延伸的柱高度的25%更大。
图1C示出了通过完全地蚀刻贯穿金属箔以暴露下方的基板100而形成导电柱106之后的基板。在特定示例中，导电柱可具有几十微米的高度，并具有几十微米的横向尺寸，例如直径。在特定示例中，高度和直径可都小于100微米。柱的直径小于导电垫的横向尺寸。每个柱的高度可比柱的直径更小或更大。
图1D示出了一变例，其中柱40形成为，与柱在参照图1C所描述而形成时的基底的宽度137（图1B）相比，与柱的高度46相关的基底宽度47可更窄。因此，与如上述方法形成的柱相比，可获得具有更大高宽比的柱40。在特定实施例中，柱40可通过应用掩模层48蚀刻部分的层状结构（图1E）而生成，其中层状结构包括第一金属箔50、第二金属箔52及位于其间的、例如夹在第一金属箔和第二金属箔之间的蚀刻隔离层54。所得的柱40可具有上部柱部分42和下部柱部分44，并可具有位于上部柱部分和下部柱部分之间的蚀刻隔离层45。在一个示例中，金属箔主要由铜组成，蚀刻隔离层45主要由如镍等不受蚀刻铜的蚀刻剂浸蚀(attack)的金属组成。替代地，蚀刻隔离层45可主要由可被用来图案化金属箔的蚀刻剂蚀刻的金属或金属合金组成，只是对隔离层45的蚀刻与金属箔相比更慢。以这种方式，当根据掩模层48蚀刻第一金属箔以限定上部柱部分时，蚀刻隔离层保护第二金属箔52不被浸蚀。然后，除去蚀刻隔离层45的暴露在上部柱部分42的边缘43之外的部分，之后应用上部柱部分作为掩模，蚀刻第二金属箔52。
所得的柱40可包括具有第一边缘的第一蚀刻部分，其中第一边缘具有第一曲率半径R1。柱40还具有至少一个在第一蚀刻部分与基板的顶面之间的第二蚀刻部分，其中第二蚀刻部分具有第二边缘，第二边缘具有与第一曲率半径不同的第二曲率半径R2。柱40可被描述的另一种方式为，每个导电柱包括远离基板的顶部区域，及位于顶部区域下方邻近基板的第二区域，第二区域和顶部区域分别具有凹的外周面，且每个固态金属柱具有一水平尺寸，在顶部区域内水平尺寸是竖直位置的第一函数，在第二区域内水平尺寸是竖直位置的第二函数。
在一个实施例中，当蚀刻第二金属箔以形成下部柱部分时，可部分地或完全地保护上部柱部分42，以免受进一步的浸蚀。例如，在蚀刻第二金属箔之前，为保护上部柱部分，可在上部柱部分的一边缘或各边缘43施加耐蚀材料。形成与图1D中所示的柱40类似的蚀刻金属柱的进一步的描述及方法，在共同拥有的专利申请号为11/717587，申请日为2007年3月13日的美国专利申请(Tessera 3.0-358 CIP CIP)中描述，其公开的内容通过援引加入本文。
在一个示例中，起始结构无需包括夹在第一金属箔和第二金属箔之间的蚀刻隔离层。替代地，上部柱部分可通过不完全蚀刻、如“半蚀刻”金属箔而形成，使得金属箔的突出部分32（图1F）被限定，以及在金属箔的曾暴露至蚀刻剂的地方，限定了突出部分之间的凹槽33。在光致抗蚀剂曝光及冲洗后用作掩模层56，可如图1F蚀刻箔58。一旦达到特定蚀刻深度后，即中断蚀刻过程。例如，蚀刻过程可在预定时间后停止。蚀刻过程留下了远离基板100向上突出的第一柱部分32，及在各第一柱部分之间限定的凹槽33。在蚀刻剂浸蚀箔58时，除去了掩模层56边缘下方的材料，允许掩模层从第一柱部分32的顶端横向突出，指示为悬垂部30。第一掩模层56保持在所示的特定位置。
一旦箔58被蚀刻至所需深度后，即在箔58的暴露表面上沉积第二光致抗蚀剂层34（图1G）。在这种情况下，第二光致抗蚀剂34可在箔58内的凹陷33上沉积，即在箔之前被蚀刻的位置。因此，第二光致抗蚀剂34还覆盖第一柱部分32。在一个示例中，可应用电泳沉积过程，以在箔58的暴露表面上选择性地形成第二光致抗蚀剂层。在这种情况下，第二光致抗蚀剂34可在没有覆盖第一光致抗蚀剂掩模层56的情况下沉积在箔上。
在接下来的步骤中，具有第一光致抗蚀剂56和第二光致抗蚀剂34的基板在辐射下曝光，然后冲洗第二光致抗蚀剂。如图1H所示，第一光致抗蚀剂56在箔58的一部分的上方横向突出，指示为悬垂部30。该悬垂部30防止第二光致抗蚀剂34在辐射下曝光，因此，防止其被冲洗及去除，致使部分的第二光致抗蚀剂34粘附在第一柱部分32上。因此，第一光致抗蚀剂56用作第二光致抗蚀剂34的掩模。第二光致抗蚀剂34通过清洗而冲洗以除去在辐射下曝光的第二光致抗蚀剂34。这样在第一柱部分32上留下第二光致抗蚀剂34的未曝光部分。
一旦部分的第二光致抗蚀剂34曝光及冲洗后，即可进行第二蚀刻过程，除去箔56的另外部分，从而在第一柱部分32的下方形成第二柱部分36，如图1I所示。在这个步骤中，第二光致抗蚀剂34，仍粘附在第一柱部分32上，保护第一柱部分32不被再次蚀刻。然后，可除去第一致抗蚀剂56和第二光致抗蚀剂34，留下从基板100的主表面突出的柱60。
这些步骤可被重复任意所需的次数，以形成第三个、第四个或第n个柱部分，构建优选的高宽比及间距。这个过程可在到达基板100时停止，这种层可用作蚀刻停止层或耐蚀层。作为最后的步骤，第一致抗蚀剂58和第二光致抗蚀剂34，可分别被完全剥离。
以这种方式，可形成具有的外形与柱40（图1D）类似的柱60（图1I），却无需在上部柱部分与下部柱部分之间设置图1D中所示的内部蚀刻隔离层45。应用这种方法，可制造各种形状的柱，其中上部柱部分和下部柱部分可具有类似的直径，或上部柱部分的直径可比下部柱部分的直径更大或更小。在特定的实施例中，通过应用上述的技术连续地形成从顶端至基底的柱的各部分，柱的直径可从顶端向基底逐渐变小，或可从顶端向基底逐渐变大。
通过上述过程（图1F至图1I）生成的柱60如图2所示。每个柱60具有在顶部区域或邻近顶部区域的第一部分32，及在第一部分下方且更接近基板表面的第二部分36。第一部分32的外周面22及第二部分36的外周面24是凹的表面，且每个外周面都具有沿Z向（基板表面上方的高度方向）位置至多逐渐变化的斜度或dX/dZ。关于本文所描述的柱的每个外周面（例如表面22或表面24），“凹陷”是指在外周面的边界之间的每个高度（如，在外周面22的上边界19与外周面22的下边界21之间的每个高度29），外周面围起的直径25，小于在相同高度29下，由理论圆锥面围起的直径，理论圆锥面由在边界之间延伸的一系列直线限定。例如，外周面22上在边界19、21之间的每个点，都位于穿过边界19、21延伸的一系列直线限定的理论圆锥面26的内部。
取代如上述的过程的通过蚀刻而形成柱的方法，柱1也可通过电镀工艺而形成，其中如光致抗蚀剂的牺牲层可沉积在基板的顶面上，之后通过光刻在牺牲层内形成开口。所述开口限定可电镀金属以形成柱的位置。典型地，通过这种方法形成的柱从基底至顶端具有均一的横截面，且可为例如圆柱的形状。
参照图3，一旦柱形成后，基板100即可放置在模具的盖板120与底板116之间。盖板120放置在底板116上方以在盖板与底板之间固定基板100。特别地，模具的盖板120可放置为与基板的第一表面102接触，且模具的底板116可放置为与基板100的第二表面104接触。模具盖板120可包括入口122，使可流动材料从其进入模具底板116与模具盖板120限定的空腔124内。
模具的盖板120可向基板的顶面102施压以限定具有一容积的内部空腔124。盖板120的内表面128可与导电柱106的顶面126并置并间隔开。在模塑过程中，底板116可提供对基板110的反作用力。然后，可固化的可流动材料如可固化的密封剂，可通过入口122注入模具的空腔124内。可固化的密封剂可为透明的、不透明的或具有透明与不透明之间标度的任意位置的光学性能。例如，当微电子元件110包括发射或接收可见光的波长范围的有源器件时，密封剂可为透明的。可固化材料优选地固化以形成固化的密封剂层，其优选地提供封装的稳定性并保护微电子元件110、导电结合引线112及导电柱106。
参照图4，导电柱106的顶面126从基板100的顶面102延伸至第一高度H1。模塑后，密封剂130可具有在高度H2的主表面134，其足以覆盖半导体芯片110、结合引线112和导电柱106。在图4所示的特定实施例中，从安装微电子元件的表面102的第一区域及在其上有导电柱126突出的表面102的第二区域，主表面134可具有均一的高度。导电柱106从基板100的顶面102上突出的高度H1小于密封剂主表面的高度H2，从而导电柱的顶面126埋在主表面134下方。
图5示出了制造微电子封装180的随后的步骤，其中在密封剂主表面134内形成至少部分地暴露导电柱106的开口136。在一个实施例中，开口136可在密封剂固化后形成。替代地，在一个变例中，开口136可在封装从模具取出后形成，此时密封剂只部分地固化。在这样的变例中，密封剂的完全固化可在密封剂内形成开口后发生。如图5特别地所示，开口136可形成为，使得至少部分地暴露单个导电柱的顶面126，并至少部分地暴露单个导电柱的边缘表面138。为了这个目的，可应用激光以烧蚀导电柱106顶面上方的密封剂材料，以形成开口136。机械钻孔或蚀刻为在密封剂内形成开口的其他可能方式。
开口可形成为完全地或部分地暴露一个或多个导电柱。在特定示例中，至少一个开口可只部分地暴露单个导电柱。以这种方式，开口可在密封剂层内提供绝缘的管道，使导电柱与电路板或如另一微电子封装等的其他元件上相对应的可与导电柱连接的导电元件之间的电连接绝缘。
在特定情况下，开口可暴露超过一个导电柱。在一个这样的示例中，整排的导电柱或这种排的一部分可在密封剂的一个开口内暴露或部分地暴露。在另一示例中，复数排柱或复数排柱的一部分可在密封剂的主表面的一个开口内暴露或部分地暴露。在特定示例中，在单个开口内或在各个开口内一起暴露或一起部分地暴露的复数个导电柱，可与在同一电位的一个或多个导电元件连接，例如用来形成地面或电源连接。但是，在一个实施例中，单个开口可至少部分地暴露复数个承载不同信号的柱，使得，例如电源、地面或信号中的至少两个的组合，可被在密封剂的单个开口内一起至少部分地暴露的至少两个柱同时承载。图5进一步示出了可与基板的导电垫108接合的导电块，如焊料球208。焊料球208可与导电柱对齐，以与其接合，如将在下文中所描述。除非另有说明，焊料球与如基板的垫等的导电元件的接合，蕴含在下面所示的实施例中。
在特定实施例中（图5A），其中至少两个柱106至少部分地在单个开口236内暴露，可采用锯形成与沿横过基板表面102的一个或多个水平方向延伸的开口236。在这种情况下，导电柱的顶面126’可暴露在开口内。在特定实施例中，导电柱的顶面126’可位于在开口内的密封剂层的表面238的上方、位于表面238的下方或与表面238平齐。在图5A所示的特定实施例中，开口236没有水平延伸至密封剂层的外周边缘，即，图5中所示密封剂层的外周边缘131。在图5B中可以看到的一个变例中，可应用锯或其他装置以形成密封剂层的凹陷336，其延伸至密封剂的外周边缘131且至少部分地暴露一个或复数个导电柱106。在特定实施例中，导电柱106的顶面126’可位于凹陷表面338的上方、位于凹陷表面338的下方或与凹陷表面338平齐。
图6示出了图5所示实施例的变例。在这个实施例中，开口以这种方式形成，导电柱106的顶面126只部分地暴露在每个开口140内。从图6中可以看出，柱的顶面126的部分142位于开口140与边缘表面138之间。在形成开口后，导电柱的顶面的这些部分142仍然埋在已固化的密封剂层130内。此外，在图6所示的实施例中，导电柱的边缘表面138埋在密封剂内。
图7示出了又一变例，其中导电块144，例如为锡、焊料或其他结合材料等的结合金属，与导电柱的顶面126及边缘表面138接触。形成在固化的密封剂材料130内的开口146至少部分地暴露导电块144，且还可暴露柱106的一部分。
图8示出了根据图5所示微电子封装的变例的微电子封装200。在这种情况下，密封剂130形成为具有复数个区域，具有从基板100的顶面102向上不同高度的主表面。如图8所示，密封剂130包括中心区域147，其具有在高度150并足够覆盖半导体芯片110和结合引线112的主表面148。如图8特别地所示，封装可包括堆叠的且与如基板100的导电垫等的导电元件电连接的复数个微电子元件110，如半导体芯片。替代地，与图5所示的实施例类似，微电子封装可包括单个的微电子元件110。
密封剂130还包括从中心区域147向基板100的外周边缘156延伸的外周区域151。在外周区域151，密封剂的主表面152具有的高度154低于密封剂在中心区域的高度150。典型地，通过如图3所示类似的方法，密封剂在中心区域147及外周区域151的主表面高度，由用于形成密封剂的模具的盖板120A的形状确定。参照图9，为形成具有不同高度的密封剂材料的中心区域与外周区域，与位于导电柱106上方的盖板120A内表面128B相对于基板顶面102的高度相比，位于微电子元件110和结合引线112上方的模具盖板120A内表面128A相对于基板顶面102的高度更大。
替代地，在一个变例中，在中心区域147及外周区域151中，密封剂层可形成位于同一高度150 的主表面，然后应用锯或其他装置，使外周区域的密封剂层高度缩减至较低的高度154。
图10示出了图8所示微电子封装的变例，其中导电柱106的顶面只部分地暴露在密封剂材料的开口140内，与上文参照图6所描述的实施例类似。
图11示出了图8所示微电子封装的变例，其中与导电柱106接合的导电块144的表面至少部分地暴露在密封材料的开口146内，与上文参照图7所描述的实施例类似。
图12示出了堆叠在其他微电子封装顶部的图8的微电子封装。特别地，第一微电子封装200A堆叠在第二微电子封装200B的顶上，第二微电子封装200B又堆叠在第三微电子封装200C的顶上。依次地，第三微电子封装堆叠在第四微电子封装200D的顶上。这四个微电子封装优选地相互电互连。第一微电子封装200A的导电块208A，如焊料球，与第二微电子封装200B的导电柱106B接触。在组装过程中，可升高导电块208A的温度，使得其至少部分地变为熔化状态，从而导电柱106B可至少部分地插入导电块208A，并彼此接合。然后导电块208A的温度降低，使得导电块再次固化，以通过导电柱106B和导电块208A而使基板200A与基板200B永久地连接。第二微电子封装200B与第三微电子封装200C之间的电连接以类似的方式形成，第三微电子封装200C与第四微电子封装200D之间的电连接也同样。典型地，形成组件内电连接的各微电子封装之间的接合是同时进行的，对其内所有封装都是如此。然而，这可只对封装的一子集进行，然后可进行进一步的接合过程，以使附加封装或一个或多个封装子集与其接合。尽管图12示出的组件包括一个在另一个之上堆叠的四个微电子封装，本发明设想具有两个或更多的微电子封装的任意大小的组件都可制造。例如，在一个实施例中，五个或更多个微电子封装的堆叠是可能的。堆叠中最上面或最下面的封装可与外部元件如电路板或检测板电连接，即通过焊料球、其他导电块或柱等。可选用的，如从图12中可以看出，组件中最上面的微电子封装200A可制造为在该封装200A的顶面152A没有如导电柱、导电块等的导电元件暴露。在单个微电子封装在堆叠内组装在一起之前，可对每个封装单独检测。
图13示出了根据图8所示实施例的变例的微电子封装。在这种情况下，如焊料球218这样的导电块在封装的顶面102暴露。密封剂层130覆盖一个微电子元件或复数个微电子元件110A、110B的面。
附加密封剂层230覆盖基板100的底面104，并具有暴露导电柱108顶面226的开口240，导电柱108从基板100的底面104向外突出。与上述实施例（图5）中的密封剂层130内的开口136类似，开口240可暴露导电柱的顶面226并部分地暴露导电柱的边缘表面238。可选择地，如焊料块、锡、导电胶及其他的导电块，可与导电柱108的表面接合。图13中示出的微电子300可堆叠，并以参照图12在上文所描述的类似的方式与一个或多个其他微电子封装接合。
在图13中示出的实施例的变例中，导电块218可被导电柱代替，如上文所述。在另一变例中，导电柱108的顶面226可只部分地暴露在开口240内，与如图6所示并在上文参照图6所描述的导电柱106和开口140的布置类似。在又一变例中，包括第二导电柱108的顶面226及边缘表面238的表面可在把组件放入模具之前与导电块接合，与如图7所示及参照图7在上文所描述的布置类似。在这种情况下，开口240至少部分地暴露与第二导电柱接合的导电块，与图8所示的布置类似，其中导电块144在开口146内部分地暴露。这些变例中的每一个都可与之前任一图中所示及参照之前任一图所描述的特征组合。尽管本发明并不受任何特定工作原理限制，据认为导电块的平面化将能使多个微电子封装大量生产，每个封装都具有标准的高度。图5、图5A、图5B、图6、图7、图8、图10、图11和图13中任一所示的结构可堆叠在其他微电子封装顶上，以形成堆叠组件，与图12中所示的堆叠组件类似。
在上述实施例的另一变例中，微电子元件110的触点承载面113（图1A），可邻近基板100的顶面102设置，且触点117可以倒装芯片的方式与暴露在基板顶面102的基板触点并置，并与其对齐，微电子元件的触点117与暴露在基板顶面的触点导电结合。这种布置可与之前所描述的任意实施例及变例相组合。此外，之前所示及所描述的实施例（图5、图5A、图5B、图6、图7、图8、图10、图11和图12）中，取代从基板底面向外突出的导电块108，在它们的位置处，微电子封装可具有如上所述的导电柱，或其上可与导电块组合的柱，导电块例如为像锡、焊料、导电胶等这样的导电结合材料块。可应用之前描述实施例的微电子封装的进一步细节包含在专利申请号为11/318404、申请日为2005年12月23日(Tessera 3.0-484)的美国专利申请中，其公开的内容通过援引加入本文。
优选实施例的之前描述旨在说明而不是限制本发明。其中制造微电子封装的特定方法及其结构，可如共同拥有的专利申请号为12/839038、发明人为Belgacem Haba、名称为“具有面阵单元连接体的可堆叠模塑微电子封装”、申请日为2010年7月19日的美国专利申请中进一步所描述，其公开的内容通过援引加入本文。
尽管本发明参照特定实施例进行描述，可以理解的是，这些实施例只是说明本发明的原理和应用。因此，应理解为，在不偏离由附加的权利要求书所确定的本发明实质和范围的情况下，说明性的实施例可做出许多修改及可设计出其他布置。 

Claims (26)

1.微电子封装，包括：
基板，具有第一表面及远离第一表面的第二表面；
微电子元件，覆盖所述第一表面；
基本为刚性的导电柱，在所述第一表面或所述第二表面中至少一个之上突出，所述导电柱具有远离所述基板的顶面及远离所述顶面延伸的边缘表面；
导电元件，暴露在与所述导电柱从其上突出的表面相对的基板表面，所述导电元件与所述微电子元件电互连；及
密封剂，覆盖所述微电子元件及所述导电柱从其上突出的基板表面的至少一部分，所述密封剂具有复数个开口，每个开口暴露至少一个所述导电柱的所述顶面且部分地暴露其所述边缘表面，其中所述导电柱中至少一些彼此电绝缘，且适于同时承载不同电位。
2.微电子封装，包括：
基板，具有第一表面及远离第一表面的第二表面；
微电子元件，覆盖所述第一表面；
基本为刚性的导电柱，在所述第一表面或所述第二表面中至少一个之上突出，所述导电柱具有远离所述基板的顶面及远离所述顶面延伸的边缘表面；
导电元件，暴露在与所述导电柱从其上突出的表面相对的基板表面，所述导电元件与所述微电子元件电互连；及
密封剂，覆盖所述微电子元件及所述导电柱从其上突出的基板表面的至少一部分，所述密封剂具有复数个开口，每个开口部分地暴露至少一个所述导电柱的所述顶面，其中所述导电柱中至少一些彼此电绝缘，且适于同时承载不同电位。
3.微电子封装，包括：
基板，具有第一表面及远离第一表面的第二表面；
微电子元件，覆盖所述第一表面；
基本为刚性的导电柱，在所述第一表面或所述第二表面中至少一个之上突出，所述导电柱具有远离所述基板的顶面及远离所述顶面延伸的边缘表面；
导电块，与所述导电柱接合；
导电元件，暴露在与所述导电柱从其上突出的表面相对的基板表面，所述导电元件与所述微电子元件电互连；及
密封剂，覆盖所述微电子元件及所述导电柱从其上突出的基板表面的至少一部分，所述密封剂具有复数个开口，每个开口部分地暴露至少一个与所述导电柱接合的所述导电块，其中所述导电块中至少一些彼此电绝缘，且适于同时承载不同电位。
4.根据权利要求1所述的微电子封装，其中所述导电柱在所述第一表面或所述第二表面中至少一个之上突出至第一高度，所述密封剂与所述导电柱接触并具有主表面，所述主表面位于所述导电柱从其上突出的所述基板同一表面上方的第二高度，所述第二高度大于所述第一高度，其中所述密封剂内的所述开口为在所述主表面内的开口。
5.根据权利要求2所述的微电子封装，其中所述导电柱在所述第一表面或所述第二表面中至少一个之上突出至第一高度，所述密封剂与所述导电柱接触并具有主表面，所述主表面位于所述导电柱从其上突出的所述基板同一表面上方的第二高度，所述第二高度大于所述第一高度，其中所述密封剂内的所述开口为在所述主表面内的开口。
6.根据权利要求3所述的微电子封装，其中所述导电块在所述第一表面或所述第二表面中至少一个之上突出至第一高度，所述密封剂与所述导电块接触并具有主表面，所述主表面位于所述导电块从其上突出的所述基板同一表面上方的第二高度，所述第二高度大于所述第一高度，其中所述密封剂内的所述开口为在所述主表面内的开口。
7.根据权利要求4、5或6所述的微电子封装，其中所述导电柱在所述第一表面之上突出，且所述导电元件在所述第二表面上暴露。
8.根据权利要求7所述的微电子封装，其中所述第一表面具有第一区域和从所述第一区域延伸的第二区域，所述微电子元件覆盖所述第一区域，所述柱与所述第二区域对齐。
9.根据权利要求4、5或6所述的微电子封装，其中所述导电柱在所述第二表面之上突出，且所述导电元件在所述第一表面暴露。
10.根据权利要求8所述的微电子元件，其中所述密封剂的所述主表面为基本平坦的表面，所述密封剂进一步具有在高于所述第一表面的第三高度覆盖所述微电子元件的第二表面，所述第三高度与所述第二高度不同。
11.根据权利要求10所述的微电子封装，其中所述第三高度比所述第二高度更高。
12.根据权利要求8所述的微电子封装，其中所述密封剂的所述主表面为基本平坦的表面，其在至少基本均一的第二高度覆盖所述第一表面的所述第一区域和所述第二区域，并覆盖所述微电子元件。
13.根据权利要求4、5或6所述的微电子封装，其中至少一个导电柱包括远离所述微电子元件的顶部区域及位于所述顶部区域下方且更邻近所述基板的第二区域，所述第二区域和所述顶部区域分别具有凹的外周面，所述至少一个柱主要由金属组成，且具有一水平尺寸，在所述顶部区域内所述水平尺寸为竖直位置的第一函数，且在所述第二区域内所述水平尺寸为竖直位置的第二函数。
14.根据权利要求7所述的微电子封装，其中所述导电元件包括导电柱或导电结合材料块中的至少一种，所述密封剂的一部分覆盖所述第二表面且进一步具有复数个第二开口，每个第二开口部分地暴露所述导电元件中的至少一个，其中所述导电元件中至少一些彼此电绝缘，且适于同时承载不同的电位。
15.根据权利要求4或5所述的微电子封装，其中所述导电柱中至少两个的表面在所述开口中的单个开口内至少部分地暴露。
16.根据权利要求6所述的微电子封装，其中所述导电块中至少两个的表面在所述开口中的单个开口内至少部分地暴露。
17.制造微电子封装的方法，包括：
提供微电子组件，所述微电子组件包括基板、安装至所述基板的微电子元件、及具有远离所述基板的顶面的基本为刚性的导电柱，其中所述导电柱中的第一导电柱和第二导电柱通过所述基板的导电特征与所述微电子元件电连接，用于在所述第一导电柱承载第一信号电位，并同时在所述第二导电柱承载第二电位，所述第二电位与所述第一信号电位不同；
然后形成覆盖所述微电子元件的至少一部分并覆盖所述导电柱的所述顶面的密封剂层；及
然后在密封剂层内形成数个开口，每个开口与所述导电柱中的至少一个对齐，每个开口允许形成与至少一个所述导电柱的电连接。
18.根据权利要求17所述的方法，其中所述密封剂层与所述导电柱接触，且每个开口至少部分地暴露所述导电柱中的至少一个。
19.根据权利要求18所述的方法，其中至少一个单独的开口至少部分地暴露所述导电柱中的两个或更多个。
20.根据权利要求17所述的方法，其中所述微电子组件进一步包括与各个所述导电柱接合的导电块，且形成在所述密封剂层内的每个开口至少部分地暴露所述导电块中的至少一个。
21.根据权利要求20所述的方法，其中至少一个单独的开口至少部分地暴露所述导电块中的两个或更多个。
22.根据权利要求17所述的方法，其中所述密封剂层形成为具有基本平坦的表面，且所述开口形成在所述基本平坦的表面内。
23.根据权利要求17所述的方法，其中所述导电柱具有远离所述顶面延伸的边缘表面，且至少一个导电柱的所述边缘表面至少部分地在至少一个所述开口内暴露。
24.根据权利要求17所述的方法，其中至少制造了第一微电子封装和第二微电子封装，进一步包括在所述第一微电子封装的顶上堆叠所述第二微电子封装，并采用所述第一微电子封装和所述第二微电子封装中至少一个微电子封装的所述导电柱，而使所述第一微电子封装与所述第二微电子封装电互连在一起。
25.根据权利要求17所述的方法，其中所述形成密封剂层的步骤包括，在所述基板的表面的上方形成所述密封剂层的基本平坦的第一表面和第二表面，所述第一表面覆盖所述基板的与所述微电子元件对齐的至少一部分，且所述第二表面覆盖所述基板的超出所述微电子元件的边缘的另一部分，所述第一表面和所述第二表面在所述基板的所述表面上方具有不同高度。
26.制造微电子封装的方法，包括：
提供微电子组件，所述微电子组件包括基板、覆盖所述基板的微电子元件、及具有远离所述基板的顶面的基本为刚性的导电柱，其中所述导电柱中的第一导电柱和第二导电柱通过所述基板与所述微电子元件电连接，用于在所述第一导电柱承载第一信号电位，并同时在所述第二导电柱承载第二电位，所述第二电位与所述第一信号电位不同；
然后形成覆盖所述微电子元件的至少一部分并覆盖所述导电柱的所述顶面的密封剂层；及
然后在密封剂层内形成与至少一个所述导电柱对齐的凹陷，所述凹陷允许形成与至少一个导电柱的电连接。
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US8482111B2 (en) 2013-07-09
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