CN103106164A

CN103106164A - Highly efficient direct memory access (DMA) controller

Info

Publication number: CN103106164A
Application number: CN2011103513123A
Authority: CN
Inventors: 石伟
Original assignee: Shenzhen Desay Microelectronic Technology Ltd Co
Current assignee: Shenzhen Desay Microelectronic Technology Ltd Co
Priority date: 2011-11-09
Filing date: 2011-11-09
Publication date: 2013-05-15

Abstract

The invention discloses a highly efficient direct memory access (DMA) controller which can effectively use bus throughput rate and reduce time delay. The DMA controller comprises a DMA control module which is used for controlling highly efficient mass data transmission among peripherals and internal memory, different peripherals, different memory areas. In the process of data transmission of the DMA controller, the peripherals can send transmission request signals of different levels according to different size of effective buffer memory space, and the signals of the level show that the peripherals need to immediately accept data or can delay for a period of time to accept data, while the DMA controller can control a bus priority dispatching module to modify the dispatching priority of the DMA controller in the bus according to different peripheral requests. With the technical scheme, DMA transmission between the peripherals and the DMA controller can be completed in the DMA controller transmission, when a plurality of main equipment are on the bus, the DMA controller can reduce the fact that the bus is taken by the DMA controller with other equipment, the bus throughput rate is improved, and the time delay caused by each main equipment on the bus taking the bus is reduced.

Description

A kind of high efficient DMA controller

Technical field

The present invention relates to technical field of integrated circuits, the method and apparatus of a kind of direct memory access (DMA) particularly, this DMA method and apparatus can be used for, but be not limited in digital signal processing device.

Background technology

Processor or digital signal processor are mainly used in the processing of data.Processor can comprise a processor core, a storer, and a dma controller, an external bus interface, and one or more external interface is used for realizing the data interaction of chip and outside.Processor core is used for completing the processing operation of data, and the processing of data must relate to the store operation with the data manipulation result of reading of data source.In the read-write of data, there is a class data read-write operation, i.e. in batches reading and writing data is about to a chunk data and moves from a storage area and make a storage area.

In processor, dma controller has realized that above-mentioned chunk data moves operation, thereby processor core is freed from heavy data-moving operation, the data that processor core can directly utilize DMA to move are carried out the data processing, and the data that also data can be completed have dma controller to move the address space of appointment.

In existing dma controller implementation method, when a plurality of peripheral hardware colleagues need to utilize dma controller to carry out data-moving, the read-write of dma controller all adopted the pattern of fixing priority or priority repeating query to carry out.One when being located at moving data outward, may cause another peripheral hardware that also needs to utilize dma controller to carry out data-moving to be in waiting status always, until another peripheral hardware just can carry out data-moving after having completed data-moving, therefore, said method will cause moving of data to have very large time-delay, and, also reduced the data throughout of system.

Summary of the invention

The technical matters that (one) will solve

In view of this, fundamental purpose of the present invention is to provide a kind of dma controller and transmission method of realizing effectively utilizing Bus through-put and reducing the efficient direct memory access DAM transmission of time delay, solve existing dma controller device when there is a plurality of main equipment in bus, time-delay and throughput problem in the heavy load situation.

(2) technical scheme

For achieving the above object, the invention provides a kind of dma controller and transmission method of realizing effectively utilizing Bus through-put and reducing the efficient direct memory access DAM transmission of time delay, comprising: the bus of the processor of configurable dma controller and peripheral hardware, dma controller, capable of dynamic priority scheduling, have the peripheral hardware that sends transfer request signal to DMA.Processor core can start dma controller according to the needs configuration that processor is executed the task, and the mode of operation that can utilize the peripheral hardware of dma controller the transmission of data, can accept DMA and complete the interrupt request that sends after data transmission.DMA can be according to the configuration of processor to it, carries out between the storer zones of different between data transmission, storer and peripheral hardware the data transmission and carry out data transmission between different peripheral.DMA can accept the data transfer request of a plurality of peripheral hardwares, this request has comprised the real-time property class information, dma controller is further according to the data transmission real-time demand of peripheral hardware, request bus scheduling module arranges the bus scheduling priority of dma controller, DMA carries out the data-moving operation after the control that obtains bus.Capable of dynamic dispatching priority bus module in processor system according to the request of other modules, dynamically arranges the bus priority of each main equipment on bus.At last, carry out the peripheral module of data source or data purpose as dma controller, can be according to the configuration of processor, start the dma operation pattern, the data-moving operation that makes it can accept dma controller, after work started, peripheral hardware can according to the size of its inside valid data buffer zone, send the data transfer request that comprises the real-time property demand levels to dma controller.

(3) beneficial effect

Can find out from technique scheme, the present invention has following beneficial effect:

1. dma controller and the transmission method that effectively utilizes Bus through-put and reduce the efficient direct memory access DAM transmission of time delay provided by the invention, can make the data-moving function between standby each data storage areas of preparation implement, processor core is discharged from moving data work.

2. dma controller and the transmission method that effectively utilizes Bus through-put and reduce the efficient direct memory access DAM transmission of time delay provided by the invention, make peripheral hardware can effectively obtain data, perhaps timely ready data are moved the appointed area by dma controller.

3. dma controller and the transmission method that effectively utilizes Bus through-put and reduce the efficient direct memory access DAM transmission of time delay provided by the invention, make processor in the situation that there are a plurality of main equipments on bus, reduced the possibility that different main equipments are seized (comprising dma controller) bus.

4. dma controller and the transmission method that effectively utilizes Bus through-put and reduce the efficient direct memory access DAM transmission of time delay provided by the invention, can use dma controller according to the real-time demand of data, rationally utilize bus resource, in the time of the real-time moving data of data, utilize high priority to obtain bus control right, and in the time of low real-time property demand, obtain the control of bus with lower priority.

Description of drawings

Below by for example and the accompanying drawing that is not construed as limiting the present invention is described, in figure, the represented meaning of identical label is identical.

Fig. 1 possesses the processor system structural drawing of dma controller

Embodiment

For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.

Fig. 1 has described the processor system structural drawing that comprises dma controller described in the invention.As shown in Figure 1, processor core 101 by system bus 107 with are connected equipment and connect, thereby realize the function of other equipment of access.Storer 102 equally by system bus 107 with are connected equipment and connect, it is as being carried out memory access by main equipments such as processor core 101 and dma controllers 103 from equipment on bus.Dma controller 103 can utilize bus 107 that data are moved another from equipment from one from equipment as main equipment.Can have a plurality of peripheral hardwares (104,105) in processor system, these peripheral hardwares hang on bus 107 equally, accept the read and write access operation of main equipment (101,103).Can be carried out read and write access by the peripheral hardware (104,105) that dma controller is accessed.And peripheral hardware can utilize connection 106 to send the dma operation request signal to dma controller, thereby requires DMA to realize the DMA data-moving.Bus priority scheduler module 108 on bus 107 can be accepted the priority scheduling request of dma controller 103, dma controller is set has certain bus access priority.

More than described and comprise dma controller in the processor system and how to connect at interior modules, further, below described the overall process how DMA realizes data-moving so that a blocks of data is moved peripheral hardware 104 from storer 102 as example.

At first, processor core 101 is according to the demand of data-moving, and configure dma controllers by bus 107: disposition data source is some addresses of storer 102; Configure the required data capacity of moving; The destination address that configuration data is moved is some addresses of peripheral hardware 104; In addition, data block size of configurable data-moving each time etc. also as required.

Processor core 101 is according to the demand of data-moving, by bus 107 configuration peripheral hardwares 104.Make it can work in DMA data-moving pattern.

Suppose that degree of depth of the interior existence of peripheral hardware 104 is 16 FIFO due to the data of accepting dma controller and sending.Can be that configuration peripheral hardware 104 can possess two other transfer request signals of level to the dma controller transmission so.That is when in the FIFO of peripheral hardware 104, the valid data degree of depth only has 4, sending the high level transmission signal of pleading, the request dma controller sends data as early as possible; When in the FIFO of peripheral hardware 104, the valid data degree of depth is 12, can ask dma controller to send data with low-level operation.Further, can configure above-mentioned dma controller each time the data block size of data-moving be 4, prevent that in the FIFO valid data degree of depth be the generation of 12 o'clock data from overflows.

Further, when dma controller when receiving high level transfer request signal, can make dma controller obtain as early as possible the control of bus by request bus scheduling module 108, reading out data from storer 102, then send data to peripheral hardware 104 as soon as possible.When dma controller when receiving low-level transfer request signal, can ask the bus scheduling module to obtain bus controller with lower priority, if this moment, processor core 101 also needed to access bus, due to peripheral hardware 104 not in the urgent need to obtaining data, can make processor 101 priority access buses, after by the time processor 101 discharges buses, the reentry control of bus of dma controller, then reading out data from storer 102 sends data to peripheral hardware 104.

Completed the capacity of the data-moving that processor core 101 sets when all dma controllers after, utilize the mode notification processor 101 that interrupts to complete this time data-moving.

Claims

1. the dma controller that realization effectively utilizes the efficient direct memory access DAM of Bus through-put and reduction time delay to transmit, is characterized by dma controller and comprise a data path for the data transmission between DMA data source and data purpose; Comprise a channel control logic and be used for configuration DMA data transfer mode; DMA transmits request interface; DMA priority scheduling request interface.

2. dma controller according to claim 1, it is characterized in that the data path module of controller according to source address, the destination address of data-moving, utilize that data bus is realized between internal memory and peripheral hardware, the data read-write operation between internal memory and internal memory, between peripheral hardware and peripheral hardware.

3. dma controller according to claim 1 is characterized in that the data path module of controller, and execution that can be concurrent is carried out read operation, carried out write operation to the data destination address from the data source address.

4. dma controller according to claim 1, it is characterized in that channel control logic is used to preserve the configuration of dma controller method of work, configuration can comprise the action after data source address, destination address, read-write operation pattern, read-write priority, DMA data-moving are completed.

5. dma controller according to claim 1 is characterized in that transmitting request interface and receives dma operation data source address, the corresponding peripheral hardware of destination address or internal memory for the dma operation request of data transmission; Accept the real-time demand information of this DMA read-write operation.

6. dma controller according to claim 1, it is characterized in that the real-time class information that the priority scheduling request interface receives according to dma controller, determine the priority of DMA data transmission on bus, dma controller is by the bus control right of priority scheduling request interface to bus scheduler application dma controller data-moving.