CN103050455A - Package on package structure - Google Patents
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- CN103050455A CN103050455A CN2012104176441A CN201210417644A CN103050455A CN 103050455 A CN103050455 A CN 103050455A CN 2012104176441 A CN2012104176441 A CN 2012104176441A CN 201210417644 A CN201210417644 A CN 201210417644A CN 103050455 A CN103050455 A CN 103050455A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
A package on package (PoP) structure is disclosed. The PoP structure includes a top package and a bottom package disposed thereunder. The top package includes a first substrate and a first die mounted onto the first substrate. The first substrate has a thermal conductivity which is more than 70 W/(mK). The bottom package includes a second substrate and a second die mounted onto the second substrate. An upper surface of the second die is in thermal contact with a lower surface of the first substrate. The package on package (PoP) structure can reduce or eliminate heat dissipation problems of a package on package structure.
Description
Technical field
The invention relates to semiconductor packaging, particularly relevant for a kind of three-dimensional (3D) stacked package (package on package, PoP) structure.
Background technology
Along with the development of electronic industry (for example, 3C (computer, communication and consumer electronics) related industry), increase for demand multi-functional, that have more the device of convenience and smaller szie fast.The demand further forces increases integrated circuit (IC) density.And increase the development that integrated circuit density has been brought up multiple chip package, such as encapsulation (package in package, PiP) and stacked package (package on package, PoP) in the encapsulation.Under the demand of high-effect and high integration (integration), the three-dimensional stacked encapsulation (3D PoP) that upper packaging body is stacked on the lower packaging body has become a kind of acceptable selection.
PoP is a kind of encapsulation technology, and tolerable is integrated the chip (for example, microprocessor, memory, logic OR optical integrated circuit etc.) with difference in functionality.Yet PoP needs higher power density compared to individual other one chip (chip/die) encapsulation.Therefore, when the semiconductor device size in power density increase and chip was dwindled (that is, IC density increases), it is more and more important that heat management becomes.The increase of power density and IC density is so that the hot total amount that PoP structure chips produces increases, and excessive heat can reduce device usefulness usually, and device may damage.
One of method that solves above-mentioned heat problem comprises provides fin (heat spreader), and this fin and chip carry out thermo-contact.Yet, in the PoP structure, because the existence of upper packaging body hindered and placed fin between the packaging body up and down, therefore be difficult to by the mode of the using fin heat that lower packaging body produces that dissipates.
Therefore, be necessary to seek a kind of new PoP structure, can alleviate or get rid of above-mentioned problem.
Summary of the invention
In view of this, the present invention proposes a kind of stack package structure of Improvement type.
According to an embodiment of the present invention, a kind of stack package structure is provided, comprising: upper packaging body comprises the first substrate and is installed in first suprabasil the first chip that wherein the thermal conductivity of the first substrate is greater than 70W/ (m * K); And lower packaging body, be positioned at the packaging body below, comprise the second substrate and be installed in second suprabasil the second chip, wherein the lower surface thermo-contact of the upper surface of the second chip and the first substrate.
According to another execution mode of the present invention, a kind of stack package structure is provided, comprising: upper packaging body comprises the first substrate and is installed in first suprabasil the first chip that wherein at least one electricity joint sheet of floating is positioned at the lower surface of the first substrate; And lower packaging body, be positioned at the packaging body below, comprise the second substrate and be installed in second suprabasil the second chip, the wherein upper surface of the second chip and the electricity joint sheet thermo-contact of floating.
Stack package structure provided by the present invention can reach the effect that alleviates or get rid of the stack package structure heat radiation.
Description of drawings
Fig. 1～Fig. 9 is the stack package structure generalized section according to embodiment of the present invention.
Embodiment
Below explanation has comprised manufacturing process and the purpose of embodiment of the present invention.Yet, be understood that these explanations are making and the uses in order to illustrate embodiment of the present invention, be not for limiting protection scope of the present invention.In specification and Figure of description, same or analogous parts use same or analogous label.In addition, for simplification and the convenience of Figure of description, amplified profile and the thickness of parts in the Figure of description.In addition, the parts of not describing in specification and Figure of description or disclosing are habitual in the art parts.
Please refer to Fig. 1, Fig. 1 is stacked package (PoP) the structural profile schematic diagram according to embodiment of the present invention.In the present embodiment, the PoP structure comprises packaging body 150 and is positioned at the lower packaging body 250 of packaging body 150 belows.Upper packaging body 150 comprises the first substrate 100 and is installed in the first chip (die) 102 in the first substrate 100.The first substrate 100 is as package substrates.Specifically, the first substrate 100 is also as the heating panel (heat dissipation plate) of lower packaging body 250.In the present embodiment, the thermal conductivity of the first substrate 100 is greater than 70W/ (m * K), and can be silicon base.A plurality of contacts/ joint sheet 100a and 100b are formed at respectively upper surface and the lower surface of the first substrate 100.Above-mentioned contact/ joint sheet 100a and 100b are used for being electrically connected between the first chip 102 and the lower packaging body 250.The first chip 102, memory chip for example can comprise a plurality of contacts of being formed at its lower surface/joint sheet 102a.The first chip 102 can be installed in the first substrate 100 by known crystalline substance (flip chip) mode of covering.For instance, the first chip 102 by contact/joint sheet 100a with contact/a plurality of projections 106 between the joint sheet 102a are electrically connected to the first substrate 100.Primer material 104, for example epoxy resin fills in the space between the first substrate 100 and the first chip 102, to protect above-mentioned projection 106.
In the present embodiment, the PoP structure can also comprise a plurality of projections 302, be arranged between the contacting of the contact of the first substrate 100/joint sheet 100b and the second substrate 200/joint sheet 200b, make the first substrate 100 and the first chip 102 of being located thereon is electrically connected to the second substrate 200 and is positioned at the second chip 202 in the second substrate 200.
The second chip 202 is high-power die, and operating period may produce a large amount of heat at device, therefore, and must loose heat except its generation.In the present embodiment, the lower surface thermo-contact of the upper surface of the second chip 202 and the first substrate 100 can be finished by the thermally conductive pathways that the first substrate 100 consists of heat radiation.In one embodiment, the second chip 202 can be by being arranged at heat-conducting interface material (thermal interface material, TIM) the 301 and first substrate 100 thermo-contacts between the second chip 202 and the first substrate 100.Heat-conducting interface material (TIM) 301 can comprise the phase-transition material of solder projection, copper bump, hot fat (being comprised of the silicone oil of inserting metal dust), micron silver or any kind.In another embodiment, the second chip 202 can be by direct the contact and the first substrate 100 thermo-contacts between this second chip and the first substrate 100.
Please refer to Fig. 2, Fig. 2 is the stack package structure generalized section according to embodiment of the present invention, and wherein also the description thereof will be omitted for the sake of clarity for parts use with Fig. 1 identical label identical with Fig. 1.In the present embodiment, the first chip 102 is installed in the first substrate 100 by the routing joint technology.For instance, the lower surface of the first chip 102 is attached on the upper surface of the first substrate 100 by adhesion layer 108.In addition, a plurality of wires 112 are electrically connected to a plurality of contacts of the first substrate 100/joint sheet 100a ' with a plurality of contacts of the first chip 102/joint sheet 102b.In the present embodiment, the first chip 102 and above-mentioned wire 112 are covered by adhesive material 110 (for example, epoxy resin).
Please refer to Fig. 3, Fig. 3 is the stack package structure generalized section according to embodiment of the present invention, and wherein also the description thereof will be omitted for the sake of clarity for parts use with Fig. 1 identical label identical with Fig. 1.Except adding fin, the PoP structure of present embodiment is identical with PoP structure shown in Figure 1.Upper packaging body 150 also comprises fin 114, the upper surface thermo-contact of this fin and the first chip 102.For instance, fin 114 is positioned in the first substrate 100, and covers the first chip 102.Fin 114 heat that the first chip 102 produces that can dissipate.In addition, fin 114 and the first substrate 100 can consist of thermally conductive pathways, the heat that second chip 202 that further dissipates produces.Therefore, compared to the PoP structure of Figure 1 and Figure 2, the radiating efficiency of PoP structure shown in Figure 3 can further promote.
Please refer to Fig. 4, Fig. 4 is the stack package structure generalized section according to embodiment of the present invention, and wherein also the description thereof will be omitted for the sake of clarity for parts use with Fig. 1 identical label identical with Fig. 1.PoP structural similarity in the present embodiment is in PoP structure shown in Figure 1.Compare with PoP structure shown in Figure 1, difference is can comprise a plurality of through holes (through substrate via, TSV) 203 that run through substrate in the second chip 202 of lower packaging body 250.Above-mentioned a plurality of through hole (TSV) that runs through substrate 203 is electrically connected a plurality of contact of a plurality of contacts of the first substrate 100/joint sheet 100c and the second substrate 200/joint sheet 200d, and the second chip 202 is electrically connected with the first substrate 100 and/or the second substrate 200 by a plurality of through holes 203 that run through substrate.In the present embodiment, the second chip 202 can be by in the heat-conducting interface material (not illustrating) between this second chip and the first substrate 100 or by direct the contact and the first substrate 100 thermo-contacts between this second chip and the first substrate 100.
Please refer to Fig. 5, Fig. 5 is the stack package structure generalized section according to embodiment of the present invention, and wherein also the description thereof will be omitted for the sake of clarity for parts use with Fig. 2 identical label identical with Fig. 2.PoP structural similarity in the present embodiment is in PoP structure shown in Figure 2.Compare with PoP structure shown in Figure 2, difference is can comprise a plurality of through holes 203 that run through substrate in the second chip 202 of lower packaging body 250.In addition, a plurality of through holes that run through substrate 203 are electrically connected a plurality of contact of a plurality of contacts of the first substrate 100/joint sheet 100c and the second substrate 200/joint sheet 200d, and the second chip 202 is electrically connected with the first substrate 100 and/or the second substrate 200 by a plurality of through holes 203 that run through substrate.Similarly, the second chip 202 can be by the heat-conducting interface material (not illustrating) between this second chip and the first substrate 100 and the first substrate 100 thermo-contacts, or by directly contacting and the first substrate 100 thermo-contacts with the first substrate 100.
Please refer to Fig. 6, Fig. 6 is the stack package structure generalized section according to embodiment of the present invention, and wherein also the description thereof will be omitted for the sake of clarity for parts use with Fig. 3 identical label identical with Fig. 3.PoP structural similarity in the present embodiment is in PoP structure shown in Figure 3.Compare with PoP structure shown in Figure 3, difference is can comprise a plurality of through holes 203 that run through substrate in the second chip 202 of lower packaging body 250.In addition, a plurality of through holes that run through substrate 203 are electrically connected a plurality of contact of a plurality of contacts of the first substrate 100/joint sheet 100c and the second substrate 200/joint sheet 200d, and the second chip 202 is electrically connected with the first substrate 100 and/or the second substrate 200 by a plurality of through holes 203 that run through substrate.Similarly, the second chip 202 can be by in the heat-conducting interface material (not illustrating) between this second chip and the first substrate 100 or by direct the contact and the first substrate 100 thermo-contacts between this second chip and the first substrate 100.According to above-mentioned execution mode, because package substrates can form thermally conductive pathways in the upper packaging body of PoP structure, the heat that the lower packaging body of dissipation PoP structure produces can not placed under the situation of any fin between therefore upper packaging body and the lower packaging body.Therefore, can prevent that locking apparatus usefulness reduces and avoids device to damage.In addition, owing to can extra fin be set at the upper packaging body of PoP structure, therefore can be by fin further the dissipate heat that PoP structure chips produces and then improving heat radiation efficiency.
Please refer to Fig. 7, Fig. 7 is the stack package structure generalized section according to embodiment of the present invention, and wherein also the description thereof will be omitted for the sake of clarity for parts use with Fig. 1 identical label identical with Fig. 1.PoP structure in the present embodiment its similar in appearance to PoP structure shown in Figure 1, compare with PoP structure shown in Figure 1, difference is that the first substrate 300 of upper packaging body 350 can comprise printed circuit board (PCB) (PCB), and as package substrates, wherein at least three layers of copper layer are embedded in the different layers position in the printed circuit board (PCB).In one embodiment, these copper layers comprise a plurality of contacts/joint sheet 300a, a plurality of contact/joint sheet 300b and heating panel 300c.One or more electricity joint sheet 304 of floating is positioned at the lower surface of the first substrate 300, wherein the electric joint sheet 304 of floating connects the wherein layer of copper layer (for example, heating panel 300c) of above-mentioned copper layer by being formed at the first substrate 300 interior connection window (via) 300d.In one embodiment, joint sheet 304 thermo-contacts of floating of the upper surface of the second chip 202 and at least one electricity are by the joint sheet 304 of being floated by electricity, connect the thermally conductive pathways that window 300d and heating panel 300c consist of and dispel the heat.In another embodiment, the second chip 202 can be by the heat-conducting interface material (not illustrating) between the joint sheet 304 of floating at this second chip and electricity, the phase-transition material of solder projection, copper bump, hot fat (being comprised of the silicone oil of inserting metal dust), micron silver or any kind for example is with electricity joint sheet 304 thermo-contacts of floating.In another embodiment, the second chip 202 can contact and electricity joint sheet 304 thermo-contacts of floating by float direct between the joint sheet 304 of this second chip and electricity.
Above-mentioned contact/ joint sheet 300a and 300b are used for being electrically connected between the second chip 202 and the upper packaging body 350.In addition, above-mentioned a plurality of contact/joint sheet 300a also is used for being electrically connected between the first chip 102 and the lower packaging body 250.In addition, the PoP structure also comprises a plurality of projections 302, be arranged between the contacting of the contact of the first substrate 300/joint sheet 300b and the second substrate 200/joint sheet 200b, make the first substrate 300 and the first chip 102 of being located thereon is electrically connected to the second substrate 200 and is positioned at the second chip 202 in the second substrate 200.
Please refer to Fig. 8, Fig. 8 is the stack package structure generalized section according to embodiment of the present invention, and wherein parts identical with Fig. 2 and Fig. 7 use respectively the label identical with Fig. 2 and Fig. 7 and the description thereof will be omitted for the sake of clarity respectively.Be different from PoP structure shown in Figure 2, the first substrate 300 of the upper packaging body 350 of PoP structure can be printed circuit board (PCB) among Fig. 8, and as package substrates, the first substrate 300 as shown in Figure 7.In addition, a plurality of wires 112 are electrically connected to a plurality of contacts of the first substrate 300/joint sheet 300e with a plurality of contacts of the first chip 102/joint sheet 102b.In the present embodiment, joint sheet 304 thermo-contacts of floating of the upper surface of the second chip 202 and at least one electricity are by the joint sheet 304 of being floated by electricity, connect the thermally conductive pathways that window 300d and heating panel 300c consist of and dispel the heat.
Please refer to Fig. 9, Fig. 9 is the stack package structure generalized section according to embodiment of the present invention, and wherein parts identical with Fig. 3 and Fig. 7 use respectively the label identical with Fig. 3 and Fig. 7 and the description thereof will be omitted for the sake of clarity respectively.Be different from PoP structure shown in Figure 3, the first substrate 300 of the upper packaging body 350 of PoP structure can be printed circuit board (PCB) among Fig. 9, and as package substrates, the first substrate 300 as shown in Figure 7.In the present embodiment, joint sheet 304 thermo-contacts of floating of the upper surface of the second chip 202 and at least one electricity, with by the joint sheet 304 of being floated by electricity, connect the thermally conductive pathways that window 300d, heating panel 300c and fin 114 consisted of and dispel the heat.
In addition, in one embodiment, can comprise respectively a plurality of through holes (not illustrating) that run through substrate in Fig. 7, Fig. 8 and the second chip 202 shown in Figure 9, such as Fig. 4, Fig. 5 and the second chip 202 shown in Figure 6, the second chip 202 is electrically connected with the first substrate 300 and the/the second substrate 200 by a plurality of through holes that run through substrate.
According to above-mentioned execution mode, because heating panel and the electricity joint sheet of floating can form thermally conductive pathways in the upper packaging body of PoP structure, the heat that the lower packaging body of dissipation PoP structure produces can not placed under the situation of any fin between therefore upper packaging body and the lower packaging body.Therefore, can prevent that locking apparatus usefulness reduces and avoids device to damage.In addition, owing to can extra fin be set at the upper packaging body of PoP structure, therefore can be by fin further the dissipate heat that PoP structure chips produces and then improving heat radiation efficiency.
Although the present invention discloses as above with preferred embodiments, yet this preferred embodiments is not to limit the present invention, those skilled in the art do not break away from the spirit and scope of the present invention, and all equalizations of doing according to the present patent application claim change and modify, and all should belong to covering scope of the present invention.
Claims (19)
1. a stack package structure is characterized in that, comprising:
Upper packaging body comprises the first substrate and is installed in this first suprabasil the first chip, and wherein the thermal conductivity of this first substrate is greater than 70W/ (m * K); And
Lower packaging body is positioned at packaging body below on this, comprises the second substrate and is installed in this second suprabasil the second chip, wherein lower surface thermo-contact of the upper surface of this second chip and this first substrate.
2. stack package structure according to claim 1 is characterized in that, packaging body also comprises fin on this, the upper surface thermo-contact of this fin and this first chip.
3. stack package structure according to claim 1 is characterized in that, this first chip is electrically connected to this first substrate by a plurality of projections or wire.
4. stack package structure according to claim 1 is characterized in that, this first substrate is silicon base.
5. stack package structure according to claim 1 is characterized in that, comprises a plurality of through holes that run through substrate in this second chip, and this second chip is electrically connected with this first substrate and/or this second substrate by these a plurality of through holes that run through substrate.
6. stack package structure according to claim 1, it is characterized in that this second chip is by the heat-conducting interface material between this second chip and this first substrate or by direct the contact and this first substrate thermo-contact between this second chip and this first substrate.
7. stack package structure according to claim 1, it is characterized in that, this second chip is by heat-conducting interface material and this first substrate thermo-contact between this second chip and this first substrate, and this heat-conducting interface material comprises solder projection, copper bump, hot fat or micron silver.
8. stack package structure according to claim 1 is characterized in that, comprises a plurality of projections, is arranged between this first substrate and this second substrate, makes this first substrate be electrically connected to this second substrate.
9. stack package structure according to claim 1 is characterized in that, the thermal conductivity of this second substrate is greater than 70W/ (m * K).
10. stack package structure according to claim 1 is characterized in that, this second substrate is silicon base.
11. a stack package structure is characterized in that, comprising:
Upper packaging body comprises the first substrate and is installed in this first suprabasil the first chip, and wherein at least one electricity joint sheet of floating is positioned at the lower surface of this first substrate; And
Lower packaging body is positioned on this packaging body below, comprises the second substrate and is installed in this second suprabasil the second chip, the wherein upper surface of this second chip and this electricity joint sheet thermo-contact of floating.
12. stack package structure according to claim 11 is characterized in that, packaging body also comprises fin on this, the upper surface thermo-contact of this fin and this first chip.
13. stack package structure according to claim 11 is characterized in that, this first chip is electrically connected to this first substrate by a plurality of projections or wire.
14. stack package structure according to claim 11 is characterized in that, this first substrate is printed circuit board (PCB).
15. stack package structure according to claim 14 is characterized in that, at least three layers of copper layer are embedded in the different layers position in this printed circuit board (PCB), and wherein this electricity joint sheet of floating is connected to the wherein layer of copper layer of these at least three layers of copper layers.
16. stack package structure according to claim 11 is characterized in that, comprises a plurality of through holes that run through substrate in this second chip, and this second chip is electrically connected with this first substrate and/or this second substrate by these a plurality of through holes that run through substrate.
17. stack package structure according to claim 11, it is characterized in that, this second chip by this second chip and this electricity float between the joint sheet heat-conducting interface material or contact and the joint sheet thermo-contact of floating of this electricity by float direct between the joint sheet of this second chip and this electricity.
18. stack package structure according to claim 11, it is characterized in that, this second chip is by heat-conducting interface material between the joint sheet and this electricity joint sheet thermo-contact of floating of floating of this second chip and this electricity, and this heat-conducting interface material comprises solder projection, copper bump, hot fat or micron silver.
19. stack package structure according to claim 11 is characterized in that, comprises a plurality of projections, is arranged between this first substrate and this second substrate, makes this first substrate be electrically connected to this second substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510083354.1A CN104882422A (en) | 2011-10-17 | 2012-10-17 | Package On Package Structure |
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201161548092P | 2011-10-17 | 2011-10-17 | |
| US61/548,092 | 2011-10-17 | ||
| US13/612,737 US20130093073A1 (en) | 2011-10-17 | 2012-09-12 | High thermal performance 3d package on package structure |
| US13/612,737 | 2012-09-12 |
Related Child Applications (1)
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| WO2021068657A1 (en) * | 2019-10-10 | 2021-04-15 | 华为技术有限公司 | Encapsulation structure and electronic apparatus |
| CN112885794A (en) * | 2021-01-15 | 2021-06-01 | 浪潮电子信息产业股份有限公司 | PCB (printed Circuit Board), POP (Point of Place) packaging heat dissipation structure and manufacturing method thereof |
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