CN103050399B - There is diode and the manufacture method thereof of three layers of dielectric passivation structure - Google Patents
There is diode and the manufacture method thereof of three layers of dielectric passivation structure Download PDFInfo
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- CN103050399B CN103050399B CN201210587556.6A CN201210587556A CN103050399B CN 103050399 B CN103050399 B CN 103050399B CN 201210587556 A CN201210587556 A CN 201210587556A CN 103050399 B CN103050399 B CN 103050399B
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Abstract
The invention provides a kind of diode and the manufacture method thereof with three layers of dielectric passivation structure, method step is as follows: utilize semiconductor technology to form the PN junction in the wafer with P contact zone and N contact zone; After front wafer surface growth silica dioxide medium, remove part silica dioxide medium, form the first window exposing P contact zone; Deposit to cover on silica dioxide medium and silicon nitride medium in first window, removes part silicon nitride medium, forms the Second Window exposing first window; The partial silicon nitride medium be close in Second Window and with Second Window makes front electrode; Silicon nitride medium and the partial elevational electrode that is close to silicon nitride medium cover and forms polyimide media; Make backplate at chip back surface, complete the processing of diode.The present invention can protect the PN junction of diode inside effectively, avoids being subject to extraneous mobile ion contamination and the impact of steam, thus ensures stability and the reliability of PN junction.
Description
Technical field
The invention belongs to semiconductor fabrication process technical field, particularly relate to a kind of diode and the manufacture method thereof with three layers of dielectric passivation structure.
Background technology
After utilizing semiconductor fabrication process to complete the PN junction of diode, generally can carry out passivation on the surface of wafer, for the protection of PN junction, avoid PN junction to be subject to extraneous contamination and the impact of steam, ensure stability and the reliability of PN junction.The quality of wafer surface passivation directly can affect the quality of diode, if passivation effect is bad, then diode is easier to be subject to the contamination such as steam, metal ion after rear operation encapsulation, diode electric property is degenerated, cause that diode leakage current becomes large, the drift of reverse breakdown curvilinear peristaltic, finally make PN junction disabling damage.The structure of passivation layer becomes the important guarantee of protection diode quality.
The surface passivation of diode is generally when semiconductor fabrication process makes PN junction, adopts hot growth pattern to form passivating structure at the certain thickness silicon dioxide of the superficial growth of PN junction, to play shielding to PN junction and protective effect.But simple silicon dioxide passivating structure effectively can not stop the impact of moveable metal ion and steam, diode electric property after rear operation encapsulation usually can be caused to degenerate.
Summary of the invention
The object of the present invention is to provide a kind of diode and the manufacture method thereof with three layers of dielectric passivation structure; effectively to protect the PN junction of diode inside; avoid being subject to extraneous mobile ion contamination and the impact of steam, thus ensure stability and the reliability of PN junction.
In order to solve the problem, the invention provides a kind of manufacture method with the diode of three layers of dielectric passivation structure, step is as follows:
Semiconductor technology is utilized to form the PN junction in the wafer with P contact zone and N contact zone;
After front wafer surface growth silica dioxide medium, remove part silica dioxide medium, form the first window exposing described P contact zone;
Deposit to cover on described silica dioxide medium and silicon nitride medium in first window, removes part silicon nitride medium, forms the Second Window exposing described first window;
The partial silicon nitride medium be close in described Second Window and with described Second Window makes front electrode;
Described silicon nitride medium and the partial elevational electrode that is close to described silicon nitride medium cover and forms polyimide media;
Make backplate at chip back surface, complete the processing of diode.
Further, described Second Window also exposes the process of the part of silica medium be close to first window and is: remove the partial silicon nitride medium be close to first window.
Further, described front electrode also covers on the part of silica SiClx medium that is close to described first window.
Further, the thickness of described silica dioxide medium is
Further, be 800 DEG C ~ 1250 DEG C in the temperature of front wafer surface oxidation growth silica dioxide medium, the time is 1h ~ 24h.
Further, the thickness of described silicon nitride medium is
Further, on described silica dioxide medium, the temperature of deposit silicon nitride medium is 600 DEG C ~ 1000 DEG C, and the time is 1h ~ 7h.
Further, the thickness of described polyimide media is 3 μm ~ 15 μm.
In order to reach another aspect of the present invention, a kind of diode with three layers of dielectric passivation structure being also provided, comprising:
Front electrode, is formed on the P contact zone in the PN junction of wafer;
Three layers of dielectric passivation structure, comprise silica dioxide medium, silicon nitride medium and polyimide media, and described silica dioxide medium to be formed on wafer and to surround the P contact zone be formed in PN junction; Described silicon nitride medium is formed on silica dioxide medium; Described polyimide media is formed on silicon nitride medium;
Described three layers of dielectric passivation close structure surround the front electrode on the P contact zone that is formed in PN junction, and described polyimide media also extends and is covered on partial elevational electrode and described front electrode also extends and is covered on partial silicon nitride medium;
Backplate, is formed on chip back surface.
Further, described front electrode also extends and is covered on the described silica dioxide medium of part.
Further, the thickness of described silica dioxide medium is
Further, the thickness of described silicon nitride medium is
Further, the thickness of described polyimide media is 3 μm ~ 15 μm.
As shown from the above technical solution, the present invention and tradition have compared with the diode of passivating structure, have following advantage: mate by reaching optimised process between three layers of dielectric passivation structure that silica dioxide medium, silicon nitride medium and polyimide media are formed respectively successively from the bottom to top; Described three layers of dielectric passivation structure can effectively ensure PN junction electrical stability and reliability.
Accompanying drawing explanation
Fig. 1 is the manufacture method schematic flow sheet with the diode of three layers of dielectric passivation structure of the present invention;
Fig. 2 to Fig. 7 is the manufacture method with the diode of three layers of dielectric passivation structure of the present invention.
Embodiment
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.
Set forth a lot of detail in the following description so that fully understand the present invention.But the present invention can be much different from alternate manner described here to implement, those skilled in the art can when without prejudice to doing similar popularization when intension of the present invention, therefore the present invention is by the restriction of following public concrete enforcement.
See Fig. 1, the invention provides a kind of flow process with the manufacture method of the diode of three layers of dielectric passivation structure is:
S1: utilize semiconductor technology to form the PN junction in the wafer with P contact zone and N contact zone;
S2: after front wafer surface growth silica dioxide medium, remove part silica dioxide medium, form the first window exposing described P contact zone;
S3: deposit to cover on described silica dioxide medium and silicon nitride medium in first window, removes part silicon nitride medium, forms the Second Window exposing described first window;
S4: the partial silicon nitride medium be close in described Second Window and with described Second Window makes front electrode;
S5: cover on described silicon nitride medium and the partial elevational electrode that is close to described silicon nitride medium and form polyimide media;
S6: make backplate at the described PN junction back side, complete the processing of diode.
Below for the method flow shown in Fig. 1, by reference to the accompanying drawings 2 to 7, a kind of manufacture craft of manufacture method of three layers of dielectric passivation structure of diode is described in detail.
S1: utilize semiconductor technology to form the PN junction in the wafer with P contact zone and N contact zone.
See Fig. 2, semiconductor technology is utilized to form the PN junction with P contact zone and N contact zone in the wafer.
S2: after front wafer surface growth silica dioxide medium, remove part silica dioxide medium, form the first window exposing described P contact zone.
See Fig. 3, be oxidized to front wafer surface, oxidizing temperature is 800 DEG C ~ 1250 DEG C, and oxidization time is 1h ~ 24h, and growth thickness is
silica dioxide medium 10 after, remove part silica dioxide medium, form first window 12, described first window exposes described P contact zone.
S3: deposit to cover on described silica dioxide medium and silicon nitride medium in first window, removes part silicon nitride medium, forms the Second Window exposing described first window.
See Fig. 4, on described silica dioxide medium 10 He in first window 12, carry out depositing technics, deposition temperature is 600 DEG C ~ 1000 DEG C, and deposition time is 1h ~ 7h, forms thickness to be
silicon nitride medium 14 after, remove the silicon nitride in described first window 12, formed Second Window 16.
Further, remove the partial silicon nitride medium be close to described first window 12, form the Second Window 16 also exposing the part of silica medium be close to described first window.
S4: the partial silicon nitride medium be close in described Second Window and with described Second Window makes front electrode.
See Fig. 5, in described Second Window 16 and on silicon nitride medium 14 after splash-proofing sputtering metal, remove part metals, the partial silicon nitride medium 16 be close in described Second Window 16 and with described Second Window is made into front electrode 18.
S5: cover on described silicon nitride medium and the partial elevational electrode that is close to described silicon nitride medium and form polyimide media.
See Fig. 6, on described silicon nitride medium 16 and front electrode 18, deposition thickness is after the polyimide media 20 of 3 μm ~ 15 μm, removal unit divides polyimide media 20, described silicon nitride medium 14 and the partial elevational electrode 18 that is close to described silicon nitride medium covers and forms described polyimide media 20.
S6: make backplate at the described PN junction back side, complete the processing of diode.
See Fig. 7, make the backplate 22 of PN junction, complete the processing of diode.
Based on above-mentioned manufacture method, see Fig. 7, the present invention forms a kind of diode with three layers of dielectric passivation structure, comprising:
Front electrode 18, is formed on the P contact zone in the PN junction of wafer;
Three layers of dielectric passivation structure, comprise silica dioxide medium 10, silicon nitride medium 14 and polyimide media 20, and described silica dioxide medium 10 to be formed on wafer and to surround the P contact zone be formed in PN junction; Described silicon nitride medium 14 is formed on described silica dioxide medium 10; Described polyimide media 20 is formed on silicon nitride medium 14;
Described three layers of dielectric passivation close structure surround the front electrode 18 on the P contact zone that is formed in PN junction, and described polyimide media 20 also extends to be covered to partial elevational electrode 20 also extends with described front electrode 20 and is covered on partial silicon nitride medium 14;
Backplate 22, is formed on chip back surface.
Further, described front electrode 18 also extends and is covered on the described silica dioxide medium 10 of part.
Further, the thickness of described silica dioxide medium 10 is
Further, the thickness of described silicon nitride medium 14 is
Further, the thickness of described polyimide media 20 is 3 μm ~ 15 μm.
Manufacture of the present invention obtains having the diode of three layers of dielectric passivation structure compared with adopting the diode of simple silicon dioxide passivating structure, both model is all 8A with current specification, withstand voltage specification is the diode of 200V is example, qualified wafer is carried out at identical conditions encapsulation and the screening of rear operation, and reliability test is carried out under identical standard, result of the test is as shown in table ():
Table (one)
From reliability test result above, the Stability and dependability of three layers of dielectric passivation structural test sample of diode of the present invention is better than the test piece only adopting simple silicon dioxide passivating structure, this is mainly because silicon dioxide passivating structure is more loose, effectively can not stop the impact of mobile ion and steam, make the bad stability of diode.Experimental project
And the diode with three layers of dielectric passivation structure disclosed by the invention to have employed be three layers of dielectric passivation structure of silicon dioxide, silicon nitride, polyimides from the bottom to top successively respectively, because silicon nitride material chemical stability is fabulous, and have good insulating properties and compactness, not only can fix and eliminate mobile ion, also can isolate the contamination of outer bound pair diode chip for backlight unit; Polyimide material tool stronger mechanical performance and resistance to chemical corrosion, diode can be made to have comparatively low-leakage current, and effectively can stop moisture, increase the moisture resistant ability of device, therefore described three layers of dielectric passivation structure reach best coupling on process structure, weaken the harmful effect to device.In addition, can realize well superposing covering between described three layers of dielectric passivation structure, also compensate for the shortcoming of simple silicon dioxide passivating structure, substantially increase the Stability and dependability of the PN junction of diode, greatly improve the qualification rate that diode is tested at high temperature reverse bias and tide temperature.
Although the present invention with preferred embodiment openly as above; but it is not for limiting claim; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible variation and amendment, the scope that therefore protection scope of the present invention should define with the claims in the present invention is as the criterion.
Claims (10)
1. have a manufacture method for the diode of three layers of dielectric passivation structure, step is as follows:
Semiconductor technology is utilized to form the PN junction in the wafer with P contact zone and N contact zone;
After front wafer surface growth silica dioxide medium, remove part silica dioxide medium, form the first window exposing described P contact zone;
Deposit to cover on described silica dioxide medium and silicon nitride medium in first window, and remove part silicon nitride medium, form the Second Window exposing described first window, described Second Window also exposes the part of silica medium be close to first window;
The partial silicon nitride medium be close in described Second Window and with described Second Window makes front electrode, and described front electrode also covers on the part of silica SiClx medium that is close to described first window;
Described silicon nitride medium and the partial elevational electrode that is close to described silicon nitride medium cover and forms polyimide media;
Make backplate at chip back surface, complete the processing of diode.
2. manufacture method as claimed in claim 1, it is characterized in that, be 800 DEG C ~ 1250 DEG C in the temperature of front wafer surface oxidation growth silica dioxide medium, the time is 1h ~ 24h.
3. manufacture method as claimed in claim 2, it is characterized in that, the thickness of described silica dioxide medium is
4. manufacture method as claimed in claim 1, it is characterized in that, on described silica dioxide medium, the temperature of deposit silicon nitride medium is 600 DEG C ~ 1000 DEG C, and the time is 1h ~ 7h.
5. manufacture method as claimed in claim 4, it is characterized in that, the thickness of described silicon nitride medium is
6. manufacture method as claimed in claim 1, it is characterized in that, the thickness of described polyimide media is 3 μm ~ 15 μm.
7. there is a diode for three layers of dielectric passivation structure, comprising:
Front electrode, is formed on the P contact zone in the PN junction of wafer;
Three layers of dielectric passivation structure, comprise silica dioxide medium, silicon nitride medium and polyimide media, and described silica dioxide medium to be formed on wafer and to surround the P contact zone be formed in PN junction; Described silicon nitride medium is formed on silica dioxide medium; Described polyimide media is formed on silicon nitride medium;
Described three layers of dielectric passivation close structure encirclement is formed in the front electrode on the P contact zone in PN junction, and described polyimide media also extends and to be covered on partial elevational electrode and described front electrode also extends and is covered on partial silicon nitride medium, described front electrode also extends and is covered on the described silica dioxide medium of part;
Backplate, is formed on chip back surface.
8. diode as claimed in claim 7, it is characterized in that, the thickness of described silica dioxide medium is
9. diode as claimed in claim 7, it is characterized in that, the thickness of described silicon nitride medium is
10. diode as claimed in claim 7, it is characterized in that, the thickness of described polyimide media is 3 μm ~ 15 μm.
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| CN201210587556.6A CN103050399B (en) | 2012-12-28 | 2012-12-28 | There is diode and the manufacture method thereof of three layers of dielectric passivation structure |
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| US6337283B1 (en) * | 1999-12-30 | 2002-01-08 | Sunpower Corporation | Method of fabricating a silicon solar cell |
| CN101419923A (en) * | 2007-10-25 | 2009-04-29 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for lead wire welding mat |
| CN101882650A (en) * | 2010-06-29 | 2010-11-10 | 常州大学 | Preparation method of solar cell with buried charge layer |
| CN202996812U (en) * | 2012-12-28 | 2013-06-12 | 杭州士兰集成电路有限公司 | Diode with three-layer medium passivation structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US20070018199A1 (en) * | 2005-07-20 | 2007-01-25 | Cree, Inc. | Nitride-based transistors and fabrication methods with an etch stop layer |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6337283B1 (en) * | 1999-12-30 | 2002-01-08 | Sunpower Corporation | Method of fabricating a silicon solar cell |
| CN101419923A (en) * | 2007-10-25 | 2009-04-29 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method for lead wire welding mat |
| CN101882650A (en) * | 2010-06-29 | 2010-11-10 | 常州大学 | Preparation method of solar cell with buried charge layer |
| CN202996812U (en) * | 2012-12-28 | 2013-06-12 | 杭州士兰集成电路有限公司 | Diode with three-layer medium passivation structure |
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