CN103036571A - Dual-mode delta-delta analog-to-digital converter and circuit thereof - Google Patents
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Abstract
The invention discloses a bimodal delta-delta analog-to-digital converter (ADC), which can realize a receiver with low intermediate frequency and near-zero intermediate frequency only under a hardware architecture. The bimodal delta-delta analog-to-digital converter comprises a first switched capacitor integrator, a second switched capacitor integrator and a third switched capacitor integrator, wherein the first switched capacitor integrator is used for integrating an input signal and a first feedback signal; the second switched capacitor type integrator is used for integrating the output of the first switched capacitor type integrator and a second feedback signal; a quantizer, for providing an output signal of the adc, having at least first and second logic states corresponding to outputs of the second switched capacitor integrator; a feedback circuit for providing the first feedback signal to the first switched capacitor integrator and the second feedback signal to the second switched capacitor integrator; and the modal component is used for providing modal signals to control the action of the first switched capacitor integrator and the action of the second switched capacitor integrator.
Description
Technical field
The present invention relates to a kind of bimodal δ-Δ analog-to-digital converter (ADC), relate in particular to and a kind ofly receive the bimodal δ belong to Low Medium Frequency and/or the nearly nearly zero intermediate frequency of zero intermediate frequency-Δ analog-to-digital converter in order to operate in.
Background technology
From nineteen sixty, δ-Δ analog-to-digital converter is widely used on the electronics industry.This δ-Δ technology is attractive to be because it does not need assembly on the exact matching chip by the control of precise time, thereby has realized high-resolution.Therefore, δ-Δ technology is one of them the selection of technology of many Application of integrated circuits.
A kind of basic δ-Δ analog-to-digital converter receives an analog input signal and deducts a feedback signal so that a wrong signal to be provided.The processing of this mistake signal is to see through a low pass filter then via quantizing to form a digital output signal.This digital output signal is fed back to digital to analog converter (Digital-to-Analog Converter, be called for short DAC) change this feedback digital signal and export analog signal to after, receive analog signal with front end and subtract each other.Except this feedback digital to analog converter, the simulated assembly that this basic δ-Δ analog-to-digital converter can be traditional is realized, such as operational amplifier, comparator and switching type capacitor filter etc.Because integrated circuit frequency speed allows to adopt higher sampling rate, therefore general δ-Δ analog-to-digital converter can provide high-resolution usually.Basic δ-Δ analog-to-digital converter by Feedback Technology quantizing noise migration high band, therefore can have high signal noise ratio (Signal to Noise Ratio, be called for short SNR), and this out-of-band quantizing noise also can fully be eliminated by traditional filtering technique.
With reference to US Patent No. 5,461, No. 381, award to Seaberg, its title is " having feed-back compensation δ-Δ analog-to-digital converter (Analog-to-Digital Converter is called for short ADC) and preparation method thereof ".It discloses one δ-Δ analog-to-digital converter and comprises first and second integrator, and a quantizer is connected to an output of this second integral device, and a feedback circuit is connected to the output of this quantizer.For fear of the delayed impact via actual circuit elements, this feedback circuit keep this feedback signal to this first integrator in a high impedance state until this quantizer is resolved the output of this second integral device.Therefore, this first integrator has been avoided the incorrect feedback signal of temporary transient totalling possibility.In addition, this feedback circuit also avoid this first integrator integration one input signal and this feedback signal until this feedback signal be driven to revise to correct attitude to respond the output of this quantizer.In order to finish these results, this feedback circuit is to comprise a compensating circuit in order to this quantizer of continuous judgement when solution to be arranged.
With reference to US Patent No. 6,225, No. 928, award to Green, its title is " the logical modulator of plural number band and method are used in δ-Δ analog-to-digital converter (ADC) ".It discloses by providing one to have on component matching insensitive cross-couplings discrete time plural number loop filter structure and by providing a simple architecture with the unmatched impact of correction modulator, and a discrete time cross-couplings to plural bypass modulator is changed to realize the logical δ of band-Δ.The logical modulator of these a plurality of bands comprises that a plurality of nonlinear resonators link together and as a linear complex operation device.Each resonator will be as a linear complex operation device, when the input signal of an imaginary number is delayed and the output signal of an imaginary number is enhanced at half sample interval at half sample interval.In addition, it is to adjust the related gain in real number and imaginary number path and adjust the related gain of real number and imaginary number input signal and eliminate by numeral that tuner does not mate the impact that causes depression of order, and this real number and imaginary number path system are connected on after the output of this analog-to-digital converter.
With reference to US Patent No. 6,954, No. 628, award to the people such as Minnis, its title is " radio receiver ".It discloses a radio receiver framework in operating in Low Medium Frequency (Low intermediate frequency, be called for short LIF) and nearly zero intermediate frequency (Near Zero Intermediate Frequency, be called for short NZIF) mode, it has the maximum recycling property of simulation and digital loop between mode.This receiver comprises a quadrature and falls and turn device to produce applying aspect (I) and quadrature (Q) signal and a complex filter in an intermediate frequency to eliminate image frequency.In this Low Medium Frequency mode, one end of the output of this filter (Q) is untapped, other yet (I) is digitized by a non-plural analog-to-digital converter, and then this digital signal is processed through digital filter again, so produce the quadrature intermediate frequency signal.In this nearly zero intermediate frequency mode, utilize that two non-plural digital to analog converters are parallel to carry out digitlization., channel filters and non-plural number is simulated to digital translation by carrying out, this can avoid the loop of repetition and provide energy-conservation significantly.
With reference to US Patent No. 7,176, No. 817, award to Jensen, its title is " having δ continuous time of shake-Δ analog-to-digital converter ".Its mixing that discloses digital signal processing and analog loopback is used to reduce residual noise and is present in δ continuous time-Δ analog-to-digital converter.By the special a small amount of random noise that adds, remove from the relevant quantizing noise of input signal and can significantly not reduce signal noise ratio (SNR) characteristic.In each embodiment, digital loop is used to produce required randomness, and the particular frequency spectrum of decorrelation and shake and simple analog loopback block are to be used for this shake signal of appropriate programming and interpolation to δ-Δ analog-to-digital converter loop continuous time.In an embodiment of this invention, random noise is added to this quantizer input, and at another embodiment of this invention, a random smallest number electric current that adds is kept original signal noise ratio in order to remove relevant this quantizing noise from input signal.
Now, bluetooth standard has enlarged the application from high speed to low power consumption.Develop simultaneously the framework of different radio frequency receivers to reach this radio frequency link requirement.Yet the design engineer should provide different designs satisfying the diversity of design specification, and this will be very consuming time and loses the time point of the first chance of winning the market.For example, the design engineer supports individually Low Medium Frequency and nearly zero intermediate frequency receiver in requisition for two different analog-to-digital converter hardware of design
So, be necessary to provide a kind of bimodal δ-Δ analog-to-digital converter, as long as a kind of hardware implement can be realized Low Medium Frequency and nearly zero intermediate frequency receiver.
Summary of the invention
Main purpose of the present invention namely is to provide a kind of bimodal δ-Δ analog-to-digital converter (ADC), as long as a kind of hardware implement can be implemented in Low Medium Frequency and nearly zero intermediate frequency receiver.By switching " mode " assembly in opening or closing, the operator can change the state of analog-to-digital converter provided by the present invention easily; Can determine to receive Low Medium Frequency (LIF) or nearly zero intermediate frequency (NZIF) signal.
For reaching above-mentioned purpose, the invention provides a kind of bimodal δ-Δ analog-to-digital converter, it is characterized in that, comprise:
The first switching capacitance integrator is used for an input signal and the first feedback signal are carried out integral operation;
The second switching capacitance integrator is coupled to described the first suitching type and holds integrator, is used for output signal and the second feedback signal of described the first switching capacitance integrator are carried out integral operation;
Quantizer has input to be coupled to described the second switching type capacitor integrator and output, is used for providing the output signal of described digital quantizer, has first and second kind logical states at least, corresponding to the output of the second switching type capacitor integrator;
Feedback circuit, be coupled to described the first switching type capacitor integrator and described the second switching type capacitor integrator, be used for providing described the first feedback signal to described the first switching type capacitor integrator and described the second feedback signal to described the second switching type capacitor integrator; And mode assembly, be coupled to the input of described the first switching type capacitor integrator and the output of described the second switching type capacitor integrator, be used for providing the action of mode signal to control described the first switching type capacitor integrator and the action of described the second switching type capacitor integrator.
According to the foregoing invention feature, described mode assembly comprises the first suitching type assembly to have first end and is coupled to the input of described the first switching type capacitor integrator and the input that the second end is coupled to described the second switching type capacitor integrator; The second suitching type assembly has input and the second end that first end is coupled to described the first switching type capacitor integrator; And the 3rd the suitching type assembly have first end and be coupled to second end of described the second suitching type assembly of described mode assembly and the output that the second end is coupled to described the second switching type capacitor integrator; Wherein said mode assembly is controlled described the first suitching type assembly, and described the second suitching type assembly and described the 3rd suitching type assembly are the states that opens or closes to determine.
In addition, the present invention also proposes a kind of receiver circuit that uses disclosed bimodal δ-Δ analog-to-digital converter.
For above and other objects of the present invention, feature and advantage can be become apparent, several preferred embodiments cited below particularly, and cooperation accompanying drawing are described in detail below.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the accompanying drawing of required use was done to introduce simply during the below will describe embodiment, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
Fig. 1 is a δ according to prior art-Δ analog-to-digital converter;
Fig. 2 is open bimodal δ according to previous invention-Δ analog-to-digital converter;
Fig. 3 is the calcspar of the receiver circuit of the bimodal δ that openly operates in nearly zero intermediate frequency-Δ analog-to-digital converter;
Fig. 4 operates in the signal flow graph of nearly zero intermediate frequency for open bimodal δ-Δ analog-to-digital converter;
Fig. 5 is the calcspar of the receiver circuit of the bimodal δ that openly operates in Low Medium Frequency-Δ analog-to-digital converter;
Fig. 6 operates in the signal flow graph of Low Medium Frequency for open bimodal δ-Δ analog-to-digital converter.
Description of reference numerals:
50 first switching capacitance integrators
60 second switching capacitance integrators
70 quantizers
100 bimodals δ-Δ analog-to-digital converter
102 suitching type assemblies
110 full differential operation amplifiers
111～115 capacitors
116～134 suitching type assemblies
150 full differential operation amplifiers
151～153 capacitors
156～159 suitching type assemblies
160～163 suitching type assemblies
170 feedback circuits
171,172 digital to analog converters
190 mode assemblies
191,192 inverters
200,201 receiver circuits
210 low noise amplifiers (Low Noise Amplifier is called for short LNA)
220,221 frequency mixers
230 low pass filters (Low Pass Filter is called for short LPF)
232 band pass filters (Band-Pass Filter is called for short BPF)
240 frequency synthesizers
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
For understanding the solution of the present invention, as shown in Figure 1, be a kind of δ according to prior art-Δ analog-to-digital converter (ADC), this δ-Δ analog-to-digital converter comprises the first switching capacitance integrator 50, is used for input signal and the first feedback signal are carried out integral operation; The second switching capacitance integrator 60 is coupled to described the first switching capacitance integrator 50, is used for output signal and the second feedback signal of described the first switching capacitance integrator are carried out integral operation; Quantizer 70, has input to be coupled to described the second switching type capacitor integrator 60 and output, be used for providing the output signal (DOUT) of described digital quantizer, have first and second logical states at least, corresponding to the output to the second switching type capacitor integrator 60; Feedback circuit 170, be coupled to described the first switching type capacitor integrator and this second switching type capacitor integrator, be used for providing described the first feedback signal to described the first switching type capacitor integrator 50 and described the second feedback signal to described the second switching type capacitor integrator 60;
These integrators 50,60 and feedback circuit 170 form a noise transfer function to filter out the noise that quantizes in the frequency band of this quantizer 70.By general switch-capacitor operation circuit method, this suitching type assembly present not overlapping FREQUENCY CONTROL switch together with capacitor forming integrator, the signal transfer function of this δ-Δ analog-to-digital converter is a Low-Pass Filter and noise transfer function is a high-pass type.The analog-to-digital converter advantage of this pattern is oversampling rate and high pass noise shape function, can obtain high signal noise ratio to meet general communication applications.Yet the design engineer supports individually Low Medium Frequency (low IF) and nearly zero intermediate frequency (NZIF) receiver in requisition for two kinds of different analog-to-digital converter hardware.This is time-consuming and easily loses the first chance of winning the market.
As shown in Figure 2, according to the invention discloses bimodal δ-Δ analog-to-digital converter, described bimodal δ-Δ analog-to-digital converter 100 comprises the first switching capacitance integrator 50; The second switching capacitance integrator 60; Quantizer 70; Feedback circuit 170; One mode assembly 190.
Described the first switching capacitance integrator 50 is used for input signal and the first feedback signal are carried out integral operation; Described the second switching capacitance integrator 60 is coupled to described the first switching type capacitor integrator 50, is used for output signal and the second feedback signal of described the first switching capacitance integrator 50 are carried out integral operation; Described quantizer 70, has input to be coupled to this second switching type capacitor integrator 60 and output, be used for providing the output signal (DOUT) of described digital quantizer, have first and second kind logical states at least, corresponding to the output of the second switching type capacitor integrator; Described feedback circuit 170, be coupled to described the first switching type capacitor integrator 50 and described the second switching type capacitor integrator 60, be used for providing described the first feedback signal to described the first switching type capacitor integrator 50 and described the second feedback signal to described the second switching type capacitor integrator 60; And described mode assembly 190, be coupled to the input of described the first switching type capacitor integrator 50 and the output of described the second switching type capacitor integrator 60, be used for providing the action of mode signal to control described the first switching type capacitor integrator 50 and the action of described the second switching type capacitor integrator 60.
Described feedback circuit 170 comprises 116～119,156～159 and two capacitors 112,152 of 172, nine suitching type assemblies of the first digital to analog converter (DAC) 171, the second digital to analog converters (DAC).Described the first digital to analog converter 171 has first end and is coupled to the output of described quantizer 70 and the input that the second end is coupled to described the first switching type capacitor integrator 50, see through described suitching type assembly 116～119 and described capacitor 112, be used for providing described the first feedback signal to described the first switching type capacitor integrator 50.
Described the second digital to analog converter 172 has first end and is coupled to the input that described quantizer 70 outputs and the second end are coupled to described the second switching type capacitor integrator 60, see through described suitching type assembly 156～159 and described capacitor 152, be used for providing described the second feedback signal to described the second switching type capacitor integrator 60.
Described suitching type assembly 116 has output and the second end that first end is coupled to described the first digital to analog converter 171.Described suitching type assembly 117 has the second end and the second end that first end is coupled to described suitching type assembly 116 and is coupled to ground connection.Described capacitor 112 has first end and the second end that first end is coupled to this suitching type assembly 117.Described suitching type assembly 118 has the second end and the second end that first end is coupled to described capacitor 112 and is coupled to ground connection.Described suitching type assembly 119 has first end and is coupled to the second end of described capacitor 112 and the output that the second end is coupled to the full differential operation amplifier 110 of described bimodal δ-Δ analog-to-digital converter 50.Described suitching type assembly 156 has output and the second end that first end is coupled to described the second digital to analog converter 172.Described suitching type assembly 157 has the second end and the second end that first end is coupled to described suitching type assembly 156 and is coupled to ground connection.Described capacitor 152 has first end and the second end that first end is coupled to described suitching type assembly 157.Described suitching type assembly 158 has the second end and the second end that first end is coupled to described capacitor 152 and is coupled to ground connection.Described suitching type assembly 159 has first end and is coupled to the second end of described capacitor 152 and the output that the second end is coupled to the full differential operation amplifier 150 of described bimodal δ-Δ analog-to-digital converter 60.
Described mode assembly 190 comprises three suitching type assemblies 132～134,115, four suitching type assemblies 128～131 of capacitor and two inverters 191～192.Described suitching type assembly 132 has the output that first end is coupled to described the first switching type capacitor integrator 50 and sees through plurality of capacitors group 113 and four suitching type assemblies 120～123, and the input that the second end is coupled to described the first switching type capacitor integrator 50 sees through plurality of capacitors group 114 and four suitching type assemblies 124～127.Described suitching type assembly 133 has input and the second end that first end is coupled to described the first switching type capacitor integrator 50.Described suitching type assembly 134 assemblies have first end and the second end.Described inverter 191 has input and the second end that first end is coupled to described the second switching type capacitor integrator 60 and is coupled to described suitching type assembly 134.Described inverter 192 has that first end is coupled to described suitching type assembly 132 assemblies and the second end is coupled to described suitching type assembly 133,134.Described suitching type assembly 128 has first end and is coupled to described suitching type assembly 134 assemblies and the second end.Described suitching type assembly 129 has the second end and the second end that first end is coupled to described suitching type assembly 128.Described capacitor 115 has the second end and the second end that first end is coupled to described suitching type assembly 129.Described suitching type assembly 130 has the second end and the second end that first end is coupled to described capacitor 115 and is coupled to ground connection.Described suitching type assembly 131 has first end and is coupled to the second end of described capacitor 152 and the second end that the second end is coupled to described suitching type assembly 133.Described the first suitching type assembly 132 of described mode assembly 190 controls, described the second suitching type assembly 133 and described the 3rd suitching type assembly 134 state to determine to open or close.
Described the first switching type capacitor integrator 50 comprises full differential operation amplifier 110,120～123,124～127 and two capacitors 113,114 of 111, eight suitching type assemblies of capacitor.
Described full differential operation amplifier 110 has the second suitching type assembly the 119,133, second end that first input end is coupled to described mode assembly and is coupled to ground connection and output.Described the first capacitor 111 has the first end that first end is coupled to the described full differential operation amplifier 110 of described the first switching type capacitor integrator 50, and the second end is coupled to the output of the described full differential operation amplifier 110 of described the first switching type capacitor integrator 50.
Described suitching type assembly 120 has first end and the second end that first end is coupled to described suitching type assembly 102.Described suitching type assembly 121 has the second end and the second end that first end is coupled to described suitching type assembly 120.Described capacitor 113 has the second end and one second end that first end is coupled to described suitching type assembly 113.Described suitching type assembly 114 has the second end and the second end that first end is coupled to described capacitor 113 and is coupled to ground connection.Described suitching type assembly 123 has first end and is coupled to the second end of described capacitor 113 and the first output that the second end is coupled to described full differential operation amplifier 110.
Described suitching type assembly 124 has the second end and the second end that first end is coupled to described suitching type assembly 102.Described suitching type assembly 125 has the second end and the second end that first end is coupled to described suitching type assembly 124.That suitching type assembly 114 has the second end and the second end that first end is coupled to described suitching type assembly 125.Described suitching type assembly 126 has the second end and the second end that first end is coupled to described capacitor 114 and is coupled to ground connection.Described suitching type assembly 127 has first end and is coupled to the second end of described capacitor 114 and the first output that the second end is coupled to described full differential operation amplifier 110.
Described the second switching type capacitor integrator 60 comprises full differential operation amplifier 150,151, four suitching type switches 160～163 of capacitor and capacitor 153.
Described differential minute operational amplifier 150 has first input end and is coupled to described suitching type assembly the 159,163, second input and is coupled to ground connection and output.Described capacitor 151 has first end and is coupled to the first output of described the second switching type capacitor integrator 60 described full differential operation amplifiers 150 and the input of described quantizer 70.
Described suitching type assembly 160 has the first output and the second end that first end is coupled to described full differential operation amplifier 110.Described suitching type assembly 161 has the second end and the second end that first end is coupled to described suitching type assembly 160.Described capacitor 153 has the second end and the second end that first end is coupled to described suitching type assembly 161.Described suitching type assembly 162 has the second end and the second end that first end is coupled to described capacitor 153 and is coupled to ground connection.Described suitching type assembly 163 has first end and is coupled to the second end of described capacitor 153 and the first output that the second end is coupled to described full differential operation amplifier 150.
According to the present invention, dual input AIN and BIN node provide in transmission signal to described bimodal δ-Δ analog-to-digital converter 100 and other comes from described mode assembly 190 input mode (MODE) signals to determine described bimodal δ-Δ analog-to-digital converter 100 is as which kind of state.When the mode signal equals 0, this bimodal δ-Δ analog-to-digital converter 100 operates in nearly zero intermediate frequency (NZIF) mode; When the mode signal equals 1, this bimodal δ-Δ analog-to-digital converter 100 operates in Low Medium Frequency mode (low IF).
As shown in Figure 3, be the calcspar of the receiver circuit 200 of the bimodal δ that operates in nearly zero intermediate frequency-Δ analog-to-digital converter.This radio frequency receiver framework is widely used in now.Described receiver circuit 200 comprises low noise amplifier 210; Frequency synthesizer 240; The first frequency mixer 220; The second frequency mixer 221; Low pass filter 231, the first bimodals δ-Δ analog-to-digital converter 100 and the second bimodal δ-Δ analog-to-digital converter 100.Should be noted, although described mode assembly 190 is in bimodal δ-Δ analog-to-digital converter 100, for clear this receiver circuit 200 of expressing, this mode assembly 190 is independently shown in the drawings.
This low noise amplifier (LNA) 210 amplifies received weak signals, and this signal is followed the interference that exceeds frequency band by low pass filter (LPF) 230 filterings then by 220,221 stages of frequency mixer.Described frequency synthesizer 240 have the first output with provide the first signal to described frequency mixer 220 and the second output to provide the second signal to described frequency mixer 221.Described frequency mixer 220 has the output that first input end is coupled to described low noise amplifier 210, and the second input is coupled to first input end and the output of described frequency synthesizer 240.Described the second frequency mixer 221 has the output that first input end is coupled to described low noise amplifier 210, and the second input is coupled to described frequency synthesizer 24 second inputs, and output.Described low pass filter 230 has the output that first input end is coupled to described the first frequency mixer 220, one second output is coupled to the output of the second frequency mixer 221, and the first output is coupled to the first bimodal δ-Δ analog-to-digital converter 100 (upper) and the second output is coupled to one second bimodal δ-Δ analog-to-digital converter 100 (lower).Input node " AIN " from the frequency reducing I of this low pass filter (LPF) 230 and Q signal transmission to this and reach " BIN ", and individual other by analog-to-digital converter 100, yet only need input " AIN " node this moment.Two digital to analog converters (being positioned at Fig. 3 below) are identical herein, and namely a digital to analog converter carries out the I signal and another digital to analog converter carries out the Q signal.
As shown in Figure 4, operate in the signal flow graph of nearly zero intermediate frequency for described bimodal δ-Δ analog-to-digital converter 100.When the mode signal of described mode assembly 190 equals zero, this moment, described δ-Δ analog-to-digital converter 100 operated in nearly zero intermediate frequency (NZIF) mode, described suitching type assembly 133,134 should be closed (off), reaching this upper strata feedback path should be opened circuit, as shown in Figure 4, and simultaneously, described suitching type assembly 132 should be opened (on), and input signal AIN equals BIN.So when the signal feed-in, we can use its input node.Under this framework, this δ-Δ analog-to-digital converter 100 has its dead-center position of high pass noise transfer function and is seated on the original frequency.
As shown in Figure 5, be the calcspar of the receiver circuit 201 of the bimodal δ that operates in Low Medium Frequency-Δ analog-to-digital converter.Same receiver architecture comprises described low noise amplifier 210 and described frequency mixer 220,221 but is linked to band pass filter (BPF) 232 and bimodal δ of the present invention-Δ analog-to-digital converter 100.Should be noted, although this mode assembly 190 is in bimodal δ-Δ analog-to-digital converter 100, for clear this receiver circuit 200 of expressing, this mode assembly 190 is independently shown in the drawings.
Described frequency synthesizer 240 have first input end with provide the first signal to described frequency mixer 220 and the second output to provide the second signal to described frequency mixer 221.Described the first frequency mixer 220 has the output that first input end is coupled to described low noise amplifier 210, and the second input is coupled to first input end and an output of described synthesizer 240.Described the second frequency mixer 221 has the output that first input end is coupled to described low noise amplifier 210, and the second input is coupled to the second output and the output of described synthesizer 240.Described band pass filter 232 has the be coupled output of described the first frequency mixer 220 of first input end, the second input is coupled to described the second frequency mixer 221 outputs, and the first output is coupled to the first bimodal δ-Δ analog-to-digital converter 100 (above the 5th figure) and the second output is coupled to the second bimodal δ-Δ analog-to-digital converter 100 (below the 5th figure).
Frequency reducing signal before described band pass filter 232 perhaps has interfering energy and can be by this second bimodal δ-Δ analog-to-digital converter 100 (below the 5th figure) institute decipher.Described the second bimodal δ-Δ digital to analog converter 100 has this detecting with the monitor interference signal, in case this signal is excessive and exceed the range of linearity of this band pass filter 232, will remind this low noise amplifier 210 to reduce gain to avoid interference saturated this band pass filter of signal (BPF) 232.At this moment, the one δ-Δ analog-to-digital converter 100 (upper) should receive from band pass filter (BPF) 232 usual I and Q path by the signal of frequency reducing, then translate into the digital character code (Data stream) of data, read by the fundamental frequency processor.That is, even this first bimodal δ-Δ analog-to-digital converter 100 (upper) and the second bimodal δ-Δ analog-to-digital converter 100 (lower) are the same assembly, they receive different signals, when mode (MODE) signal of this mode assembly 190 equal 1 and this bimodal δ-Δ analog-to-digital converter 100 operate in Low Medium Frequency mode.
As shown in Figure 6, operate in the signal flow graph of Low Medium Frequency for bimodal δ-Δ analog-to-digital converter 100.When these mode assembly 190 mode signals equal 1 and this bimodal δ-Δ analog-to-digital converter 100 operate in Low Medium Frequency mode, this suitching type assembly 133,134 should be opened (on) and this suitching type assembly should be closed (off) 132 this moments, as shown in Figure 6.This upper strata feedback path links now, this moment δ-Δ analog-to-digital converter 100 have a high pass noise transfer function wherein this dead-center position fall within intermediate frequency." AIN " reaches the indivedual signals of " BIN " node processing and utilizes this switching type capacitor operation so that input signal is summed into such as " AIN+BIN " under this framework.
Although the present invention is open with aforementioned preferred embodiment, so it is not to limit the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention, and when making various changes or modifications.Explanation described above can be done correction and the variation of each pattern, and can not destroy the spirit of this creation.Therefore protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Claims (14)
1. bimodal δ-Δ analog-to-digital converter is characterized in that, comprises:
The first switching capacitance integrator is used for input signal and the first feedback signal are carried out integral operation;
The second switching capacitance integrator is coupled to described the first switching type capacitor integrator, is used for output signal and the second feedback signal of described the first switching type capacitor integrator are carried out integral operation;
Quantizer has input to be coupled to described the second switching type capacitor integrator and output, is used for providing the output signal of described digital quantizer, has first and second logical states at least, corresponding to the output to the second switching type capacitor integrator;
Feedback circuit, be coupled to described the first switching type capacitor integrator and described the second switching type capacitor integrator, be used for providing described the first feedback signal to described the first switching type capacitor integrator and described the second feedback signal to described the second switching type capacitor integrator; And
The mode assembly, be coupled to the input of described the first switching type capacitor integrator and the output of described the second switching type capacitor integrator, be used for providing the action of mode signal to control described the first switching type capacitor integrator and the action of described the second switching type capacitor integrator.
2. bimodal δ according to claim 1-Δ analog-to-digital converter is characterized in that, described feedback circuit comprises:
The first digital to analog converter is coupled to the input of described the first switching type capacitor integrator, is used for providing described the first feedback signal to described the first switching type capacitor integrator; And
The second digital to analog converter is coupled to the input of described the second switching type capacitor integrator, is used for providing described the second feedback signal to described the second switching type capacitor integrator.
3. bimodal δ according to claim 1-Δ analog-to-digital converter is characterized in that, described mode assembly comprises:
The first suitching type assembly has first end and is coupled to the input of described the first switching type capacitor integrator and the input that the second end is coupled to described the second switching type capacitor integrator;
The second suitching type assembly has input and the second end that first end is coupled to described the first switching type capacitor integrator; And
The 3rd suitching type assembly has first end and is coupled to second end of the second suitching type assembly of described mode assembly and the output that one second end is coupled to described the second switching type capacitor integrator;
Wherein said mode assembly is controlled described the first suitching type assembly, and described the second suitching type assembly and described the 3rd suitching type assembly are the states that opens or closes to determine.
4. bimodal δ according to claim 3-Δ analog-to-digital converter is characterized in that, between described the second suitching type assembly and the 3rd suitching type assembly, described mode also comprises:
The 4th suitching type assembly has the second end points and the second end points that first end is coupled to described the 3rd suitching type assembly; And
The 5th suitching type assembly has the second end points and the second end points that first end is coupled to described the 4th suitching type assembly and is coupled to ground connection;
The first electric capacity has first end and the second end that first end is coupled to described the 5th suitching type assembly;
The 6th suitching type assembly has described the second end and the second end that first end is coupled to described the first electric capacity and is coupled to ground connection; And
The 7th suitching type assembly has first end and is coupled to the first end of described the 6th suitching type assembly and the second end that the second end is coupled to described the second suitching type assembly.
5. described bimodal δ according to claim 1-Δ analog-to-digital converter is characterized in that, described the first switching type capacitor integrator comprises:
Full differential operation amplifier has the described first end that first input end is coupled to the second suitching type assembly of described mode assembly; And
The first electric capacity has the described first end that first end is coupled to the full differential operation amplifier of described the first switching type capacitor integrator, and the second end is coupled to the output of the full differential operation amplifier of described the first switching type capacitor integrator.
6. bimodal δ according to claim 5-Δ analog-to-digital converter is characterized in that, described the first switching type capacitor integrator also comprises:
The first suitching type assembly has first end and the second end that first end is coupled to described the first suitching type assembly;
The second switching type capacitor assembly has the second end and the second end that first end is coupled to described the first suitching type assembly and is coupled to ground connection;
The second electric capacity has first end and the second end that first end is coupled to described the second suitching type assembly;
The 3rd suitching type assembly has the second end and the second end that first end is coupled to described the second electric capacity and is coupled to ground connection;
The 4th suitching type assembly has first end and is coupled to the second end of described the 3rd suitching type assembly and the input that the second end is coupled to the full differential operation amplifier of described the first switching type capacitor integrator;
The 5th suitching type assembly has the second end and the second end that first end is coupled to described the first suitching type assembly;
The 6th suitching type assembly has first end and is coupled to the second end and the second end that described the 5th suitching type unit does and is coupled to ground connection;
The 3rd electric capacity has the second end and the second end that first end is coupled to described the 6th suitching type assembly;
The 7th suitching type assembly has the second end and the second end that first end is coupled to described the 3rd electric capacity and is coupled to ground connection;
The 8th suitching type assembly has first end and is bonded to the second end of described the 7th suitching type assembly and the input that the second end is coupled to the full differential operation amplifier of described the first switching type capacitor integrator.
7. described bimodal δ according to claim 1-Δ analog-to-digital converter, wherein said the second switching type capacitor integrator comprises:
Full differential operation amplifier has first input end, and the second input is coupled to the output that ground connection and output are coupled to described quantizer; And
The first electric capacity has the first input end that first end is coupled to the full differential operation amplifier of described the second switching type capacitor integrator, and the second end is coupled to the output of described full differential operation amplifier.
8. bimodal δ according to claim 7-Δ analog-to-digital converter is characterized in that, described the second switching type capacitor integrator also comprises:
The first suitching type assembly has first end and the second end that first end is coupled to described full differential operation amplifier;
The second suitching type assembly has the second end and the second end that first end is coupled to described the first suitching type assembly and is coupled to ground connection;
The second electric capacity has first end and the second end that first end is coupled to described the second suitching type assembly;
The 3rd suitching type assembly has the second end and the second end that first end is coupled to described the second electric capacity and is coupled to ground connection;
The 4th suitching type assembly has first end and is coupled to described second end of described the 3rd suitching type assembly and the input that the second end is coupled to the full differential operation amplifier of described the second switching type capacitor integrator.
9. bimodal δ according to claim 3-Δ analog-to-digital converter, it is characterized in that, the first suitching type switch between components of described mode assembly is to opening, the second suitching type assembly and the 3rd suitching type assembly of described mode assembly will switch to the pass, be used for making described bimodal δ-Δ analog-to-digital converter operate in nearly zero intermediate frequency mode.
10. bimodal δ according to claim 3-Δ analog-to-digital converter, it is characterized in that, the first suitching type switch between components of described mode assembly is to closing, the second suitching type assembly of described mode assembly and described the 3rd suitching type switch between components are used for making described bimodal δ-Δ analog-to-digital converter operate in Low Medium Frequency to opening.
11. a bimodal δ-Δ simulation is to the receiver circuit of digital circuit, comprise two bimodal δ-Δ analog-to-digital converters as claimed in claim 1, be the first bimodal δ-Δ analog-to-digital converter and the second bimodal δ-Δ analog-to-digital converter, it is characterized in that, comprise:
Low noise amplifier has output;
Frequency synthesizer has the first output, is used for providing the first signal and the second output to be used for providing the second output signal;
The first frequency mixer has the output that the first output is coupled to described low noise amplifier, and the second input is coupled to the first output of described frequency synthesizer, and output;
The second frequency mixer has the output that the first output is coupled to described low noise amplifier, and the second input is coupled to the second input of described frequency synthesizer, and output;
Low pass filter, have first input end and be coupled to the output of the first frequency mixer, the second input is coupled to the output of the second frequency mixer, and the first output is coupled to the first bimodal δ claimed in claim 1-Δ analog-to-digital converter and the second output is coupled to the second bimodal δ claimed in claim 1-Δ analog-to-digital converter.
12. bimodal δ according to claim 11-Δ simulation is to the receiver circuit of numeral, it is characterized in that, the first suitching type switch between components of the described mode assembly of described the first bimodal δ-Δ analog-to-digital converter and described the second bimodal δ-Δ analog-to-digital converter is to opening, the second suitching type assembly and the 3rd suitching type assembly of the described mode assembly of described the first bimodal δ-Δ analog-to-digital converter and described the second bimodal δ-Δ analog-to-digital converter will switch to the pass, be used for making described the first bimodal δ-Δ analog-to-digital converter and described the second bimodal δ-Δ analog-to-digital converter operate in nearly zero intermediate frequency mode.
13. a bimodal δ-Δ simulation is characterized in that the receiver circuit of digital circuit, comprises:
Low noise amplifier has output;
Frequency synthesizer has the first output, is used for providing the first signal to reach and is used for providing the second output the second output signal;
The first frequency mixer has the output that the first output is coupled to described low noise amplifier, and the second input is coupled to the first output of described frequency synthesizer, and output;
The second frequency mixer has the output that the first output is coupled to described low noise amplifier, and the second input is coupled to the second input of described frequency synthesizer, and output;
Bypass filter, have first input end and be coupled to the output of the first frequency mixer, the second input is coupled to the output of the second frequency mixer, and the first output is coupled to the first bimodal δ claimed in claim 1-Δ analog-to-digital converter and the second output is coupled to the second bimodal δ claimed in claim 1-Δ analog-to-digital converter.
14. bimodal δ according to claim 13-Δ simulation is to the receiver circuit of numeral, it is characterized in that, the first suitching type switch between components of the mode assembly of described the first bimodal δ-Δ analog-to-digital converter and described the second bimodal δ-Δ analog-to-digital converter extremely, the second suitching type assembly of the mode assembly of described the first bimodal δ-Δ analog-to-digital converter and described the second bimodal δ-Δ analog-to-digital converter and the 3rd suitching type switch between components are to opening, so that described the first bimodal δ-Δ analog-to-digital converter and described the second bimodal δ-Δ analog-to-digital converter operate in Low Medium Frequency mode.
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| TW100136372 | 2011-10-06 | ||
| TW100136372A TWI477086B (en) | 2011-10-06 | 2011-10-06 | A dual mode sigma delta analog to digital converter and circuit using the same |
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Cited By (2)
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| CN104282700A (en) * | 2013-07-12 | 2015-01-14 | 全视科技有限公司 | Image sensor and operating method thereof |
| CN105007069A (en) * | 2015-06-26 | 2015-10-28 | 深圳市芯海科技有限公司 | Digital to analog converter and multiplexer for capacitance detection |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI513182B (en) * | 2013-06-19 | 2015-12-11 | Coretex Technology Corp | Switched capacitor filter device and filtering method thereof |
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| Publication number | Publication date |
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| TW201316698A (en) | 2013-04-16 |
| CN103036571B (en) | 2016-01-20 |
| TWI477086B (en) | 2015-03-11 |
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