CN103027707A - Method and system used for achieving ultrasound digital scanning conversion based on dynamic random access memory (DRAM) - Google Patents
Method and system used for achieving ultrasound digital scanning conversion based on dynamic random access memory (DRAM) Download PDFInfo
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Abstract
The invention discloses a method and a system used for achieving ultrasound digital scanning conversion based on a dynamic random access memory (DRAM). According to the method for achieving the ultrasound digital scanning conversion based on the DRAM, a plurality of line caches are arranged in the DRAM inside a dynamic stability control (DSC) system, each line cache is used for caching a part of a scanning line in a frame scanning image, each time the scanning image needed to be displayed in a frame corresponding image display unit is stored in the DRAM with the scanning line as a unit, echo data corresponding to the same scanning line are stored in registers which are in the same line but have different addresses, with the scanning line as the unit, N echo data in each scanning line are read out from the DRAM by line by line and step by step each time, then the N echo data read out by each scanning line are stored in each internal line cache, coordinate conversion and interpolation algorithm are carried out on each pixel according to the display sequence of display images, and the grey value of each pixel in the display images is calculated. The method and the system used for achieving the ultrasound digital scanning conversion based on the DRAM have the advantages of being low in achieving cost, and high in reliability.
Description
Technical field
The present invention relates to a kind of ultrasonic Digital Signal Processing, especially relate to a kind of method and system that realize ultrasonic digital scan conversion based on dynamic RAM (DRAM).
Background technology
In the medical ultrasound imaging system, the echo information of scanning end need to be converted into the image of display end, for professional's observation and diagnosis, the process that this image transforms is called digital scan conversion, be called for short DSC (Digital Scan Converter), the DSC technology conveniently has very important effect in the raising image quality, has become a key technology in the present medical ultrasound imaging, has broad application prospects.
The core of DSC technology is that coordinate take display space image vegetarian refreshments is as the source, through a series of coordinate transform, obtain the original coordinates of point in scanogram of its correspondence, utilize original coordinates or 4 points (getting adjacent horizontal and vertical each 2 point after when the coordinate transform result is decimal, rounding) around it, adopt the algorithm of linear interpolation, obtain the value of display pixel.
The DSC technology will realize by the conversion to the display end image of the echo data of scanning end, need first the view picture of scanning end (frame) scanogram buffer memory, according to the result of display end coordinate transform, from the scanning end data buffer storage, take out corresponding numerical value and carry out interpolation operation again.
The DSC computing needs line by line computing just can obtain the complete displayed map picture of a width of cloth (frame), for example suppose that the size of viewing area is 800*600 (pixel), so every two field picture then needs to carry out the DSC computing of 480000 pixels, if real-time DSC, because the frame per second of medical ultrasound Real Time Image System all about tens frame/seconds, can be calculated usually, its operand is larger, need to get 4 value because major part is put the DSC computing simultaneously, so the operational ton of buffer memory is just larger.If consider the bandwidth that also needs buffer memory front end scanogram, be one of place of throughput maximum during whole DSC processes to the operation of buffer memory so.
Because these characteristics of DSC technology cause the DSC technology in realization, be faced with big data quantity, large data throughput, high performance requirement.In the current medical ultrasound equipment, the realization of DSC has software to realize and hardware is realized two large schemes, and wherein software adopts the CPU computing, the mode of DDR2/3 storage, and hardware plan then is the scheme of FPGA+SRAM, FPGA control and computing, SRAM storage.
In existing DSC implementation, wherein software implement scheme utilizes the stronger operational capability of CPU to carry out the computing of DSC, characteristics are to realize flexibly, but because the super large that DSC needs and lasting operand, a very large expense to software, cause easily software system to process the other problems scarce capacity, and further cause the unstable of system, and because the macrooperation amount of DSC, add other demands of ultrasonic image-forming system to the expense of software, cost when causing the CPU type selecting has greater impact, uses certain limitation.
In existing hardware implementations, be in the scheme of FPGA+SRAM, control and computing with FPGA, SRAM realizes storage, this implementation is within one quite long period, satisfied market demand, but the further intensification and the new storage scheme that are accompanied by the market competition are the appearance of control mode, and the needs of system extension etc., this scheme of FPGA+SRAM has shown inferior position in all fields: at first its cost relative dynamic is stored the scheme of (DDR2/3 or SDRAM below are referred to as DDR) at random, under the same capacity conditions, exceeded more than 10 times; Secondly, the low capacity of SRAM makes it almost just satisfy the requirement of DSC storage, if there are other storage needs in system, also needs to add in addition memory device, and autgmentability is relatively poor; Again, SRAM throughput wretched insufficiency can't be tackled day by day the more highdensity image that improves, larger frame per second, the processing demands of high bandwidth more.
Summary of the invention
For solve exist in the existing DSC implementation data operation quantity large, to the more high many defectives of system requirements, the present invention proposes a kind of based on dynamic RAM, use minimum cost price, the most simple and practical mode realizes the method and system of ultrasonic digital scan conversion.
The present invention adopts following technical scheme to realize: a kind ofly realize the method for ultrasonic digital scan conversion based on DRAM, it comprises:
Several line buffer memorys are set in the internal RAM of DSC system;
The scanogram that at every turn a frame correspondence image display unit need to be shown is take scanning line as the unit buffer memory to DRAM, and echo data corresponding to same scanning line deposits in the same delegation among the DRAM;
Take scanning line as unit, progressively from DRAM, read N echo data of each scanning line by line at every turn, N the echo data of respectively each scanning line being read deposits in each line buffer memory;
DISPLAY ORDER according to the displayed map picture carries out coordinate transform to each pixel, obtain the absolute address` of each pixel correspondence in scanogram in the displayed map picture, according to finding corresponding echo data to advance interpolation operation in the absolute address` inline cache, calculate the gray value of each pixel in the displayed map picture.
Wherein, absolute address` comprises the line address that is determined by azimuth angle theta and the dot address that is determined by utmost point footpath R, and the direct conduct in line address is the index address of collinear buffer memory not, and dot address is then as the some index address in the line buffer memory.
Wherein, the storage depth of each line buffer memory is 8.
Wherein, the DSC system is realized that by fpga chip described several line buffer settings are in the RAM of fpga chip inside, and DRAM is connected to the fpga chip outside.
In addition, the present invention discloses and a kind ofly realizes the system of ultrasonic digital scan conversion based on DRAM, and it comprises: RAM, DRAM, coordinate transformation unit and interpolating unit; Several line buffer memorys are set in RAM; Each scanogram that a frame correspondence image display unit need to be shown is that unit carries out buffer memory by scanning line, and echo data corresponding to same scanning line deposits in the same delegation among the DRAM; Take scanning line as unit, from DRAM, read N echo data of each scanning line by line at every turn, N the echo data of respectively each scanning line being read deposits in the line buffer memory; According to the DISPLAY ORDER of displayed map picture each pixel is carried out coordinate transform by coordinate transformation unit, obtain the absolute address` of each pixel correspondence in scanogram in the displayed map picture; In the line buffer memory of RAM, find corresponding echo data to advance interpolation operation by interpolating unit according to absolute address`, calculate the gray value of each pixel in the displayed map picture.
Compared with prior art, the present invention has following beneficial effect:
The present invention adopts has cheaply DRAM realization DSC system, it is original below 10% in the storage link system cost to be reduced to, and data processing amount reduction, systematic function and reliability have been improved, and the large capacity of DRAM and high bandwidth make its remaining capacity can also be used for other and process, and have improved the extensibility of system.
Description of drawings
Fig. 1 is the structural representation that the present invention proposes the DSC system;
Fig. 2 is the sketch map of digital scan conversion in the preferred embodiment.
The specific embodiment
As shown in Figure 1, the structural representation of the ultrasonic digital scan conversion system (or being called the DSC system) of the present invention's proposition.
The DSC system that the present invention proposes is the implementation that adopts FPGA+ DRAM at hardware, utilize DRAM(Dynamic Random Access Memory, dynamic random access memory) large capacity, high bandwidth and auxiliary FPGA(Field-Programmable Gate Array, i.e. field programmable gate array of advantage cheaply) realize the DSC system.
The RAM(of FPGA inside is SRAM, cost is higher) as the inner buffer of DSC system, and be arranged on the DRAM of FPGA outside as the external cache of DSC system, and DRAM cooperates realization DSC system to the processing of ultrasonic digital scan conversion with the RAM of FPGA inside.
The DSC system is in ultrasonic system after the Digital Signal Processing, before the display driver.The DSC system comprises: image data memory cell, interpolating unit, coordinate transformation unit (take protruding gust changes in coordinates as example, the probe processing mode of other types is similar), image-display units, cooperation image data memory cell realize the dynamic random access memory (DRAM) of digital scan conversion.
During the DSC system works, by coordinate transformation unit the upper pixel address that adopts rectangular coordinate (x, y) of image-display units (such as display) is transformed into polar coordinate address (R, θ) in the image data memory cell.This coordinate transformation unit is divided into linear array scanning conversion, the scan conversion of protruding battle array and the conversion of M Mode scans etc. according to the difference of probe type and display mode, the no matter scan conversion of which kind of pattern, all be that a pixel from image-display units is with rectangular coordinate (x, y), be transformed to again the residing μ v coordinate of probe, be transformed at last polar coordinate address (R, θ).
By polar coordinate address (R, θ) can from image data memory cell, read the echo data of storage, but polar coordinate address (R, sampled value θ) and rectangular coordinate (x, y) pixel in does not generally overlap, so must calculate pixel value on the actual rectangular coordinate (x, y) through interpolation by the error (being fractional part) of the R that calculates, θ value.
In general, from rectangular coordinate (x, y) produce to being converted to polar coordinate address (R, θ) and error, calculate by bilinear interpolation, by a rectangular coordinate (x, y) address of pixel obtains image data memory cell with polar coordinate (R in, θ) 4 dot addresses of expression, and from 4 dot addresses of the polar coordinate (R, Theta) of image data memory cell expression, take out echo data, by interpolating unit the echo data of 4 dot addresses of taking out is carried out interpolation operation, calculate the gray value of the middle pixel of rectangular coordinate (x, y) in image-display units.
How obtain 4 dot addresses of polar coordinate (R, θ) expression and how carry out interpolation operation according to the echo data of 4 dot addresses by a rectangular coordinate (x, y) the address correspondence in the displayed map picture, be prior art.This case just has mentionedly for the expressed intact of technical scheme, but is not described in detail.
For example, in the coordinate transform of protruding battle array, image data memory cell obtains the address of the respective image data of image data memory cell, and then reads view data according to the footpath R of the utmost point after the coordinate transform and polar angle or azimuth angle theta.
Because a frame scan image of ultrasonic system forms (according to the different slightly differences of scanning density and sweep limits) by tens to the hundreds of scanning line usually, each scanning line forms (according to the degree of depth and pattern different slightly different) by hundreds of to several thousand points (pixel) again, and therefore a frame scan image is general horizontal by the hundreds of scanning line, vertically be made of the hundreds of pixel.
Take 256 scanning lines, 512 the scanogram of certain ultrasonic scanning pattern as example, further specify the process that realizes the DSC system based on dynamic RAM (DRAM), the scan pattern processing method of all the other degree of depth and density is similarly.
The viewing area of image-display units is generally 800*600,512*512 or 640*480 etc. in the ultrasonic system, this case is take the image display area of 512*512 as the example explanation, the size of image display area, do not affect the feasibility of implementation method of the present invention, between the different images size, be the operand difference of a frame scan image, other also zero difference.
In a frame displayed map picture, the order of image-display units displayed map picture can be line by line from left to right, vertical from top to bottom mode, simultaneously, the order of ultrasonic digital scan conversion also can be from right to left, from the bottom up or other mode, this case is with line by line from left to right, vertically from top to bottom mode describes, but the order that DSC processes does not affect realization of the present invention, and the present invention also has pair processing sequence to adjust the discussion of rear optimization process.
At first, realize with dynamic RAM (DRAM) core of DSC is how to improve the efficient of data-interface.Guarantee this point, each scanning line in the frame scan image need to be deposited respectively in the different row among the DRAM, and the pixel number that same scanning line is corresponding in the scanogram is according to the depositor of different addresses in the same delegation that deposits among the DRAM.This is because the opening and closing of DRAM delegation need the operation of more complicated, consuming time more, each element of action row the inside after if delegation opens then quite fast and convenient, but if read to operate again after a certain number in (or writing) delegation some unit of another row, just can insert during this and close lastrow, open the operation of next line, greatly reduce the efficient of DRAM, if the image of same line all is saved in same delegation among the DRAM in the scanogram, when reading several of image of a line so at every turn, just can once read more and duration that read is very short, greatly improve data-interface efficient and the operating efficiency of DRAM.Like this, can once read one section new data when needing to upgrade after the number in each inner wire buffer memory has been used up, be used for following one section calculating.
Secondly, set up 256 line buffer memorys in the random access memory (RAM) of FPGA inside, the quantity of line buffer memory is just relevant with the line number of present mode one frame scan image, not necessarily equates.Each line buffer memory degree of depth is 8 (also can be other values, relevant with image angle, image size etc., need be selected according to system's needs); The bit wide of each view data is decided according to system's needs, is assumed to be 8.Each bit wide line buffer memory not necessarily needs ram cells different among the corresponding FPGA, that is to say, 256 degree of depth are that 8 line buffer memory can be put among the RAM of same or several FPGA inside, certainly, also can use the distributed RAM of FPGA inside to realize.
Again, after DSC system start-up, take scanning line as unit, with a frame scan image by scanning line by line different rows from DRAM read each scanning line the 8(of shallow depth direction can change) individual value (being top 8 echo datas of each scanning line in the scanogram), deposit in above-mentioned 256 line buffer memorys.
Then, by coordinate transformation unit according to the DISPLAY ORDER of the displayed map picture rectangular coordinate (x to each pixel in the displayed map picture, y) carry out coordinate transform after, each pixel (x, y) obtained 4 addresses in the polar coordinate (R, θ), these 4 addresses are the absolute address` in the expression scanogram, absolute address` comprises two parts, i.e. line address (being determined by azimuth angle theta) and dot address (R determines by utmost point footpath).Wherein, the line address is directly as the index address of collinear buffer memory not; Dot address is then as the some index address in the line buffer memory.
At last, according to absolute address` addressing in the line buffer memory of RAM, find each pixel (x, y) corresponding to polar coordinate (R, 4 echo datas θ), by interpolating unit 4 echo datas that take out are carried out interpolation operation, calculate the gray value of the middle pixel of rectangular coordinate (x, y) in image-display units.The gray value that calculates carries out image at image-display units and shows.
In the process that reality is processed in real time, because display pixel movement from left to right, major embodiment for its coordinate line address of getting also corresponding generation variation, because display pixel movement from top to bottom, major embodiment is its corresponding changing in coordinate points address of getting, be saved in advance each line buffer memory among the RAM as long as guarantee the data that need to take out after the coordinate transform from DRAM, whole processing procedure just can be moved.
In the RAM of FPGA, because the inner buffer that each scanning line is corresponding is very little, total buffer memory that a frame scan image is corresponding also is no more than tens K bits (bit), with respect to the memory space of the inner several Mbit of FPGA, very little, very little on other design impacts of system.
Line buffer memory for each inner buffer scanning line, all need to process and whether the processing of last DSC system is judged the data of next time processing needs in the movement of depth direction and do not suffered at the little buffer memory in current inside according to current DSC system, if so, then start from external cache corresponding data are read into the action of upgrading in the inner little buffer memory.Because the moment of using this scanning line buffer memory is also in several processes pixel after the cycle next time, be used for changing that to obtain new scanning line data cached the time during this.
When display pixel carries out the DSC processing, the optimal way that also can adopt subregion to process, for example minute left and right region shown in Figure 2 is processed, at this moment, can take from top to bottom the zone in displayed map picture left side (empty vertical line left side) first, order is from left to right carried out coordinate transform, again the right is processed, when left side, processes and displays district, only can use the line data in left side in the original image like this, the buffer memory quantity of FPGA inside can be reduced into half of former scheme.
The displayed map picture pixel (square) among Fig. 2, coordinate after coordinate transform is certain point (square) in the original image, obtain the gray value of square dot, need to as Fig. 2 left side 1,2,3,4 totally 4 points carry out interpolation arithmetic, if so these 4 points are saved in same delegation among the DRAM (the different depositors with identical row address), also can greatly improve the efficient that reads.Also can adopt a kind of new access mode optimization to realize the DSC system, namely not only there is same delegation among the DRAM in the data of same line, and each point and near it 3 points stored simultaneously, then can take out simultaneously when reading, take this implementation, the mode that reads with respect to single-point, DRAM when in operating efficiency improved 4 times, this mode can realize that the DSC system is the same by similar SRAM, pointwise is carried out DSC and is changed, pointwise is read and is processed, and does not need the FPGA internal RAM to realize the line buffer memory of corresponding each scanning line, and only needs a very little inner buffer save data to get final product.The weak point of this mode is that each point is repeated to have preserved 4 times, and is higher to the occupancy of buffer memory, but consider that DRAM has the memory capacity of upper G, also is very little on the impact of the memory space about a width of cloth (frame) scanogram 1M.
To sum up, the present invention adopts has cheaply DRAM realization DSC system, it is original below 10% in the storage link system cost to be reduced to, and data processing amount reduction, systematic function and reliability have been improved, and the large capacity of DRAM and high bandwidth make its remaining capacity can also be used for other and process, and have improved the extensibility of system.
The above only is preferred embodiment of the present invention, not in order to limiting the present invention, all any modifications of doing within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (6)
1. method that realizes ultrasonic digital scan conversion based on DRAM is characterized in that described method comprises:
Several line buffer memorys are set in the internal RAM of DSC system;
The scanogram that at every turn a frame correspondence image display unit need to be shown is take scanning line as the unit buffer memory to DRAM, and echo data corresponding to same scanning line deposits in the same delegation among the DRAM;
Take scanning line as unit, progressively from DRAM, read N echo data of each scanning line by line at every turn, N the echo data of respectively each scanning line being read deposits in each line buffer memory;
DISPLAY ORDER according to the displayed map picture carries out coordinate transform to each pixel, obtain the absolute address` of each pixel correspondence in scanogram in the displayed map picture, according to finding corresponding echo data to advance interpolation operation in the absolute address` inline cache, calculate the gray value of each pixel in the displayed map picture.
2. the described method that realizes ultrasonic digital scan conversion based on DRAM according to claim 1, it is characterized in that, absolute address` comprises the line address that is determined by azimuth angle theta and the dot address that is determined by utmost point footpath R, the direct conduct in line address is the index address of collinear buffer memory not, and dot address is then as the some index address in the line buffer memory.
3. the described method that realizes ultrasonic digital scan conversion based on DRAM according to claim 1 it is characterized in that the DSC system is realized that by fpga chip described several line buffer settings are in the RAM of fpga chip inside, and DRAM is connected to the fpga chip outside.
4. a system that realizes ultrasonic digital scan conversion based on DRAM is characterized in that described system comprises: RAM, DRAM, coordinate transformation unit and interpolating unit; Several line buffer memorys are set in RAM; Each scanogram that a frame correspondence image display unit need to be shown is that unit carries out buffer memory by scanning line, and echo data corresponding to same scanning line deposits in the same delegation among the DRAM; Take scanning line as unit, progressively from DRAM, read N echo data in each scanning line by line at every turn, N the echo data of respectively each scanning line being read deposits in the line buffer memory; According to the DISPLAY ORDER of displayed map picture each pixel is carried out coordinate transform by coordinate transformation unit, obtain the absolute address` of each pixel correspondence in scanogram in the displayed map picture; In the line buffer memory of RAM, find corresponding echo data to advance interpolation operation by interpolating unit according to absolute address`, calculate the gray value of each pixel in the displayed map picture.
5. the described system that realizes ultrasonic digital scan conversion based on DRAM according to claim 4, it is characterized in that, absolute address` comprises the line address that is determined by azimuth angle theta and the dot address that is determined by utmost point footpath R, the direct conduct in line address is the index address of collinear buffer memory not, and dot address is then as the some index address in the line buffer memory.
6. the described method that realizes ultrasonic digital scan conversion based on DRAM according to claim 4 it is characterized in that described system is realized that by fpga chip described several line buffer settings are in the RAM of fpga chip inside, and DRAM is connected to the fpga chip outside.
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Application publication date: 20130410 |