CN102969876B - A kind of core control panel controlling 36 power cells - Google Patents
A kind of core control panel controlling 36 power cells Download PDFInfo
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- CN102969876B CN102969876B CN201210506064.XA CN201210506064A CN102969876B CN 102969876 B CN102969876 B CN 102969876B CN 201210506064 A CN201210506064 A CN 201210506064A CN 102969876 B CN102969876 B CN 102969876B
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Abstract
What the present invention designed is the core control panel scheme of a kind of current transformer, the cascade converter being no more than made up of 36 H bridge power units can be controlled, be mainly used in cascading silent oscillation reacance generator, cascaded high-voltage frequency converter, cascade connection type cophase supply power converter etc..The present invention program specifically includes that for producing 36 H bridge power unit control waves and receiving the fpga chip of power cell status signal, dsp chip for core control algolithm, for the CPLD chip with extraneous On-off signal, output and the communication connected, for receiving the operational amplifier A 1～A18 of analogue signal, for power supply chip IC1～IC4 for each chip power supply, for detecting the chip IC 5 of this circuit environment temperature and humidity, for preserving the chip EEPROM etc. of parameter.This circuit is stable, range is extensive.
Description
Technical field
What the present invention designed is the core control panel scheme of a kind of current transformer, and specific design is a kind of core control panel that can control the current transformer that no more than 36 power cells are constituted.
Background technology
Cascade converter is widely used in no more than 35kV high-pressure system, such as cascade connection type static reacance generator SVG, cascaded high-voltage frequency converter, cascade connection type cophase supply power converter etc..But, the core control circuit scheme controlling this kind of current transformer at present has the disadvantage in that
1, the card insertion type structure being typically made up of multiple boards, connector is many, and structure is complicated, and reliability is relatively low；
2, general employing bus type circuit structure, between board and board, circuit is longer, is not only vulnerable to crosstalk, also easily by external disturbance between bus；
3, board is adjacent with board, and be easily generated between board and board unit interferes；
4, in board is enclosed in cabinet, heat dispersion is poor；
5, the signal on board it is difficult to detection and measures, it is necessary to manufacturing and use custom-designed accessory to measure, adding difficulty to production detection；
6, plate card type control circuit, typically can only be for some concrete cascade converter, as: or it is the control circuit for cascade connection type static reacance generator SVG, it it is the control circuit for cascaded high-voltage frequency converter, it is the control circuit for cascade connection type cophase supply power converter, and each type current transformer above-mentioned can not be common to.
Summary of the invention
What the present invention designed is the core control circuit of a kind of current transformer, and this circuit can control the cascade converter being no more than made up of 36 H bridge power units.This type of cascade converter mainly can be widely applied to cascade on the equipment such as silent oscillation reacance generator, cascaded high-voltage frequency converter, cascade connection type cophase supply power converter.
The present invention is achieved in that a kind of core control panel controlling 36 power cells, mainly processed dsp chip by general on-site programmable gate array FPGA chip, 3 general-purpose digital signal, wherein 1 DSP1 for core control algolithm, its external memory RAM 1；Optionally with the DSP2 calculated in auxiliary, its external memory RAM 2；nullFor this circuit and the extraneous DSP3 coordinating and controlling，Its external memory RAM 3、General complex programmable logic device (CPLD) chip、General-purpose operation amplifier A1～A18、General power supply chip IC1～IC4、General detection temperature humidity chip IC 5、For preserving the general-purpose chip EEPROM of parameter、Pulse width modulation (PWM) mouth、Input and output I/O port composition，It is characterized in that: if with PWM mouth as top on device layout，The lower section of so PWM mouth is FPGA，The lower section of FPGA is DSP1，The lower section of DSP1 is DSP3，The lower section of DSP3 is I/O port，The right of DSP1 is DSP2，The top of DSP2 is RAM2，The upper left side of DSP1 is RAM1，The left of DSP3 is CPLD，The top of CPLD is RAM3，The back of DSP3 is EEPROM,The left of FPGA is IC1、IC2、IC3、IC4，Left side between RAM1 and RAM3 is IC5，The lower section of DSP2 is operational amplifier A 1～A18，I/O port is in bottom；nullIn circuit theory, PWM mouth is connected with the FPGA signal of telecommunication，RAM1 with the DSP1 signal of telecommunication is connected，RAM2 with the DSP2 signal of telecommunication is connected，RAM1、DSP1、RAM2、DSP2 is connected with the FPGA signal of telecommunication respectively，RAM3 with the DSP3 signal of telecommunication is connected，DSP3 is connected with DSP1 and the DSP2 signal of telecommunication respectively，CPLD respectively with DSP1、DSP2、DSP3、RAM3、The I/O port signal of telecommunication connects，General-purpose operation amplifier A1～A18 respectively with DSP1、DSP2、DSP3、The I/O port signal of telecommunication connects，Multiple power source chip IC 1～IC4 is connected with the I/O port signal of telecommunication，And the power supply of different voltage is provided for each device，General-purpose chip IC5 and DSP3、EEPROM、The I/O port signal of telecommunication connects.
The present invention also has a techniques below feature:
1, the chip that described FPGA uses is EP3C16240C8N type.
2, described DSP1, DSP2, DSP3 uses the TMS320x28x family device of TI company.
3, the chip that described CPLD uses is EPM1270T144C5 type.
This circuit is stable, range is extensive.
Accompanying drawing explanation
Fig. 1 is the components' placement arrangement figure of the present invention
Fig. 2 is the electrical principle block diagram of the present invention
Detailed description of the invention
The present invention is described in further detail with specific embodiment below in conjunction with the accompanying drawings:
As shown in Figure 1, a kind of core control panel controlling 36 power cells, mainly processed dsp chip by for 36 H bridge power unit control waves of generation and the reception general in-situ programmable gate array FPGA chip of power cell status signal, 3 general-purpose digital signal, wherein 1 DSP1 for core control algolithm, its external memory RAM 1；Optionally with the DSP2 calculated in auxiliary, its external memory RAM 2；For this circuit and the extraneous DSP3 coordinating and controlling, its external memory RAM 3, for connecting the general complex programmable logic device (CPLD) chip of On-off signal, output and communication between this circuit and the external world, for receiving general-purpose operation amplifier A1～A18 of analogue signal, for for the multiple power source chip IC 1～IC4 of each chip power supply, for detecting the general-purpose chip IC5 of this circuit environment temperature and humidity, for preserving the compositions such as the chip EEPROM of parameter.
1, power supply implementation
As shown in Figure 2, multiple power source chip IC 1～IC4 of the present invention internally provides+5V digital power and ± 5V analog power by its I/O port, + 5V digital power constitutes power circuit voltage stabilizing output 1.2V, 1.9V, 2.5V, 3.3V voltage through IC1, IC2, IC3, IC4, thering is provided power supply for the circuit such as FPGA, DSP1～DSP3, CPLD, RAM1～RAM3, ± 5V analog power is directly fed to operational amplifier A 1～A18.
2, I/O port signal
As shown in Figure 2, the I/O port signal of the present invention specifically includes that 1 road rotating speed coder signal ENCODER, there are 3 signals, 16 way switch amount input signal I [16], 10 way switch amount output signal O [10], 2 road asynchronous serial signal SCI-1, there are each 1 signal of sending and receiving and SCI-2, there are each 1 signal of sending and receiving, 1 road CANbus bus, having each 1 signal of sending and receiving, above signal is connected to CPLD and can again re-define；Also having 1 road I2C bus, have each 1 signal of clock, data, be directly connected to DSP3, EEPROM and IC5,18 roads analog input signal Ain [18] are connected to operational amplifier A 1～A18.
3, PWM message number
As in figure 2 it is shown, the PWM message number of the present invention mainly has: 36 tunnels send signal TX [36], 36 tunnels receive signal RX [36], are all connected to fpga chip.
4, the signal that CPLD with DSP1 is connected
As shown in Figure 2, the signal that CPLD with DSP1 of the present invention is connected mainly has: 1 road CANbus bus 1CANbus signal, has each 1 signal of sending and receiving, No. 1 encoder capture signal 1EQEP, has 3 signals, 1 road asynchronous serial signal 1SCI, has each 1 signal of sending and receiving.
5, the signal that CPLD with DSP2 is connected
As in figure 2 it is shown, the signal that CPLD with DSP2 of the present invention is connected mainly has: 1 road CANbus bus 2CANbus signal, there are each 1 signal of sending and receiving, 1 road asynchronous serial signal 2SCI, have each 1 signal of sending and receiving.
6, the signal that CPLD with DSP3 is connected
As shown in Figure 2, the signal that CPLD with DSP3 of the present invention is connected mainly has: 2 road CANbus bus 3CANbus signals, each 1 signal of sending and receiving and 4CANbus signal is had to have each 1 signal of sending and receiving, 2 road asynchronous serial signal 3SCI, there are each 1 signal of sending and receiving and 4SCI, have each 1 signal of sending and receiving, 16 single data buses 3Data [15:0], 19 address bus 3Addr [18:0], 4 controls bus 3Ctrl [4].3Data [15:0], 3Addr [18:0] and 3Ctrl [4] are also connected to memory RAM 3.
7, the signal that FPGA with DSP1 is connected
As in figure 2 it is shown, the signal that FPGA with DSP1 of the present invention is connected mainly has: 6 pwm signal 1PWM [6], 1 failure capture signal 1TZ, 16 single data buses 1Data [15:0], 8 address bus 1Addr [7:0], 4 controls bus 1Ctrl [4].1Data [15:0], 1Addr [7:0] and 1Ctrl [4] are also connected to memory RAM 1.
8, the signal that FPGA with DSP2 is connected
As in figure 2 it is shown, the signal that FPGA with DSP2 of the present invention is connected mainly has: 6 pwm signal 2PWM [6], 1 failure capture signal 2TZ, 16 single data buses 2Data [15:0], 8 address bus 2Addr [7:0], 4 controls bus 2Ctrl [4].2Data [15:0], 2Addr [7:0] and 2Ctrl [4] are also connected to memory RAM 2.
9, communication modes between DSP1 and DSP2, DSP3
As in figure 2 it is shown, between DSP1 and DSP2 of the present invention, DSP3 mainly there be communication modes: synchronous serial communication SPI, it is directly realized by the rapid communication between DSP1 and DSP2, DSP3；The asynchronous serial communication SCI communication between DSP1 and DSP2, DSP3 is realized by 1SCI, 2SCI, 3SCI signal and CPLD inter-process；The Controller Area Network BUS CANbus communication between DSP1 and DSP2, DSP3 is realized by 1CANbus, 2CANbus, 3CANbus signal and CPLD inter-process.The parallel communication between DSP1 and DSP2 can also be realized by 1Data [15:0], 1Addr [7:0] and 1Ctrl [4] bus and 2Data [15:0], 2Addr [7:0] and 2Ctrl [4] bus and FPGA inter-process between DSP1 and DSP2.
10, the analog signals that DSP1 Yu DSP2, DSP3 receive
As shown in Figure 2, the analog signals that DSP1 Yu DSP2 of the present invention, DSP3 receive is respectively as follows: 16 road 1AD [16], 16 road 2AD [16], 16 road 3AD [16], it is connected to the output of operational amplifier A 1～A18, the input of A1～A18 is connected to I/O port, can receive the analog signals of this circuit external.
Claims (4)
1. the core control panel controlling 36 power cells, specifically include that general on-site programmable gate array FPGA chip, 3 general-purpose digital signal process dsp chip, general complex programmable logic device (CPLD) chip, general-purpose operation amplifier A1～A18, general power supply chip IC1～IC4, general detection temperature humidity chip IC 5, for preserving the general-purpose chip EEPROM of parameter, pulse width modulation (PWM) mouth, input and output I/O port, 3 general-purpose digital signal process dsp chip, the wherein DSP1 of core control algolithm, its external memory storage is RAM1；Optionally with the DSP2 calculated in auxiliary, its external memory storage is RAM2；For this circuit and the extraneous DSP3 coordinating and controlling, its external memory storage is RAM3, it is characterized in that: if with PWM mouth as top on device layout, the lower section of so PWM mouth is FPGA, the lower section of FPGA is DSP1, the lower section of DSP1 is DSP3, the lower section of DSP3 is I/O port, the right of DSP1 is DSP2, the top of DSP2 is RAM2, the upper left side of DSP1 is RAM1, the left of DSP3 is CPLD, the top of CPLD is RAM3, the back of DSP3 is EEPROM, the left of FPGA is IC1, IC2, IC3, IC4, left side between RAM1 and RAM3 is IC5, the lower section of DSP2 is operational amplifier A 1～A18, I/O port is in bottom；nullIn circuit theory, PWM mouth is connected with the FPGA signal of telecommunication，RAM1 with the DSP1 signal of telecommunication is connected，RAM2 with the DSP2 signal of telecommunication is connected，RAM1、DSP1、RAM2、DSP2 is connected with the FPGA signal of telecommunication respectively，RAM3 with the DSP3 signal of telecommunication is connected，DSP3 is connected with DSP1 and the DSP2 signal of telecommunication respectively，CPLD respectively with DSP1、DSP2、DSP3、RAM3、The I/O port signal of telecommunication connects，General-purpose operation amplifier A1～A18 respectively with DSP1、DSP2、DSP3、The I/O port signal of telecommunication connects，Multiple power source chip IC 1～IC4 is connected with the I/O port signal of telecommunication，And the power supply of different voltage is provided for each device，General-purpose chip IC5 and DSP3、EEPROM、The I/O port signal of telecommunication connects.
A kind of core control panel controlling 36 power cells the most according to claim 1, it is characterised in that the chip that described FPGA uses is EP3C16240C8N type.
A kind of core control panel controlling 36 power cells the most according to claim 1, it is characterised in that described DSP1, DSP2, DSP3 uses the TMS320x28x family device of TI company.
A kind of core control panel controlling 36 power cells the most according to claim 1, it is characterised in that the chip that described CPLD uses is EPM1270T144C5 type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201210506064.XA CN102969876B (en) | 2012-12-01 | 2012-12-01 | A kind of core control panel controlling 36 power cells |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210506064.XA CN102969876B (en) | 2012-12-01 | 2012-12-01 | A kind of core control panel controlling 36 power cells |
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| Publication Number | Publication Date |
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| CN102969876A CN102969876A (en) | 2013-03-13 |
| CN102969876B true CN102969876B (en) | 2016-09-28 |
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| CN108121687A (en) * | 2016-11-28 | 2018-06-05 | 沈阳新松机器人自动化股份有限公司 | Core board and board |
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| US7346784B1 (en) * | 2002-08-29 | 2008-03-18 | Xilinx, Inc. | Integrated circuit device programming with partial power |
| CN201060394Y (en) * | 2007-06-05 | 2008-05-14 | 三垦力达电气(江阴)有限公司 | Controller device for high voltage frequency converter |
| CN101860253A (en) * | 2010-05-27 | 2010-10-13 | 国电南京自动化股份有限公司 | Control system of cascaded high-voltage inverter and method thereof |
| CN201965605U (en) * | 2010-12-21 | 2011-09-07 | 北京镭航世纪科技有限公司 | Universal array signal processing board |
| CN202041823U (en) * | 2010-12-09 | 2011-11-16 | 东南大学 | Universal control platform applied to cascading type power electronic converter |
| CN202978682U (en) * | 2012-12-01 | 2013-06-05 | 哈尔滨九洲电气股份有限公司 | Core control panel controlling 36 power units |
-
2012
- 2012-12-01 CN CN201210506064.XA patent/CN102969876B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7346784B1 (en) * | 2002-08-29 | 2008-03-18 | Xilinx, Inc. | Integrated circuit device programming with partial power |
| CN201060394Y (en) * | 2007-06-05 | 2008-05-14 | 三垦力达电气(江阴)有限公司 | Controller device for high voltage frequency converter |
| CN101860253A (en) * | 2010-05-27 | 2010-10-13 | 国电南京自动化股份有限公司 | Control system of cascaded high-voltage inverter and method thereof |
| CN202041823U (en) * | 2010-12-09 | 2011-11-16 | 东南大学 | Universal control platform applied to cascading type power electronic converter |
| CN201965605U (en) * | 2010-12-21 | 2011-09-07 | 北京镭航世纪科技有限公司 | Universal array signal processing board |
| CN202978682U (en) * | 2012-12-01 | 2013-06-05 | 哈尔滨九洲电气股份有限公司 | Core control panel controlling 36 power units |
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