CN102969271A - Semiconductor device and production method thereof - Google Patents
Semiconductor device and production method thereof Download PDFInfo
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- CN102969271A CN102969271A CN2011102557590A CN201110255759A CN102969271A CN 102969271 A CN102969271 A CN 102969271A CN 2011102557590 A CN2011102557590 A CN 2011102557590A CN 201110255759 A CN201110255759 A CN 201110255759A CN 102969271 A CN102969271 A CN 102969271A
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Abstract
The invention discloses a semiconductor device and a production method thereof. The method comprises steps of providing a semiconductor substrate; forming a first dielectric layer on the semiconductor substrate; forming an etching stopping layer on the surface of first dielectric layer of a redundant metal area; forming second dielectric layers on surfaces of the first dielectric layer and the etching stopping layer respectivley; etching the first dielectric layer, the second dielectric layers and the etching stopping layer so as to form a redundant metal slot and a metal wire slot; depositing metal layers in the redundant metal slot and the metal wire slot and on the dielectric layers; and conducting the chemical mechanical polishing process till the surfaces of the dielectric layers are exposed and forming redundant metal and a metal wire, wherein the height of the redundant metal is less than that of the metal wire. By the aid of the method, the depth of the redundant metal slot is less than that of the metal wire slot. Compared with the prior art, the thickness (height) of the redundant metal is reduced, and coupling capacitance in metal layers and among metal layers, which is introduced through the filling of the redundant metal, is reduced effectively.
Description
Technical field
The present invention relates to integrated circuit and make field, particularly a kind of semiconductor device and preparation method thereof.
Background technology
Along with the integrated level of semiconductor chip improves constantly, transistorized characteristic size is constantly dwindled thereupon.After entering into 130 nm technology node, be subject to the restriction of the high-ohmic of aluminium, copper-connection gradually substitution of Al interconnection becomes metal interconnected main flow.Because the dry etch process of copper is difficult for realizing that the manufacture method of copper interconnecting line can not obtain by etching sheet metal that as aluminum interconnecting the manufacture method of the copper interconnecting line that extensively adopts now is the embedding technique that is called Damascus technics.This Damascus technics comprises single Damascus technics of only making plain conductor and makes simultaneously the dual damascene process of through hole (also claiming contact hole) and plain conductor.Specifically, single damascene structure (also claiming single inlay structure) only is that the production method of single-layer metal wire is changed into mosaic mode (dielectric layer etching+metal filled) by traditional mode (metal etch+dielectric layer is filled), dual-damascene structure then is that through hole and plain conductor are combined, and so only needs together metal filled step.The common method of making dual-damascene structure generally has following several: all-pass hole precedence method (Full VIA First), half through hole precedence method (Partial VIA First), plain conductor precedence method (Full Trench First) and self aligned approach (Self-alignment method).
As shown in Figure 1, existing a kind of plain conductor manufacture craft comprises the steps: at first, metallization medium layer 110 at first on Semiconductor substrate 100; Then in dielectric layer 110, form metallic channel by photoetching and etching technics; Depositing metal layers subsequently, described metal level are filled in the metallic channel and on described dielectric layer 110 surfaces and have also deposited metal; Then, carry out cmp (CMP) technique and remove metal on the described dielectric layer 110, thereby in described metallic channel, made plain conductor 140.
As mentioned above, in Damascus technics, need to utilize chemical mechanical milling tech, be embedded in plain conductor 140 in the dielectric layer 110 with final formation.Yet, because the removal rate of metal and dielectric layer material is generally not identical, therefore can causes the depression (dishing) of not expecting and corrode (erosion) phenomenon the selectivity of grinding.Depression often occurs in metal and goes down to the plane of contiguous dielectric layer or exceed more than the plane of contiguous dielectric layer, and corroding then is that the part of dielectric layer is excessively thin.Depression and erosion are subject to the structure of figure and the Effects of Density of figure.Therefore, in order to reach uniform grinding effect, require the metallic pattern density on the Semiconductor substrate even as far as possible, and the metallic pattern density of product design usually can not satisfy the requirement of the cmp uniformity.At present, solution is to fill the pattern density homogenizing that the redundancy metal pattern makes domain at the white space of domain, thereby also forms redundancy metal (dummy metal) 150 when forming plain conductor 140 in dielectric layer 110, as shown in Figure 2.But, although redundancy metal has improved the uniformity of pattern density, but introduced inevitably in the extra metal level and the coupling capacitance of metal interlevel.
Summary of the invention
The invention provides a kind of semiconductor device and preparation method thereof, fill in the metal level of introducing and the coupling capacitance of metal interlevel effectively to reduce redundancy metal.
For solving the problems of the technologies described above, the invention provides a kind of manufacture method of semiconductor device, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate comprises redundancy metal district and nonredundancy metal area;
Form the first medium layer in described Semiconductor substrate;
First medium floor surface in described redundancy metal district forms etching barrier layer;
Form the second medium layer at described first medium layer and etching barrier layer surface;
The described first medium layer of etching, second medium layer and etching barrier layer, to form redundancy metal groove and metallic channel, the etch rate of described etching barrier layer is less than the etch rate of described first medium layer and second medium layer, and the degree of depth of described redundancy metal groove is less than the degree of depth of described metallic channel;
Depositing metal layers in described redundancy metal groove and metallic channel and on the dielectric layer;
Carry out chemical mechanical milling tech until expose the surface of described dielectric layer, to form redundancy metal and plain conductor, the height of described redundancy metal is less than the height of described plain conductor.
Optionally, in the manufacture method of described semiconductor device, the step that the first medium floor surface in described redundancy metal district forms etching barrier layer comprises: form etching barrier layer on described first medium floor surface; Etching is removed the etching barrier layer on the described nonredundancy metal area, forms etching barrier layer with the surface of the first medium floor in described redundancy metal district.
Optionally, in the manufacture method of described semiconductor device, the step of the described first medium layer of etching, second medium layer and etching barrier layer comprises: form the mask layer with redundancy metal groove and metallic channel pattern on described second medium layer surface; Etching first medium layer, second medium layer and etching barrier layer forming metallic channel at the nonredundancy metal area, and form the redundancy metal groove in the redundancy metal district.
Optionally, in the manufacture method of described semiconductor device, the step of the described first medium layer of etching, second medium layer and etching barrier layer comprises: form the mask layer with through-hole pattern on described second medium layer surface; Second medium layer on the described nonredundancy metal area of etching forms through hole; Form the mask layer with redundancy metal groove and metallic channel pattern on described second medium layer surface; Etching first medium layer, second medium layer and etching barrier layer forming metallic channel at described lead to the hole site, and form the redundancy metal groove in the redundancy metal district.
Optionally, in the manufacture method of described semiconductor device, the material of described etching barrier layer is a kind of or its combination in carborundum, silicon nitride, silicon oxynitride, titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, the tantalum oxide.Described dielectric layer is the low k dielectric layer.
The present invention also provides the manufacture method of another kind of semiconductor device, comprising:
Semiconductor substrate is provided, and described Semiconductor substrate comprises redundancy metal district and nonredundancy metal area;
Form the first medium layer in described Semiconductor substrate;
First medium floor surface in described redundancy metal district forms etching barrier layer;
Form the second medium layer at described first medium layer and etching barrier layer surface;
Form hard mask layer at described second medium layer, and the described hard mask layer of etching forms hard mask metallic channel and hard mask redundancy metal groove;
Second medium layer on the etching nonredundancy metal area is to form through hole at hard mask metallic channel place;
The described first medium layer of etching, second medium layer, etching barrier layer and remaining hard mask layer, to form the redundancy metal groove at described lead to the hole site formation metallic channel and in the redundancy metal district, the etch rate of described etching barrier layer is less than the etch rate of described first medium layer and second medium layer, and the degree of depth of described redundancy metal groove is less than the degree of depth of described metallic channel;
Depositing metal layers in described redundancy metal groove and metallic channel and on the dielectric layer;
Carry out chemical mechanical milling tech until expose the surface of described dielectric layer, to form redundancy metal and plain conductor, the height of described redundancy metal is less than the height of described plain conductor.
Optionally, in the manufacture method of described semiconductor device, the material of described hard mask layer is a kind of or its combination in carborundum, silicon nitride, silicon oxynitride, titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, the tantalum oxide.Described dielectric layer is the low k dielectric layer.
Accordingly, the present invention also provides a kind of semiconductor device that utilizes said method to form, and comprising: Semiconductor substrate; Be formed at the dielectric layer on the described Semiconductor substrate; And being formed at redundancy metal and plain conductor in the described dielectric layer, the height of described redundancy metal is less than the height of described plain conductor.
The present invention forms the first medium layer in Semiconductor substrate first, then form etching barrier layer on the first medium floor surface in redundancy metal district, then form the second medium layer at described first medium layer and etching barrier layer surface, in the subsequent etching step, because the etch rate of etching barrier layer is less than the etch rate of first medium layer and second medium layer, therefore so that the degree of depth of the redundancy metal groove that forms less than the degree of depth of metallic channel, the height of the final redundancy metal that forms is less than the height of plain conductor, compared with prior art reduced the thickness (highly) of redundancy metal, can effectively reduce redundancy metal and fill in the metal level of introducing and the coupling capacitance of metal interlevel.
Description of drawings
Fig. 1 is the structural representation of existing a kind of semiconductor device;
Fig. 2 is the structural representation of existing another kind of semiconductor device;
Fig. 3 is the schematic flow sheet of manufacture method of the semiconductor device of the embodiment of the invention one;
Fig. 4 A～4F is the cross-sectional view of device corresponding to each step in the manufacture method of semiconductor device of the embodiment of the invention one;
Fig. 5 A～5G is the cross-sectional view of device corresponding to each step in the manufacture method of semiconductor device of the embodiment of the invention two;
Fig. 6 A～6H is the cross-sectional view of device corresponding to each step in the manufacture method of semiconductor device of the embodiment of the invention three.
Embodiment
Mention that in background technology although redundancy metal has improved the uniformity of pattern density, but introduced in the extra metal level and the coupling capacitance of metal interlevel, electric capacity can be calculated by following formula:
Wherein, ε
0Be permittivity of vacuum; ε
rBe the medium dielectric constant; S is relative metallic area; The intermetallic distance that d is.This shows, reduce the relative area of metal and increase intermetallic apart from reducing electric capacity.That is to say that the volume that reduces redundancy metal can reduce the extra intermetallic coupling capacitance introduced owing to adding redundancy metal.For this reason, the present invention makes the degree of depth of redundancy metal groove less than the degree of depth of metallic channel, therefore the height of the final redundancy metal that forms is less than the height of plain conductor, compared with prior art reduced the thickness (highly) of redundancy metal, can effectively reduce redundancy metal and fill in the metal level of introducing and the coupling capacitance of metal interlevel.
The present invention also provides a kind of semiconductor device, comprising: Semiconductor substrate; Be formed at the dielectric layer on the Semiconductor substrate; And be formed at redundancy metal and plain conductor in the dielectric layer, the height of described redundancy metal is less than the height of described plain conductor, compared with prior art reduced the thickness of redundancy metal, can effectively reduce redundancy metal and fill in the metal level of introducing and the coupling capacitance of metal interlevel.
Embodiment one
Please refer to Fig. 3, it is the schematic flow sheet of the manufacture method of semiconductor device of the present invention.As shown in Figure 3, the manufacture method of described semiconductor device comprises the steps:
Step S310: Semiconductor substrate is provided, and Semiconductor substrate comprises redundancy metal district and nonredundancy metal area;
Step S320: form the first medium layer in described Semiconductor substrate;
Step S330: the first medium floor surface in described redundancy metal district forms etching barrier layer;
Step S340: form the second medium layer at described first medium layer and etching barrier layer surface;
Step S350: the described first medium layer of etching, second medium layer and etching barrier layer, to form redundancy metal groove and metallic channel, the etch rate of described etching barrier layer is less than the etch rate of described first medium layer and second medium layer, so that the degree of depth of described redundancy metal groove is less than the degree of depth of described metallic channel;
Step S360: depositing metal layers in described redundancy metal groove and metallic channel and on the dielectric layer;
Step S370: carry out chemical mechanical milling tech until expose the surface of described dielectric layer, to form redundancy metal and plain conductor, the height of described redundancy metal is less than the height of described plain conductor.
Be described in more detail below in conjunction with the manufacturing method of semiconductor device of generalized section to present embodiment.
Shown in Fig. 4 A, at first, provide Semiconductor substrate 400, this Semiconductor substrate 400 comprises redundancy metal district 402 and nonredundancy metal area 401, described redundancy metal district 402 is in order to form redundancy metal, and the semiconductor substrate region outside the described redundancy metal district 402 is nonredundancy metal area 401.Wherein, be formed with metal line in the described Semiconductor substrate 400, because the present invention relates generally to the manufacture craft of metal damascene structure, thus will not introduce the process that in Semiconductor substrate 400, forms metal line, but those skilled in the art are still this and know.
Continue with reference to figure 4A, then, form first medium layer 411 in Semiconductor substrate 400, described first medium layer 411 is preferably low-k (K) dielectric layer, postpone with the resistance capacitance that reduces its parasitic capacitance and metallic copper, satisfy the requirement of Quick conductive.Better, it is black diamond (black diamond that described first medium layer 410 adopts the trade mark of Material Used (Applied Materials) company, BD) silicon oxide carbide, perhaps adopt the Coral material of Novellus company, again or adopt and to utilize spin coating process to make the Silk advanced low-k materials of Dow Corning Corporation etc.
With reference to figure 4B, then, form etching barrier layers on described first medium layer 411 surface, and utilize photoetching and etching technics to remove etching barrier layer on the described nonredundancy metal area 401, form etching barrier layer 430 with the surface of the first medium floor in described redundancy metal district 402.The material of described etching barrier layer 430 can be a kind of or its combination in carborundum, silicon nitride, silicon oxynitride, titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, the tantalum oxide, described etching barrier layer 430 can utilize physical vapour deposition (PVD) (PVD) or chemical vapour deposition (CVD) (CVD) technology to form, and the etch rate of described etching barrier layer 430 is less than the etch rate of the second medium layer of described first medium layer and follow-up formation.
Shown in Fig. 4 C, thereafter, form second medium layer 412 at described first medium layer 411 and etching barrier layer 430 surfaces, better, described second medium layer 412 is identical with the material of first medium layer 411.
Shown in Fig. 4 D, form the mask layer with redundancy metal groove and metallic channel pattern on described second medium layer 412 surface, and the first medium floor on etching redundancy metal district 402 and the nonredundancy metal area 401 simultaneously, second medium layer and etching barrier layer, to form metallic channel 412a at nonredundancy metal area 401 and the 402 formation redundancy metal groove 411a in the redundancy metal district, because the etch rate of described etching barrier layer 430 is less than the etch rate of first medium layer 411 and second medium layer 412, although in this step be etching simultaneously, the degree of depth of the redundancy metal groove 411a of final formation is less than the degree of depth of metallic channel 412a.Can select etching gas commonly used to described first medium layer, second medium layer and etching barrier layer, do not repeat them here, but those skilled in the art are still and know.
Shown in Fig. 4 E, subsequently, depositing metal layers 420 in described redundancy metal groove 411a and the metallic channel 412a, because the characteristic of depositing operation also can deposit metal on this process medium layer 410, the material of wherein said metal level 420 is copper.
Shown in Fig. 4 F, subsequently, carry out cmp (CMP) technique until expose the surface of dielectric layer 410, in redundancy metal groove 411a, to form redundancy metal 421, and in metallic channel 412a plain conductor 422, the height of described redundancy metal 421 is less than the height of plain conductor 422.Owing to make the degree of depth of redundancy metal groove 411a less than the degree of depth of metallic channel 412a, therefore the height of the final redundancy metal 421 that forms is less than the height of plain conductor 422, compared with prior art reduced the height (thickness) of redundancy metal 421, filled in the metal level of introducing and the coupling capacitance of metal interlevel thereby reduced redundancy metal.
Embodiment two
Shown in Fig. 5 A, at first, provide Semiconductor substrate 500, this Semiconductor substrate 500 comprises redundancy metal district 502 and nonredundancy metal area 501, described redundancy metal district 502 is in order to form redundancy metal, and the semiconductor substrate region outside the described redundancy metal district 502 is nonredundancy metal area 501.Subsequently, form first medium layer 511 in Semiconductor substrate 500.
With reference to figure 5B, then, form etching barrier layer on described first medium layer 511 surface, and utilize photoetching and etching technics to remove etching barrier layer on the described nonredundancy metal area 501, form etching barrier layer 530 with the surface of the first medium floor in described redundancy metal district 502, the etch rate of described etching barrier layer 530 is less than the etch rate of the second medium layer 512 of described first medium 511 and follow-up formation.
Shown in Fig. 5 C, thereafter, form second medium layer 512 at described first medium layer 511 and etching barrier layer 530 surfaces, better, described second medium layer 512 is identical with the material of first medium layer 511.
Shown in Fig. 5 D, utilize photoetching process forming the mask layer with through-hole pattern on described second medium layer 512 surface, and take described mask layer as mask, second medium layer on the described nonredundancy metal area 501 of etching, thereby form through hole 513a at the nonredundancy metal area, and then remove described mask layer.Need to prove, thereby also can etch away again in this step part first medium layer and form through hole 513a, the present invention also will not limit this, and the thickness of the degree of depth of the through hole that can form as requested and first medium layer and second medium layer is determined etch period and the etching terminal of this etching step.
Shown in Fig. 5 E, subsequently, form the mask layer with metallic channel pattern and redundancy metal groove pattern at described second medium layer 512, and take described mask layer as mask, the first medium floor on etching described redundancy metal district and the nonredundancy metal area simultaneously, second medium layer and etching barrier layer, with the 502 formation redundancy metal groove 511a in the redundancy metal district, and at through hole 513a correspondence position formation metallic channel 512a, namely stop etching until expose the surface of Semiconductor substrate 500 in this etch step, because the etch rate of etching barrier layer 530 is less than the etch rate of first medium layer 511 and second medium layer 512, therefore although be etching simultaneously, the degree of depth of the redundancy metal groove 511a of final formation is less than the degree of depth of metallic channel 512a.
Shown in Fig. 5 F, subsequently, depositing metal layers 520 in described redundancy metal groove 511a and the metallic channel 512a is because the characteristic of depositing operation also can deposit metal on this process medium layer 510.
Shown in Fig. 5 G, subsequently, carry out chemical mechanical milling tech until expose the surface of dielectric layer 510, in redundancy metal groove 511a, to form redundancy metal 521, and in metallic channel 512a plain conductor 522, the height of described redundancy metal 521 is less than the height of plain conductor 522, therefore the height of the final redundancy metal 521 that forms is less than the height of plain conductor 522, compared with prior art reduced the height of redundancy metal 521, effectively reduced redundancy metal and filled in the metal level of introducing and the coupling capacitance of metal interlevel.
Embodiment three
As shown in Figure 6A, at first, provide Semiconductor substrate 600, this Semiconductor substrate 600 comprises redundancy metal district 602 and nonredundancy metal area 601, described redundancy metal district 602 is in order to form redundancy metal, and the semiconductor substrate region outside the described redundancy metal district 602 is nonredundancy metal area 601.Subsequently, form first medium layer 611 in Semiconductor substrate 600.
With reference to figure 6B, then, form etching barrier layer on described first medium layer 611 surface, and utilize photoetching and etching technics to remove etching barrier layer on the described nonredundancy metal area 601, form etching barrier layer 630 with the surface of the first medium floor in described redundancy metal district 602, the etch rate of described etching barrier layer 630 is less than the etch rate of the second medium layer 612 of described first medium 611 and follow-up formation.
Shown in Fig. 6 C, thereafter, form second medium layer 612 at described first medium layer 611 and etching barrier layer 630 surfaces, better, described second medium layer 612 is identical with the material of first medium layer 611.
Shown in Fig. 6 D, form hard mask layer at described second medium layer 612, and the described hard mask layer of etching is to form hard mask metallic channel 642a and hard mask redundancy metal groove 641a.
Shown in Fig. 6 E, the second medium layer on the etching nonredundancy metal area 601, to form through hole 613a at hard mask metallic channel 642a place, described hard mask metallic channel 642a has played self aligned effect.
Shown in Fig. 6 F, the described first medium layer 611 of etching, second medium layer 612, etching barrier layer 630 and remaining hard mask layer forming metallic channel 612a in described through hole 613a position, and 602 form redundancy metal groove 611a in the redundancy metal district.
Shown in Fig. 6 G, subsequently, depositing metal layers 620 in redundancy metal groove 611a and the metallic channel 612a is because the characteristic of depositing operation also can deposit metal on this process medium layer 610.
Shown in Fig. 6 H, subsequently, carry out chemical mechanical milling tech until expose the surface of described dielectric layer 610, in redundancy metal groove 611a, to form redundancy metal 621, and in metallic channel 612a plain conductor 622, the height of described redundancy metal 621 is less than the height of described plain conductor 622, because the height of the final redundancy metal 621 that forms is less than the height of plain conductor 622, namely compared with prior art reduced the height (thickness) of redundancy metal 621, therefore can effectively reduce redundancy metal and fill in the metal level of introducing and the coupling capacitance of metal interlevel.
In sum, the present invention forms the first medium layer in Semiconductor substrate first, then form etching barrier layer on the first medium floor surface in redundancy metal district, then form the second medium layer at described first medium layer and etching barrier layer surface, in the subsequent etching step, because the etch rate of etching barrier layer is less than the etch rate of first medium layer and second medium layer, therefore so that the degree of depth of the redundancy metal groove that forms less than the degree of depth of metallic channel, the height of the final redundancy metal that forms is less than the height of plain conductor, compared with prior art reduced the thickness (highly) of redundancy metal, can effectively reduce redundancy metal and fill in the metal level of introducing and the coupling capacitance of metal interlevel.
Need to prove that each embodiment adopts the mode of going forward one by one to describe in this specification, each embodiment stresses is difference with other embodiment, the mutually reference of relevant part.And accompanying drawing all adopts the form of simplifying very much and all uses non-accurately ratio, only is used for purpose convenient, each embodiment of lucidly aid illustration the present invention.
In addition, although below describe the present invention in detail as an example of the dual damascene metal interconnect structure (referring to embodiment three) of the dual damascene metal interconnect structure (referring to embodiment two) of single Damascus metal interconnect structure (referring to embodiment one), through hole elder generation etching and the first etching of the hard mask groove of self-alignment type example respectively, those skilled in the art can also carry out various changes and modification and not break away from the spirit and scope of the present invention the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (10)
1. the manufacture method of a semiconductor device comprises:
Semiconductor substrate is provided, and described Semiconductor substrate comprises redundancy metal district and nonredundancy metal area;
Form the first medium layer in described Semiconductor substrate;
First medium floor surface in described redundancy metal district forms etching barrier layer;
Form the second medium layer at described first medium layer and etching barrier layer surface;
The described first medium layer of etching, second medium layer and etching barrier layer, to form redundancy metal groove and metallic channel, the etch rate of described etching barrier layer is less than the etch rate of described first medium layer and second medium layer, and the degree of depth of described redundancy metal groove is less than the degree of depth of described metallic channel;
Depositing metal layers in described redundancy metal groove and metallic channel and on the dielectric layer;
Carry out chemical mechanical milling tech until expose the surface of described dielectric layer, to form redundancy metal and plain conductor, the height of described redundancy metal is less than the height of described plain conductor.
2. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the step that the first medium floor surface in described redundancy metal district forms etching barrier layer comprises:
Form etching barrier layer on described first medium layer surface;
Etching is removed the etching barrier layer on the described nonredundancy metal area, forms etching barrier layer with the surface of the first medium floor in described redundancy metal district.
3. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the step of the described first medium layer of etching, second medium layer and etching barrier layer comprises:
Form the mask layer with redundancy metal groove and metallic channel pattern on described second medium layer surface;
Etching first medium layer, second medium layer and etching barrier layer forming metallic channel at the nonredundancy metal area, and form the redundancy metal groove in the redundancy metal district.
4. the manufacture method of semiconductor device as claimed in claim 1 is characterized in that, the step of the described first medium layer of etching, second medium layer and etching barrier layer comprises:
Form the mask layer with through-hole pattern on described second medium layer surface;
Second medium layer on the described nonredundancy metal area of etching forms through hole;
Form the mask layer with redundancy metal groove and metallic channel pattern on described second medium layer surface;
Etching first medium layer, second medium layer and etching barrier layer forming metallic channel at described lead to the hole site, and form the redundancy metal groove in the redundancy metal district.
5. such as the manufacture method of the described semiconductor device of any one in the claim 1 to 4, it is characterized in that the material of described etching barrier layer is a kind of or its combination in carborundum, silicon nitride, silicon oxynitride, titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, the tantalum oxide.
6. such as the manufacture method of the described semiconductor device of any one in the claim 1 to 4, it is characterized in that described dielectric layer is the low k dielectric layer.
7. the manufacture method of a semiconductor device comprises:
Semiconductor substrate is provided, and described Semiconductor substrate comprises redundancy metal district and nonredundancy metal area;
Form the first medium layer in described Semiconductor substrate;
First medium floor surface in described redundancy metal district forms etching barrier layer;
Form the second medium layer at described first medium layer and etching barrier layer surface;
Form hard mask layer at described second medium layer, and the described hard mask layer of etching forms hard mask metallic channel and hard mask redundancy metal groove;
Second medium layer on the etching nonredundancy metal area is to form through hole at hard mask metallic channel place;
The described first medium layer of etching, second medium layer, etching barrier layer and remaining hard mask layer, to form the redundancy metal groove at described lead to the hole site formation metallic channel and in the redundancy metal district, the etch rate of described etching barrier layer is less than the etch rate of described first medium layer and second medium layer, and the degree of depth of described redundancy metal groove is less than the degree of depth of described metallic channel;
Depositing metal layers in described redundancy metal groove and metallic channel and on the dielectric layer;
Carry out chemical mechanical milling tech until expose the surface of described dielectric layer, to form redundancy metal and plain conductor, the height of described redundancy metal is less than the height of described plain conductor.
8. the manufacture method of semiconductor device as claimed in claim 7 is characterized in that, the material of described hard mask layer is a kind of or its combination in carborundum, silicon nitride, silicon oxynitride, titanium, titanium nitride, titanium oxide, tantalum, tantalum nitride, the tantalum oxide.
9. the manufacture method of semiconductor device as claimed in claim 7 is characterized in that, described dielectric layer is the low k dielectric layer.
10. a semiconductor device that utilizes claim 1 or 7 described methods to form is characterized in that, comprising: Semiconductor substrate; Be formed at the dielectric layer on the described Semiconductor substrate; And being formed at redundancy metal and plain conductor in the described dielectric layer, the height of described redundancy metal is less than the height of described plain conductor.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110148582A (en) * | 2019-04-15 | 2019-08-20 | 上海华力集成电路制造有限公司 | The manufacturing method of contact hole |
| CN110190024A (en) * | 2019-04-15 | 2019-08-30 | 上海华力集成电路制造有限公司 | The manufacturing method of contact hole |
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Application publication date: 20130313 |