CN102968350A - System debugging method for solid state memory - Google Patents
System debugging method for solid state memory Download PDFInfo
- Publication number
- CN102968350A CN102968350A CN2012104450728A CN201210445072A CN102968350A CN 102968350 A CN102968350 A CN 102968350A CN 2012104450728 A CN2012104450728 A CN 2012104450728A CN 201210445072 A CN201210445072 A CN 201210445072A CN 102968350 A CN102968350 A CN 102968350A
- Authority
- CN
- China
- Prior art keywords
- reading
- data
- supervising device
- flash
- pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
The invention provides a system debugging method for a solid state memory. The method comprises stepwise debugging of a power supply module, a main control board and an acquisition board. Through the system debugging method provided by the invention, a series of technical problems occurring during system debugging of the solid state memory which has high reliability, large volume, low power consumption and high speed can be solved effectively.
Description
Technical field
The present invention relates to memory area, relate in particular to the adjustment method of solid-state memory.
Background technology
Solid-state memory with FPGA as main control unit, realization is to the control of each module of system, with Flash as storage medium, speed according to data stream, adopt the biplane Writing Technology, finish the collection of 6 tunnel analog quantitys, reception and the data storage work of 2 railway digital amounts, and the working condition of solid-state memory is transferred to the topside readout supervising device and carries out Real-Time Monitoring can will test by the LVDS interface time, after test is finished, the data reading among the Flash is passed back to the topside readout supervising device, for post analysis and processing.
But because the slow development of domestic semiconductor industry has caused the solid-state memory slower development of China, and owing to start late, the solid-state memory of domestic development is comparatively backward at aspects such as memory capacity, message transmission rates.The in recent years development of domestic spationautics is for the development of China's solid-state memory provides good opportunity, so that the solid-state memory of China is towards the future development of high reliability, large capacity, low-power consumption, two-forty.Along with the fast development of solid-state memory, for the system testing of solid-state memory series of technical appears.
Summary of the invention
Based on the problems referred to above, the present invention proposes a kind of system debug method with solid-state memory of high reliability, large capacity, low-power consumption, two-forty.
One aspect of the present invention proposes a kind of solid state memory system adjustment method, and concrete steps comprise:
(1) for power module, at first with multimeter testing power supply plate power supply input whether short-circuit conditions is arranged, then test each circuit board supply module and whether have the phenomenon of short circuit, if there is not short circuit phenomenon, power module and power conversion chip and peripheral component can be welded on the circuit board, provide 28V voltage to power panel, use multimeter test each several part output voltage whether normal, if normal, can carry out next step operation;
(2) for master control borad, the realization of completion system mode of operation function, system is in " resetting " pattern in the 20s that powers on, during 20s according to the setting of uphole equipment reading supervising device, enter " record " pattern or " reading " pattern, debugging LVDS communication module, so that the LVDS receiver module is after the order that receives the transmission of uphole equipment reading supervising device, main control unit can send test data to topside readout monitoring equipment, at last, debugging Flash storage unit, realize under " record " pattern with test data write and " reading " pattern under data reading and be transferred to the topside readout supervising device by LVDS, and realization Flash Self-disconnecting defencive function;
(3) for collection plate, welding component, there be not short-circuit conditions, under the condition of FPGA normal operation, at first write the analog acquisition program, and it is write external FIFO, master control borad Flash control module is read external FIFO, and after the analog quantity that gathers write Flash, data reading is transferred to the reading supervising device, and the reading supervising device transfers data to computing machine, uses upper computer software that the analog quantity that gathers is analyzed, look into the situation of losing number or error code that sees if there is, and it is drawn, whether with waveform that outside source send consistent, then if observing the waveform drawn according to image data, write respectively two-way digital quantity reception program, making uses the same method is transferred to computing machine with it, checks whether the digital quantity of reception is correct, at last digital quantity and analog quantity is compiled frame, when compiling frame, the signal that will " take off " is squeezed into packet, and the data of compiling behind the frame are written to Flash, data reading is transferred to that computing machine unpacks the analysis mode amount and whether digital quantity is correct again.
Description of drawings
In order to be illustrated more clearly in the technical scheme in the embodiment of the invention, the accompanying drawing of required use was done to introduce simply during the below will describe embodiment, obviously, accompanying drawing in the following describes only is part embodiment of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 shows the system debug process flow diagram of solid-state memory according to an embodiment of the invention.
Embodiment
Describe specific embodiments of the invention in detail below in conjunction with accompanying drawing.
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
Draw the schematic diagram of solid-state memory power panel, collection plate and master control borad according to design proposal, and carry out the PCB design, after circuit board making is finished, welded components and parts, carry out the debugging of systemic-function.When debugging, realize first the function of each module, at last each module combinations is got up to carry out integral body debugging and joint-trial.The concrete steps of debugging as shown in Figure 1.
At first, because any electronic system all needs power supply, so power module is the pacing items that realizes allomeric function.Whether power panel, collection plate and master control borad for not welding at first have short-circuit conditions with multimeter testing power supply plate power supply input, then test the phenomenon whether each circuit board supply module exists short circuit.After finishing test, if there is not short circuit phenomenon, power module and power conversion chip and peripheral component can be welded on the circuit board.After welding is finished, provide 28V voltage to power panel, use multimeter test each several part output voltage whether normal, if normal, can carry out next step operation.
For master control borad, welding component in the situation of guaranteeing not have short circuit and FPGA normally to download, is write code, realizes each function.At first, the realization of completion system mode of operation function, system is in " resetting " pattern in the 20s that powers on, according to the setting of uphole equipment reading supervising device, enter " record " pattern or " reading " pattern during 20s.Secondly, debugging LVDS communication module, so that the LVDS receiver module is after receiving the order that uphole equipment reading supervising device sends, main control unit can send test data to topside readout monitoring equipment.At last, debugging Flash storage unit, realize under " record " pattern with test data write and " reading " pattern under data reading and be transferred to the topside readout supervising device by LVDS, and realization Flash Self-disconnecting defencive function.
At last, for collection plate, welding component, guaranteeing does not have short-circuit conditions, under the condition of FPGA normal operation, at first write the analog acquisition program, and it is write external FIFO, master control borad Flash control module is read external FIFO, and after the analog quantity that gathers write Flash, data reading being transferred to the reading supervising device, the reading supervising device transfers data to computing machine, use upper computer software that the analog quantity that gathers is analyzed, whether look into and see if there is the situation of losing number or error code, and it is drawn, it is consistent with the waveform of outside source transmission to observe the waveform of drawing according to image data.Secondly, write respectively two-way digital quantity reception program, making uses the same method is transferred to computing machine with it, checks whether the digital quantity of reception is correct.At last digital quantity and analog quantity are compiled frame, when compiling frame, the signal that will " take off " is squeezed into packet, and the data behind the volume frame are written to Flash, data reading is transferred to that computing machine unpacks the analysis mode amount and whether digital quantity is correct again.
Need to prove that above embodiment only is the exemplary description to technical solution of the present invention, and is not limitation of the present invention; Although with reference to top embodiment the present invention is had been described in detail; but; those of ordinary skill in the art should be understood that fully; do not breaking away from the protection domain that limited by claims of the present invention under the prerequisite of spirit; can make amendment or part technical characterictic wherein is equal to replacement the technical scheme that above-described embodiment is put down in writing, these all should belong to protection scope of the present invention.
Claims (1)
1. solid state memory system adjustment method, concrete steps comprise:
(1) for power module, at first with multimeter testing power supply plate power supply input whether short-circuit conditions is arranged, then test each circuit board supply module and whether have the phenomenon of short circuit, if there is not short circuit phenomenon, power module and power conversion chip and peripheral component can be welded on the circuit board, provide 28V voltage to power panel, use multimeter test each several part output voltage whether normal, if normal, can carry out next step operation;
(2) for master control borad, the realization of completion system mode of operation function, system is in " resetting " pattern in the 20s that powers on, during 20s according to the setting of uphole equipment reading supervising device, enter " record " pattern or " reading " pattern, debugging LVDS communication module, so that the LVDS receiver module is after the order that receives the transmission of uphole equipment reading supervising device, main control unit can send test data to topside readout monitoring equipment, at last, debugging Flash storage unit, realize under " record " pattern with test data write and " reading " pattern under data reading and be transferred to the topside readout supervising device by LVDS, and realization Flash Self-disconnecting defencive function;
(3) for collection plate, welding component, there be not short-circuit conditions, under the condition of FPGA normal operation, at first write the analog acquisition program, and it is write external FIFO, master control borad Flash control module is read external FIFO, and after the analog quantity that gathers write Flash, data reading is transferred to the reading supervising device, the reading supervising device transfers data to computing machine, uses upper computer software that the analog quantity that gathers is analyzed, and looks into the situation of losing number or error code that sees if there is, and it is drawn, whether the waveform that observation is drawn according to image data is consistent with the waveform of outside source transmission, then, writes respectively two-way digital quantity reception program, making uses the same method is transferred to computing machine with it, checks whether the digital quantity of reception is correct; At last digital quantity and analog quantity are compiled frame, when compiling frame, the signal that will " take off " is squeezed into packet, and the data behind the volume frame are written to Flash, data reading is transferred to that computing machine unpacks the analysis mode amount and whether digital quantity is correct again.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012104450728A CN102968350A (en) | 2012-11-09 | 2012-11-09 | System debugging method for solid state memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012104450728A CN102968350A (en) | 2012-11-09 | 2012-11-09 | System debugging method for solid state memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102968350A true CN102968350A (en) | 2013-03-13 |
Family
ID=47798503
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012104450728A Pending CN102968350A (en) | 2012-11-09 | 2012-11-09 | System debugging method for solid state memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102968350A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108958658B (en) * | 2018-06-28 | 2021-06-29 | 郑州云海信息技术有限公司 | Target data acquisition method and device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100573694B1 (en) * | 2002-08-17 | 2006-04-26 | 삼성전자주식회사 | Image recording/reproducing apparatus for system optimization |
| JP2006172148A (en) * | 2004-12-16 | 2006-06-29 | Hitachi High-Technologies Corp | Operation control system |
| CN101839974A (en) * | 2010-05-05 | 2010-09-22 | 北京航空航天大学 | Dual-interface radar data recorder |
| US20100281276A1 (en) * | 2009-04-29 | 2010-11-04 | Micro-Star Internationa'l Co., Ltd. | Computer system with power source control and power source control method |
-
2012
- 2012-11-09 CN CN2012104450728A patent/CN102968350A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100573694B1 (en) * | 2002-08-17 | 2006-04-26 | 삼성전자주식회사 | Image recording/reproducing apparatus for system optimization |
| JP2006172148A (en) * | 2004-12-16 | 2006-06-29 | Hitachi High-Technologies Corp | Operation control system |
| US20100281276A1 (en) * | 2009-04-29 | 2010-11-04 | Micro-Star Internationa'l Co., Ltd. | Computer system with power source control and power source control method |
| CN101839974A (en) * | 2010-05-05 | 2010-09-22 | 北京航空航天大学 | Dual-interface radar data recorder |
Non-Patent Citations (1)
| Title |
|---|
| 朱岩，沈卫华，孙辉先: "《基于闪存的固态存储器的数据管理》", 《计算机工程》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108958658B (en) * | 2018-06-28 | 2021-06-29 | 郑州云海信息技术有限公司 | Target data acquisition method and device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106951587A (en) | FPGA debugging systems and method | |
| CN102541707B (en) | Multiplex JTAG (Joint Test Action Group) interface-based FPGA (Field Programmable Gate Array) on-chip logic analyzer system and method | |
| CN104820637B (en) | A kind of hand-held USB3.0 protocol analyzers | |
| US9684583B2 (en) | Trace data export to remote memory using memory mapped write transactions | |
| CN107741559B (en) | Single event upset test system and method under space radiation environment | |
| CN103092119B (en) | A kind of bus state supervision method based on FPGA | |
| CN104361143A (en) | Portable data acquisition card and method thereof | |
| CN114328369A (en) | Automatic test equipment all-state signal monitoring facilities based on multisource information fusion | |
| CN104408213A (en) | Portable data acquisition card | |
| CN103207824B (en) | Not by the emulator of the interference that resets under monitoring mode | |
| CN104461796B (en) | JTAG debugging modules and adjustment method for embedded 8051CPU | |
| CN102968350A (en) | System debugging method for solid state memory | |
| CN103838664A (en) | Pressure testing method and device | |
| CN203275482U (en) | Data acquisition card of virtual oscilloscope | |
| CN102288298B (en) | Detector simulator device | |
| CN111722968A (en) | Hardware debugging method, device and system and readable storage medium | |
| CN103840822A (en) | Astronavigation FPGA universal refresh circuit based on SELECTMAP and achieving method thereof | |
| CN104572515B (en) | Tracking module, method, system and on-chip system chip | |
| CN103389438B (en) | A kind of for the welding detection system with cpu pcb and method | |
| CN204706031U (en) | Serial peripheral equipment interface SPI bus circuit and electronic equipment | |
| CN109101386A (en) | A kind of emulator for supporting ram test | |
| CN205068366U (en) | Circuit of exempting from wire jumper is downloaded to program run and JTAG procedure | |
| CN103984263B (en) | A kind of compatible ISA, the general dsp module of pci bus interface and collocation method | |
| CN101937665B (en) | Method for enhancing sharing of printed circuit board of display | |
| CN202854797U (en) | Detection device for computer hardware |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| AD01 | Patent right deemed abandoned |
Effective date of abandoning: 20151216 |
|
| C20 | Patent right or utility model deemed to be abandoned or is abandoned |