CN102955308A - Array substrate for display device and method of fabricating the same - Google Patents
Array substrate for display device and method of fabricating the same Download PDFInfo
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- CN102955308A CN102955308A CN2012102876764A CN201210287676A CN102955308A CN 102955308 A CN102955308 A CN 102955308A CN 2012102876764 A CN2012102876764 A CN 2012102876764A CN 201210287676 A CN201210287676 A CN 201210287676A CN 102955308 A CN102955308 A CN 102955308A
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Abstract
The invention discloses an array substrate for a display device and a method of fabricating the same. The device comprises a substrate, a grid line formed on the substrate along a first direction; a data line formed above the substrate along a second direction, wherein the data line and the grid line are intersected with each other to limit a pixel region; a film transistor formed in the pixel region and having a drain, a grid connected with the grid line and a source connected with the data line; a pixel electrode formed in the pixel region and connected with the drain; a first auxiliary grid pattern formed above the grid line and contacted with the grid line; and a first auxiliary data pattern formed above the data line a nd contacted with the data line.
Description
The application requires to enjoy in korean patent application 10-2011-0082808 number submitted on August 19th, 2011 and the right of priority of the korean patent application submitted on June 25th, 2012 10-2012-0067842 number, for all purposes, incorporate described patented claim into this paper by quoting, as described patented claim this is all set forth.
Technical field
Present disclosure relates to a kind of array base palte for display device, particularly relates to a kind of array base palte of the display device be used to comprising thin film transistor (TFT), and the manufacture method of this array base palte.
Background technology
Along with the fast development of infotech, need various display device for showing image.Flat pannel display (FPD) device such as liquid crystal display (LCD) device, plasma display (PDP) device and Organic Light Emitting Diode (OLED) device has been proposed.
In described FPD device, the LCD device since little, lightweight, the slim body of size and advantage low in energy consumption be used widely.
Comprise with the pixel of matrix arrangement with for the active matrix type display of the open/close on-off element of controlling each pixel and being used widely.Active matrix type display comprises array base palte, is formed with grid line, data line, on-off element and pixel electrode at described array base palte.Hereinafter with reference to accompanying drawing array base palte is described.
Fig. 1 is that expression is according to the planimetric map of the array base palte that is used for display device of prior art.
In Fig. 1, grid line 22 and data line 52 are intersected with each other to limit pixel region P.Thin film transistor (TFT) T and grid line 22 are connected with data line and are connected.
Thin film transistor (TFT) T comprises grid 24, active layer 42, source electrode 54 and drains 56.Grid 24 is connected with grid line 22, and source electrode 54 is connected with data line 52, and drains and 56 separate with source electrode 54.Active layer 42 is at source electrode 54 and drain and be exposed between 56, and the expose portion of active layer 42 becomes the raceway groove of thin film transistor (TFT) T.
With reference to the cross section structure of Fig. 2 description according to the array base palte that is used for display device of prior art.
Fig. 2 be expression according to the sectional view of the array base palte that is used for display device of prior art, and Fig. 2 is corresponding to the cross section along the II-II line intercepting of Fig. 1.
Among Fig. 2, be formed with grid line 22 and the grid 24 that is connected with grid line 22 at substrate 10, and be formed with gate insulation layer 30 at grid line 22 and grid 24.
On the gate insulation layer 30 and above grid 24, be formed with the active layer 42 of intrinsic silicon, and be formed with the ohmic contact layer 44 of doped silicon at active layer 42.
Be formed with data line 52, source electrode 54 and drain 56 at ohmic contact layer 44.At data line 52, source electrode 54 with drain and 56 be formed with passivation layer 60.Passivation layer 60 comprises the drain contact hole 62 that exposes drain electrode 56.
Be formed with pixel electrode 72 at passivation layer 60, and pixel electrode 72 is connected with drain electrode 56 by drain contact hole 62.
Recently, because display device is required to have large scale and high definition, so the length of the signal wire such as grid line 22 and data line 52 becomes longer.So the resistance of signal wire increases, and causes signal delay.In addition, because the actuating speed raising, so impose on the load rise of signal wire.For addressing these problems, people have carried out various trials.
For example, can reduce the resistance of signal wire by the width of widening signal wire.In this case, because the area of pixel region reduces, aperture ratio is reduced and the brightness reduction.Here, brightness can improve by the amount that increases the light of supplying with.Yet this raises power consumption, and luminescence efficiency reduces.
Alternately, can reduce the resistance of signal wire by the thickness of thickening signal wire.Yet, signal wire by deposit metallic material with form metal level and optionally the described metal level of composition (pattern) form.So, in order to thicken the thickness of signal wire, should thicken the thickness of described metal level, and then also increase for the amount of the metal material that deposits.In addition, the amount that is used for the etching agent of the described metal level of composition also increases.Therefore, the manufacturing cost of array base palte improves.
Simultaneously, some metal material has bad performance aspect substrate contacts, and when these metal materials form thickly, may rupture or peel off from substrate.Therefore, the increase of signal wire thickness has limit.
Summary of the invention
Therefore, the present invention relates to a kind of manufacture method of array base palte and the described array base palte for display device, described array base palte and manufacture method have been eliminated the one or more problems that cause owing to the limitation of prior art and defective basically.
An advantage of the present invention has been to provide a kind of can reduce the array base palte that is used for display device of signal wire resistance and the manufacture method of described array base palte.
Another advantage of the present invention has been to provide a kind of can improve the array base palte that is used for display device of aperture ratio and brightness and the manufacture method of described array base palte.
Other characteristics of the present invention and advantage will be illustrated in the following description, and a part wherein is apparent from instructions, maybe can be by enforcement of the present invention is learned.These and other advantages of the present invention can realize by the structure of specifically noting in instructions, claims and the accompanying drawing and obtain.
For realizing these and other advantages, purpose according to the embodiment of the present invention, as and general description concrete at this, a kind of array base palte for display device comprises: substrate; Grid line, described grid line is formed on the described substrate along first direction; Data line, described data line is formed on the top of described substrate along second direction, and wherein said data line and described grid line are intersected with each other to limit pixel region; Thin film transistor (TFT), described thin film transistor (TFT) is formed in the described pixel region, and have drain electrode, the grid that is connected with described grid line and the source electrode that is connected with described data line; Pixel electrode, described pixel electrode is formed in the described pixel region, and is connected with described drain electrode; The first auxiliary grid pattern, described the first auxiliary grid pattern are formed on the top of described grid line and contact with described grid line; And the first auxiliary data pattern, described the first auxiliary data pattern is formed on the top of described data line and contacts with described data line.
In addition, the array base palte that more than is used for display device can further comprise: gate insulation layer, described gate insulation layer cover described grid line and described grid, and below described data line; Passivation layer, described passivation layer are formed on described data line and the described gate insulation layer; The first contact hole, described the first contact hole is formed in described passivation layer and the described gate insulation layer, and exposes described grid line along described first direction; And second contact hole, described the second contact hole is formed in the described passivation layer, and exposes described data line along described second direction, and wherein said the first auxiliary grid pattern can be formed in described the first contact hole; And described the first auxiliary data pattern can be formed in described the second contact hole.
In addition, the array base palte that more than is used for display device can further comprise: the drain electrode contact patterns, wherein said passivation layer can further be formed in the described drain electrode and comprise drain contact hole, described drain electrode contact patterns can be formed in the described drain contact hole and contact described drain electrode, and described pixel electrode can cover and contact described drain electrode contact patterns.
In addition, the array base palte that more than is used for display device can further comprise: the second auxiliary grid pattern, described the second auxiliary grid pattern are formed on described the first auxiliary grid pattern, to cover, to contact and protect described the first auxiliary grid pattern; And the second auxiliary data pattern, described the second auxiliary data pattern is formed on described the first auxiliary data pattern, to cover, to contact and protect described the first auxiliary data pattern.
In addition, at above array base palte for display device, described the second auxiliary grid pattern can be formed by the material identical with the material of described pixel electrode with described the second auxiliary data pattern.
In addition, at above array base palte for display device, described the first auxiliary grid pattern and described the first auxiliary data pattern can form by plating method (plating).
In addition, at above array base palte for display device, described drain electrode contact patterns, described the first auxiliary grid pattern and described the first auxiliary data pattern can form by the plating method.
In addition, at above array base palte for display device, described the first auxiliary grid pattern and described the first auxiliary data pattern can be formed by copper, chromium or nickel.
In addition, at above array base palte for display device, described drain electrode contact patterns, described the first auxiliary grid pattern and described the first auxiliary data pattern can be formed by copper, chromium or nickel.
In addition, at above array base palte for display device, described the first auxiliary data pattern can be integrally formed along described data line.
In addition, the array base palte that more than is used for display device can further comprise: concentric line, and described concentric line is formed between the adjacent grid line, and parallel with described grid line, and wherein said gate insulation layer can further cover described concentric line; Capacitance electrode, described capacitance electrode is formed on the top of described concentric line, and the described capacitance electrode that overlaps each other and described concentric line form holding capacitor with the described gate insulation layer between described capacitance electrode and described concentric line; And electric capacity contact patterns, wherein said passivation layer can further be formed on the described capacitance electrode, and described passivation layer comprises the electric capacity contact hole, described electric capacity contact patterns can be formed in the described electric capacity contact hole and contact described capacitance electrode, and described pixel electrode can cover and contact described electric capacity contact patterns.
In addition, at above array base palte for display device, described drain electrode contact patterns, described the first auxiliary grid pattern, described the first auxiliary data pattern and described electric capacity contact patterns can form by the plating method.
In addition, at above array base palte for display device, described drain electrode contact patterns, described the first auxiliary grid pattern, described the first auxiliary data pattern and described electric capacity contact patterns can be formed by copper, chromium or nickel.
In addition, at above array base palte for display device, each can comprise the first plating layer of being formed by copper and the second plating layer that is formed by nickel on described the first plating layer described the first auxiliary grid pattern and described the first auxiliary data pattern, and described the second plating layer is thinner than described the first plating layer.
On the other hand, the method that a kind of manufacturing is used for the array base palte of display device may further comprise the steps: form grid line along first direction on substrate, and form grid at described substrate, wherein said grid extends from described grid line; Form the gate insulation layer that covers described grid line and described grid; Above described the above grid of gate insulation layer, form active layer, form ohmic contact layer at described active layer; On described gate insulation layer, form data line along second direction, and form source electrode and drain electrode at described ohmic contact layer, wherein said data line and described grid line are intersected with each other to limit pixel region, described source electrode extends from described data line, and described drain electrode and described source electrode are separated above described grid; Form the first auxiliary grid pattern contacting described grid line, and form the first auxiliary data pattern to contact described data line; And in described pixel region, forming pixel electrode, described pixel electrode is connected with described drain electrode.
In addition, above method can further may further comprise the steps: form passivation layer in described data line, described source electrode and described drain electrode; And in described passivation layer and described gate insulation layer, form the first contact hole to expose described grid line, and in described passivation layer, form the second contact hole to expose described data line, wherein said the first auxiliary grid pattern can be formed in described the first contact hole, and described the first auxiliary data pattern can be formed in described the second contact hole.
In addition, above method can further may further comprise the steps: form drain contact hole in described passivation layer, to expose described drain electrode; And in described drain contact hole, form the drain electrode contact patterns, to contact described drain electrode.
In addition, in the step that forms pixel electrode, can form the second auxiliary grid pattern at described the first auxiliary grid pattern, to cover and to contact described the first auxiliary grid pattern, and can form the second auxiliary data pattern at the first auxiliary data pattern, to cover and to contact described the first auxiliary data pattern.
In addition, in above method, described the second auxiliary grid pattern can be formed by the material identical with the material of described pixel electrode with described the second auxiliary data pattern.
In addition, in the step that forms grid line, can between adjacent grid line and with described grid line, form abreast concentric line; In the step that forms gate insulation layer, described gate insulation layer can further cover described concentric line; In the step that forms active layer, can above described concentric line, form capacitance electrode, and the described capacitance electrode that overlaps each other and described concentric line can form with the described gate insulation layer between described capacitance electrode and described concentric line holding capacitor; In the step that forms drain contact hole, the electric capacity contact hole can be formed, to expose described capacitance electrode in described passivation layer; In the step that forms the first auxiliary grid pattern, the electric capacity contact patterns can be formed, to contact described capacitance electrode in described electric capacity contact hole; And in the step that forms pixel electrode, described pixel electrode can further cover and contact described electric capacity contact patterns.
In addition, in above method, described the first auxiliary grid pattern and described the first auxiliary data pattern can form by the plating method.
In addition, in above method, described drain electrode contact patterns, described the first auxiliary grid pattern and described the first auxiliary data pattern can form by the plating method.
In addition, in above method, described electric capacity contact patterns, described drain electrode contact patterns, described the first auxiliary grid pattern and described the first auxiliary data pattern can form by the plating method.
In addition, in above method, described the first auxiliary grid pattern and described the first auxiliary data pattern can be formed by copper, chromium or nickel.
In addition, in above method, described drain electrode contact patterns, described the first auxiliary grid pattern and described the first auxiliary data pattern can be formed by copper, chromium or nickel.
In addition, in above method, described electric capacity contact patterns, described drain electrode contact patterns, described the first auxiliary grid pattern and described the first auxiliary data pattern can be formed by copper, chromium or nickel.
In addition, in above method, described the first auxiliary data pattern can be integrally formed along described data line.
In addition, in above method, form described the first auxiliary grid pattern and described the first auxiliary data pattern and can comprise and form the first plating layer of being formed by copper and form the second plating layer that is formed by nickel at described the first plating layer, and wherein said the second plating layer is thinner than described the first plating layer.
The general description and the following detailed description that it should be understood that the front all are exemplary and explanatory, are intended to claimed the invention provides further specified.
Description of drawings
Included accompanying drawing is used to provide a further understanding of the present invention, and accompanying drawing is incorporated in the present specification and consists of the part of present specification.Accompanying drawing shows embodiments of the present invention, and is used from explanation principle of the present invention with instructions one.
In the accompanying drawings:
Fig. 1 is that expression is according to the planimetric map of the array base palte that is used for display device of prior art;
Fig. 2 be expression according to the sectional view of the array base palte that is used for display device of prior art, and Fig. 2 is corresponding to the cross section along the II-II line intercepting of Fig. 1;
Fig. 3 is that expression is according to the planimetric map of the array base palte that is used for display device of exemplary embodiment of the invention;
Fig. 4 is the sectional view along the IV-IV line intercepting of Fig. 3;
Fig. 5 A to Fig. 5 D is that expression is according to the planimetric map of the array base palte in each step of the method for exemplary embodiment of the invention manufacturing array substrate;
Fig. 6 A to Fig. 6 F be expression according to the sectional view of the array base palte in each step of the method for exemplary embodiment of the invention manufacturing array substrate, and Fig. 6 A to Fig. 6 F is corresponding to the cross section along the VI-VI line intercepting of Fig. 5 A to Fig. 5 D;
Fig. 7 is that expression is according to the process flow diagram without electric plating (electroless plating) method technique of the present invention;
Fig. 8 is that expression is according to another sectional view for the array base palte of display device of exemplary embodiment of the invention;
Fig. 9 is the planimetric map of the array base palte that is used for display device of expression another embodiment according to the present invention; And
Figure 10 is the sectional view along the IX-IX line intercepting of Fig. 9.
Embodiment
Now will be described with reference to embodiments of the present invention in detail, some examples wherein are shown in the drawings.
Fig. 3 is that expression is according to the planimetric map of the array base palte that is used for display device of exemplary embodiment of the invention.Fig. 4 is the sectional view along the IV-IV line intercepting of Fig. 3.
In Fig. 3 and Fig. 4, be formed with grid line 122 and the grid 124 of conductive material in transparent insulation substrate 110.Grid line 122 forms along first direction, and grid 124 extends from grid line 122.Between adjacent grid line 122, be formed with concentric line 126, and concentric line 126 is parallel with grid line 122.
Be formed with the gate insulation layer 130 of silicon nitride or monox at grid line 122, grid 124 and concentric line 126, and gate insulation layer 130 covers grid line 122, grid 124 and concentric lines 126.
On the gate insulation layer 130 and above grid 124, be formed with the active layer 142 of intrinsic amorphous silicon.Be formed with the ohmic contact layer 144 of doped amorphous silicon at active layer 142.
Be formed with data line 152, the source electrode 154 of the conductive material such as metal and drain 156 at ohmic contact layer 144.Data line 152 forms along the second direction vertical with first direction, and data line 152 intersects with grid line 122 and concentric line 126.Data line 152 limits pixel region P with grid line 122.Source electrode 154 extends from data line 152, and drain 156 and source electrode 154 above grid 124, separate.Be formed with capacitance electrode 158 on the gate insulation layer 130 and above concentric line 126, and capacitance electrode 158 is formed by the material identical with 156 the material of draining with data line 152, source electrode 154.Here, be formed with intrinsic silicon pattern and doped silicon pattern at data line 152 and capacitance electrode 158 below each.
In drain contact hole 162, be formed with drain electrode contact patterns 172, and should the 172 contact drain electrodes 156 of drain electrode contact patterns.In electric capacity contact hole 164, be formed with electric capacity contact patterns 174, and these electric capacity contact patterns 174 hand capacity electrodes 158.In the first contact hole 166, be formed with the first auxiliary grid pattern 176, and these the first auxiliary grid pattern 176 contact grid lines 122.In the second contact hole 168, be formed with the first auxiliary data pattern 178, and these the first auxiliary data pattern 178 contact data lines 152.
Drain electrode contact patterns 172, electric capacity contact patterns 174, the first auxiliary grid pattern 176 and the first auxiliary data pattern 178 form by the plating method, and difference filling contact hole 162,164,166 and 168.Drain electrode contact patterns 172, electric capacity contact patterns 174, the first auxiliary grid pattern 176 and the first auxiliary data pattern 178 can have the height identical with passivation layer 160, perhaps can exceed passivation layer 160.Drain electrode contact patterns 172, electric capacity contact patterns 174, the first auxiliary grid pattern 176 can have identical thickness with the first auxiliary data pattern 178, and therefore drain contact patterns 172, electric capacity contact patterns 174 and the first auxiliary data pattern 178 comparable the first auxiliary grid patterns 176 more exceed passivation layer 160.
In embodiments of the present invention, when forming drain contact hole 162 and electric capacity contact hole 164, form expose respectively grid line 122 and data line 152 the first contact hole 166 and the second contact hole 168, and in this first contact hole 166 and the second contact hole 168, form respectively the first auxiliary grid pattern 176 and the first auxiliary data pattern 178.Thus, can reduce the resistance of grid line 122 and data line 152.Therefore, signal delay can be prevented, and load can be reduced.In addition, the width of grid line 122 and data line 152 can be reduced, and aperture ratio and brightness can be improved.
Describe the method for manufacturing array substrate in detail with reference to Fig. 5 A to Fig. 5 D, Fig. 6 A to Fig. 6 F, Fig. 3 and Fig. 4.Fig. 5 A to Fig. 5 D is that expression is according to the planimetric map of the array base palte in each step of the method for exemplary embodiment of the invention manufacturing array substrate.Fig. 6 A to Fig. 6 F be expression according to the sectional view of the array base palte in each step of the method for exemplary embodiment of the invention manufacturing array substrate, and Fig. 6 A to Fig. 6 F is corresponding to the cross section along the VI-VI line intercepting of Fig. 5 A to Fig. 5 D.
In Fig. 5 A and Fig. 6 A, by utilizing sputtering method to deposit conductive material such as metal, and come the described conductive material of composition by the photoetching process of having utilized photomask, form grid line 122, grid 124 and concentric lines 126 in the transparent insulation substrate 110 such as glass or plastics thus.Grid line 122 forms along first direction, and concentric line 126 is arranged between the adjacent grid line 122 and parallel with grid line 122.Grid 124 extends from grid line 122.
In Fig. 5 B and Fig. 6 B to Fig. 6 D, form gate insulation layer 130 at grid line 122, grid 124 and concentric line 126, then form active layer 142, ohmic contact layer 144, data line 152, source electrode 154, drain electrode 156 and capacitance electrode 158 by the photoetching process of having utilized photomask at gate insulation layer 130.
This will describe in following content in more detail.
In Fig. 6 B, on grid line 122, grid 124 and concentric line 126, sequentially form gate insulation layer 130, intrinsic silicon layer 140, doped silicon layer 141 and metal level 150.Here, gate insulation layer 130, intrinsic silicon layer 140 and doped silicon layer 141 can form by the chemical vapor deposition (CVD) method.Metal level 150 can form by the physical vapor deposition (PVD) method such as sputter.Gate insulation layer 130 can be by silicon nitride (SiNx) or monox (SiO
2) form.Intrinsic silicon layer 140 can be formed by intrinsic amorphous silicon, and doped silicon layer 141 can be formed by boron-doping or phosphorus-doped amorphous silicon.Metal level 150 can be formed by aluminium, molybdenum, nickel, chromium, copper or their alloy.Here, because copper has relatively low resistivity, so use copper can more effectively reduce the resistance of line and prevent signal delay.When using copper, can be below the copper layer formation cushion, to improve the surface nature with substrate 110.Cushion 110 can be formed by molybdenum, titanium, tantalum or their alloy.
Form the photoresist layer (not shown) at metal level 150, and mask M is set above this photoresist layer.Mask M comprises shading light part BA for shading light, is used for the transmitted light part TA of transmitted light and is used for the partly half transmitting light part HTA of transmitted light.Half transmitting light part HTA can comprise semitransparent layer or a plurality of slit.
Next, the light such as ultraviolet ray is by mask M photolithography glue-line, and photoresist layer is exposed.Photoresist layer after the exposure is developed, thereby form the first photoetching agent pattern 192 and the second photoetching agent pattern 194.The first photoetching agent pattern 192 is corresponding with the shading light part BA of mask M, and has the first thickness.The second photoetching agent pattern 194 is corresponding with half transmitting light part HTA, and has the second thickness than the first thin thickness.The second photoetching agent pattern 194 is arranged on the top of grid 124, and the first photoetching agent pattern is arranged on the both sides of the second photoetching agent pattern 194 and the top of concentric line 126.
In Fig. 6 C, come sequentially metal level 150, the doped silicon layer 141 of Fig. 6 B and the intrinsic silicon layer 140 of Fig. 6 B of etching Fig. 6 B by the first photoetching agent pattern 192 and the second photoetching agent pattern 194 that utilizes Fig. 6 B as etching mask, thereby form data line 152, source drain pattern 150a, doped semiconductor pattern 141a, active layer 142 and capacitance electrode 158.Here, can carry out wet etching to the metal level 150 of Fig. 6 B by mordant, can carry out dry etching to the doped silicon layer 141 of Fig. 6 B and the intrinsic silicon layer 140 of Fig. 6 B by etching gas.
Then, remove the second photoetching agent pattern 194 of Fig. 6 B by ashing (ashing) technique, thereby expose the source drain pattern 150a of grid 124 tops.At this moment, the first photoetching agent pattern 192 is partly removed, and the thickness of this first photoetching agent pattern 192 reduces.
In Fig. 6 D, come the source drain pattern 150a of etching Fig. 6 C and the doped semiconductor pattern 141a of Fig. 6 C by the first photoetching agent pattern 192 with Fig. 6 C as etching mask, thereby form source electrode 154 and drain electrode 156 and ohmic contact layer 144, and expose active layer 142.Source electrode 154 is connected with data line 152, and drains 156 in the face of source electrode 154 and separate with source electrode 154 with respect to grid 124.
Next, remove the first photoetching agent pattern 192.
Here, by forming active layer 142 with photoetching process that to form data line 152, source electrode 154 identical with 156 the photoetching process of draining.Also can be by forming active layer 142 from photoetching process that to form data line 152, source electrode 154 different with 156 the photoetching process of draining.
Then, in Fig. 5 C and Fig. 6 E, form passivation layer 160 by the inorganic insulating material of deposition such as silicon nitride or monox, and come composition passivation layer 160 by the photoetching process of having utilized photomask, thereby form drain contact hole 162, electric capacity contact hole 164, the first contact hole 166 and the second contact hole 168.At this moment, the gate insulation layer 130 corresponding with the first contact hole 166 also optionally removed.Drain contact hole 162 exposes drain electrode 156, and electric capacity contact hole 164 exposes capacitance electrode 158.The grid line 122 that the first contact hole 166 exposes between the adjacent data line 152, and the data line 152 that the second contact hole 168 exposes between the adjacent grid line 122.
Simultaneously, passivation layer 160 can be formed by the organic insulation such as acryl resin, and in this case, passivation layer 160 has flat top surface.
In Fig. 5 D and Fig. 6 F, in drain contact hole 162, electric capacity contact hole 164, the first contact hole 166 and the second contact hole 168, form respectively drain electrode contact patterns 172, electric capacity contact patterns 174, the first auxiliary grid pattern 176 and the first auxiliary data pattern 178 by the plating method.Here, drain electrode contact patterns 172, electric capacity contact patterns 174, the first auxiliary grid pattern 176 and the first auxiliary data pattern 178 can have about 0.2 micron to about 5 microns thickness.Valuably, drain electrode contact patterns 172, electric capacity contact patterns 174, the first auxiliary grid pattern 176 and the first auxiliary data pattern 178 can have about 2 microns to about 3 microns thickness, with the resistance that reduces line and prevent because the orientation problem of the liquid crystal molecule that the step of pattern causes.Drain electrode contact patterns 172, electric capacity contact patterns 174, the first auxiliary grid pattern 176 and the first auxiliary data pattern 178 can be filled respectively drain contact hole 162, electric capacity contact hole 164, the first contact hole 166 and the second contact hole 168, and can exceed passivation layer 160.
Drain electrode contact patterns 172, electric capacity contact patterns 174, the first auxiliary grid pattern 176 and the first auxiliary data pattern 178 can be formed by the conductive material such as copper, chromium or nickel.Valuably, drain electrode contact patterns 172, electric capacity contact patterns 174, the first auxiliary grid pattern 176 and the first auxiliary data pattern 178 can be formed by copper, further to reduce the resistance of line.
In this embodiment of the present invention, the second contact hole 168 can be formed on the top of the data line 152 between the adjacent grid line 122.This second contact hole 168 can be formed on the top of the data line 152 that intersects with grid line 122, and may extend to next pixel region P.The second adjacent contact hole 168 can be connected to each other.Therefore, the first auxiliary data pattern 178 in the second contact hole 168 can be integrally formed along data line 152, further to reduce the resistance of line.In other words, can form continuously whole the first auxiliary data patterns along data line.
Next, in Fig. 3 and Fig. 4, deposit transparent conductive material, and come the described transparent conductive material of composition by the photoetching process of having utilized photomask, thereby form pixel electrode 182, the second auxiliary grid pattern 184 and the second auxiliary data pattern 186.Pixel electrode 182 is arranged on the passivation layer 160 among the pixel region P.Pixel electrode 182 contacts also cover drain electrode contact patterns 172 and electric capacity contact patterns 174, and pixel electrode 182 is electrically connected with drain electrode 156 and capacitance electrode 158.184 contacts of the second auxiliary grid pattern also cover the first auxiliary grid pattern 176, and the second auxiliary data pattern 186 contacts and cover the first auxiliary data pattern 178.Described transparent conductive material can be tin indium oxide or indium zinc oxide.
The second auxiliary grid pattern 184 and the second auxiliary data pattern 186 prevent the oxidation of the first auxiliary grid pattern 176 and the first auxiliary data pattern 178, and protect this first auxiliary grid pattern 176 and the first auxiliary data pattern 178.
Describe according to of the present invention without electric plating method with reference to Fig. 7.Fig. 7 is that expression is according to the process flow diagram without electric plating method technique of the present invention.Will explain as an example to cover copper coating.
In Fig. 7, at first step ST1, for increasing the adhesion between basalis (base layer) and the plating layer, carry out cleaning procedure, remove particle or organic substance, thus the surface of clear base bottom.At this moment, the substrate that the above includes basalis can be exposed to organic solution about 30 seconds, and described basalis can comprise copper.
Then, at second step ST2, carry out adjusting process (conditioning process), remove the oxide film on the basalis.The surface of basalis has polarity, and described polarity for example is (+) polarity just.At this moment, the above's substrate of including basalis can be exposed to and comprise sulfuric acid (H
2SO
4) about 30 seconds of solution.Here, can omit second step ST2.
Next, at third step ST3, carry out activating process (activating process), palladium (Pd) is adsorbed onto the surface of basalis.Palladium plays catalyzer.The substrate that the above includes basalis can be exposed to the acid solution that wherein is dissolved with palladium ion about 60 seconds.The copper of basalis becomes ion owing to the catalytic performance of displaced type (substitution-type) palladium ion loses electronics.Palladium ion reduces and is adsorbed to the surface of basalis.Here, acid solution can be sulfuric acid (H
2SO
4) based sols.
At the 4th step ST4, carry out without electric plating technique, form copper plate at basalis.At this moment, use copper plating solution.Copper plating solution comprises slaine, reductive agent, complexing agent (complexant), stabilizing agent and promoter (exaltant) (in other words rate accelerating material (accelerator)), and copper plating solution is alkalescence (alkali).
Reductive agent offers the copper ion electronics.The electromotive force of reductive agent (potential) can be lower than the equilibrium potential (equilibrium potential) of copper ion.Reductive agent can comprise one of formaldehyde, dimethylamino monoborane (dimethylamine borane, DMAD) and sodium hypophosphite.For example, when using formaldehyde as reductive agent, because the reduction process of formaldehyde can generate hydrogen ion (H+) and hydroxide ion (OH-), and can change the pH value of plating solution.
Complexing agent is combined with copper ion, prevent copper ion and reductive agent the reaction and precipitate.Complexing agent can comprise sodium-potassium tartrate (sodium potassium tartrate), ethylenediamine tetraacetic acid (ethylenediamine tetraacetic acid, EDTA), one of glycollic acid (glycolic acid) and triethanolamine (triethanol amine), described sodium-potassium tartrate can be called as Rochelle (Rochelle) salt.
Stabilizing agent is adsorbed onto on dust (dust) or the copper particle, prevents that copper ion from contacting with reductive agent.Stabilizing agent can comprise one of oxygen, thiocarbamide, 2-mercaptobenzothiazole (2-mercaptobenzothiazole), DECTC (diethyldithiocarbamate) and vanadium pentoxide (vanadium pentoxide).
Promoter (or rate accelerating material) being used for improved plating speed.Promoter can comprise one of prussiate, propionitrile (proprionitrile) and phenanthrolene (O-phenanthroline).
Therefore, when comprising that the exposure of substrates of basalis that absorption has a palladium is to copper plating solution, because the reduction process of reductive agent generates electronics, copper ion is tied to be incorporated on the palladium catalyst with electronics and is separated out (educe), thus the formation copper plate.In addition, the copper of plating plays autocatalysis, and further forms copper plate.
Here, the thickness of copper plate changed according to composition, component ratio and the open-assembly time of copper plating solution.For example, when basalis is exposed to the copper plating solution that comprises formaldehyde, Rochelle salt and 2-mercaptobenzothiazole in the time of about 1200 seconds, can form about 1.5 microns copper plate.
In this embodiment of the present invention, the first auxiliary grid pattern 176 and the first auxiliary data pattern 178 are by forming without electric plating method.The first auxiliary grid pattern 176 and the first auxiliary data pattern 178 also can form by electroplating (electro plating) method.More particularly, for avoid during the manufacturing array substrate static and for after the manufacturing array substrate, to check electric condition, formed the short-circuiting bar (shorting bar) that connects grid line and data line.The first auxiliary grid pattern 176 and the first auxiliary data pattern 178 can form by the electrochemical plating of having utilized short-circuiting bar.
In this embodiment of the present invention, the first auxiliary grid pattern 176 and the first auxiliary data pattern 178 are respectively formed on grid line 122 and the data line 152 by the plating method.Reduce the resistance of grid line 122 and data line 152, and prevented signal delay.The load of line can be reduced.At this moment, because the width of grid line 122 and data line 152 can be reduced, and pixel region P can be extended, so can improve aperture ratio and brightness.Size and the resolution of display device is depended in the raising of aperture ratio.Compared with prior art, aperture ratio can improve about 10% to about 50%, and along with the resolution of display device uprises, can further improve aperture ratio.
Because when forming drain contact hole 162 and electric capacity contact hole 164 and after exposing grid line 122 and data line 152, auxiliary patterns 176 and 178 forms simultaneously by the plating method, so plating grid line 122 is compared with the situation of data line 152 with minute coming, technique be can simplify, manufacturing cost and shortening time reduced.
In addition, if grid line 122 and data line 152 are divided the plating of coming, then grid line 122 and data line 152 are in their cross part branch coating plating twice, and this will have in the cross part office relatively high step.So because the cause of step, the layer that forms on the cross section may disconnect.Yet, in the present invention, because grid line 122 is not in cross part office coating plating, so the layer that can avoid being formed on the cross section disconnects.In addition, the plating if grid line 122 and data line 152 minute come, then the electrode of thin film transistor (TFT) T may be by plating, and this just has the problem such as thin film transistor (TFT) T deteriorated.Yet in the present invention, the electrode of thin film transistor (TFT) T has been avoided this problem not by plating.
Simultaneously, if when form contact hole 162,164 by composition passivation layer 160, contact hole 162,164 166 and 168 time, 166 and 168 side be back taper, then because the cause of back taper step, the layer that forms later may disconnect.Yet in the present invention, metal pattern is formed in the contact hole 162,164,166 and 168 by the plating method.So, even contact hole 162,164,166 and 168 side are back taper, also can prevent the disconnection of the layer that forms later.
In the superincumbent embodiment, the first auxiliary grid pattern 176 and the first auxiliary data pattern 178 have single layer structure.The first auxiliary grid pattern 176 also can have sandwich construction by the different material of plating with the first auxiliary data pattern 178.Especially, when the first auxiliary grid pattern 176 and the first auxiliary data pattern 178 comprise copper, on copper plate, can further form nickel coating so that anti-oxidation and reduce contact resistance with succeeding layer.
This describes with reference to Fig. 8.Fig. 8 is that expression is according to another sectional view for the array base palte of display device of exemplary embodiment of the invention.Identical Reference numeral will be used to refer to the generation parts identical with above embodiment, and will omit the explanation to same parts.
In Fig. 8, each comprises the first plating layer 176a or 178a and the second plating layer 176b or 178b the first auxiliary grid pattern 176 and the first auxiliary data pattern 178.The second plating layer 176b or 178b have the thickness less than the thickness of the first plating layer 176a or 178a.Here, drain electrode contact patterns 172 and electric capacity contact patterns 174 also have the double-decker of the first plating layer 172a or 174a and the second plating layer 172b or 174b.
For example, the first plating layer 172a, 174a, 176a and 178a form by plating copper, and the second plating layer 172b, 174b, 176b and 178b form by plating nickel.The second plating layer 172b, 174b, 176b and 178b prevent that the first plating layer 172a, 174a, 176a and 178a are oxidized, and are reduced in the contact resistance between one of pixel electrode 182, the second auxiliary grid pattern 184 and second auxiliary data pattern 186 and the first plating layer 172a, 174a, 176a or the 178a.
The first plating layer 172a, 174a, 176a and 178a can have more than or equal to about 0.2 micron and be less than or equal to about 5 microns thickness, valuably, can have more than or equal to about 2 microns and be less than or equal to about 3 microns thickness.The second plating layer 172b, 174b, 176b and 178b can have more than or equal to about 0.02 micron and be less than or equal to about 0.1 micron thickness.
In above embodiment of the present invention, the concentric line and the capacitance electrode that overlap each other have consisted of holding capacitor.Alternately, the structure of holding capacitor can change, and this describes with reference to Fig. 9 and Figure 10.
Fig. 9 is the planimetric map of the array base palte that is used for display device of expression another embodiment according to the present invention.Figure 10 is the sectional view along the IX-IX line intercepting of Fig. 9.
In Fig. 9 and Figure 10, be formed with grid line 222 and the grid 224 of conductive material in transparent insulation substrate 210.Grid line 222 forms along first direction, and grid 224 extends from grid line 222.
Be formed with the gate insulation layer 230 of silicon nitride or monox at grid line 222 and grid 224, and gate insulation layer 230 covers grid line 222 and grids 224.
On the gate insulation layer 230 and above grid 224, be formed with the active layer 242 of intrinsic amorphous silicon.Be formed with the ohmic contact layer 244 of doped amorphous silicon at active layer 242.
Be formed with data line 252, the source electrode 254 of the conductive material such as metal and drain 256 at ohmic contact layer 244.Data line 252 forms along the second direction vertical with first direction, and data line 252 intersects to limit pixel region P with grid line 222.Source electrode 254 extends from data line 252, and drain electrode 256 is separated above grid 224 in the face of source electrode 254 and with source electrode 254.On the gate insulation layer 230 and be to be formed with capacitance electrode 258 above the first of grid line 222, and capacitance electrode 258 is by forming with data line 252, source electrode 254 and the 256 identical materials that drain.Here, be formed with intrinsic silicon pattern and doped silicon pattern at data line 252 and capacitance electrode 258 below each.
In drain contact hole 262, be formed with drain electrode contact patterns 272, and should the 272 contact drain electrodes 256 of drain electrode contact patterns.In electric capacity contact hole 264, be formed with electric capacity contact patterns 274, and these electric capacity contact patterns 274 hand capacity electrodes 258.In the first contact hole 266, be formed with the first auxiliary grid pattern 276, and these the first auxiliary grid pattern 276 contact grid lines 222.In the second contact hole 268, be formed with the first auxiliary data pattern 278, and these the first auxiliary data pattern 278 contact data lines 252.
Drain electrode contact patterns 272, electric capacity contact patterns 274, the first auxiliary grid pattern 276 and the first auxiliary data pattern 278 form by the plating method, and difference filling contact hole 262,264,266 and 268.Drain electrode contact patterns 272, electric capacity contact patterns 274, the first auxiliary grid pattern 276 can have the height identical with the height of passivation layer 260 with the first auxiliary data pattern 278, perhaps can exceed passivation layer 260.Drain electrode contact patterns 272, electric capacity contact patterns 274, the first auxiliary grid pattern 276 can have identical thickness with the first auxiliary data pattern 278, and therefore drain contact patterns 272, electric capacity contact patterns 274 and the first auxiliary data pattern 278 comparable the first auxiliary grid patterns 276 more exceed passivation layer 260.
Simultaneously, can omit capacitance electrode 258, in this case, pixel electrode 282 can overlapping grid line 222 to form holding capacitor.
Array base palte according to another embodiment of the present invention can be made by the technique of Fig. 5 A to Fig. 5 D, Fig. 6 A to Fig. 6 F, Fig. 3 and Fig. 4.
In the manufacture method of array base palte according to the present invention and this array base palte, be formed with auxiliary patterns at grid line and data line.So, can reduce the resistance of line, and can prevent signal delay.Can reduce the load of line.In addition, the width of line be can reduce, and aperture ratio and brightness improved.At this moment, littlely on grid line and data line, form simultaneously auxiliary patterns by plating technique, simplified technique.Reduce manufacturing cost and shortened the time.
Simultaneously, not by plating, the layer that can avoid being formed on the cross section top disconnects grid line in the cross part office of grid line and data line.In addition, the electrode of thin film transistor (TFT) is not by plating.So, can avoid thin film transistor (TFT) deteriorated.
Can make various modifications and variations to the present invention in the situation that does not break away from the spirit or scope of the present invention, this will be readily apparent to persons skilled in the art.Therefore, the present invention is intended to contain the various modifications and variations of the present invention in the scope that is included into appended claims and its equivalent.
Claims (28)
1. array base palte that is used for display device, described array base palte for display device comprises:
Substrate;
Grid line, described grid line is formed on the described substrate along first direction;
Data line, described data line is formed on the top of described substrate along second direction, and wherein said data line and described grid line are intersected with each other to limit pixel region;
Thin film transistor (TFT), described thin film transistor (TFT) is formed in the described pixel region, and the source electrode that has drain electrode, the grid that is connected with described grid line and be connected with described data line;
Pixel electrode, described pixel electrode is formed in the described pixel region, and is connected with described drain electrode;
The first auxiliary grid pattern, described the first auxiliary grid pattern are formed on the top of described grid line and contact with described grid line; And
The first auxiliary data pattern, described the first auxiliary data pattern are formed on the top of described data line and contact with described data line.
2. the array base palte for display device according to claim 1 further comprises:
Gate insulation layer, described gate insulation layer cover described grid line and described grid, and below described data line;
Passivation layer, described passivation layer are formed on described data line and the described gate insulation layer;
The first contact hole, described the first contact hole is formed in described passivation layer and the described gate insulation layer, and exposes described grid line along described first direction; And
The second contact hole, described the second contact hole is formed in the described passivation layer, and exposes described data line along described second direction,
Wherein said the first auxiliary grid pattern is formed in described the first contact hole; And described the first auxiliary data pattern is formed in described the second contact hole.
3. the array base palte for display device according to claim 2, further comprise the drain electrode contact patterns, wherein said passivation layer further is formed in the described drain electrode and comprises drain contact hole, described drain electrode contact patterns is formed in the described drain contact hole and contacts described drain electrode, and described pixel electrode covers and contact described drain electrode contact patterns.
4. the array base palte for display device according to claim 1 further comprises:
The second auxiliary grid pattern, described the second auxiliary grid pattern are formed on described the first auxiliary grid pattern, to cover, to contact and protect described the first auxiliary grid pattern; And
The second auxiliary data pattern, described the second auxiliary data pattern are formed on described the first auxiliary data pattern, to cover, to contact and protect described the first auxiliary data pattern.
5. the array base palte for display device according to claim 4, wherein said the second auxiliary grid pattern is to be formed by the material identical with described pixel electrode with described the second auxiliary data pattern.
6. the array base palte for display device according to claim 1 and 2, wherein said the first auxiliary grid pattern and described the first auxiliary data pattern form by the plating method.
7. the array base palte for display device according to claim 3, wherein said drain electrode contact patterns, described the first auxiliary grid pattern and described the first auxiliary data pattern form by the plating method.
8. the array base palte for display device according to claim 1 and 2, wherein said the first auxiliary grid pattern and described the first auxiliary data pattern are formed by copper, chromium or nickel.
9. the array base palte for display device according to claim 3, wherein said drain electrode contact patterns, described the first auxiliary grid pattern and described the first auxiliary data pattern are formed by copper, chromium or nickel.
10. according to claim 1,2 or 3 described array base paltes for display device, wherein said the first auxiliary data pattern is integrally formed along described data line.
11. the array base palte for display device according to claim 3 further comprises:
Concentric line, described concentric line is formed between the adjacent grid line, and parallel with described grid line, and wherein said gate insulation layer further covers described concentric line;
Capacitance electrode, described capacitance electrode is formed on the top of described concentric line, and the described capacitance electrode that wherein overlaps each other and described concentric line form holding capacitor with the described gate insulation layer between described capacitance electrode and described concentric line; And
The electric capacity contact patterns,
Wherein said passivation layer further is formed on the described capacitance electrode, and described passivation layer comprises the electric capacity contact hole, described electric capacity contact patterns is formed in the described electric capacity contact hole and contacts described capacitance electrode, and described pixel electrode covers and contact described electric capacity contact patterns.
12. the array base palte for display device according to claim 11, wherein said drain electrode contact patterns, described the first auxiliary grid pattern, described the first auxiliary data pattern and described electric capacity contact patterns form by the plating method.
13. the array base palte for display device according to claim 11, wherein said drain electrode contact patterns, described the first auxiliary grid pattern, described the first auxiliary data pattern and described electric capacity contact patterns are formed by copper, chromium or nickel.
14. the array base palte for display device according to claim 1, each comprises the first plating layer of being formed by copper and the second plating layer that is formed by nickel on described the first plating layer wherein said the first auxiliary grid pattern and described the first auxiliary data pattern, and described the second plating layer is thinner than described the first plating layer.
15. a manufacturing is used for the method for the array base palte of display device, said method comprising the steps of:
Form grid line along first direction on substrate, and form grid at described substrate, wherein said grid extends from described grid line;
Form the gate insulation layer that covers described grid line and described grid;
On described gate insulation layer and above described grid, form active layer, form ohmic contact layer at described active layer;
On described gate insulation layer, form data line along second direction, and form source electrode and drain electrode at described ohmic contact layer, wherein said data line and described grid line are intersected with each other to limit pixel region, described source electrode extends from described data line, and described drain electrode and described source electrode are separated above described grid;
Form the first auxiliary grid pattern contacting described grid line, and form the first auxiliary data pattern to contact described data line; And
Form pixel electrode in described pixel region, described pixel electrode is connected with described drain electrode.
16. method according to claim 15 further may further comprise the steps:
Form passivation layer in described data line, described source electrode and described drain electrode; And
In described passivation layer and described gate insulation layer, form the first contact hole, exposing described grid line, and in described passivation layer, form the second contact hole, exposing described data line,
Wherein said the first auxiliary grid pattern is formed in described the first contact hole, and described the first auxiliary data pattern is formed in described the second contact hole.
17. method according to claim 16 further may further comprise the steps:
In described passivation layer, form drain contact hole, to expose described drain electrode; And
In described drain contact hole, form the drain electrode contact patterns, to contact described drain electrode.
18. method according to claim 15, wherein in the step that forms pixel electrode, form the second auxiliary grid pattern at described the first auxiliary grid pattern, to cover and to contact described the first auxiliary grid pattern, and form the second auxiliary data pattern at described the first auxiliary data pattern, to cover and to contact described the first auxiliary data pattern.
19. method according to claim 18, wherein said the second auxiliary grid pattern is formed by the material identical with described pixel electrode with described the second auxiliary data pattern.
20. method according to claim 17, wherein:
In the step that forms grid line, between adjacent grid line and with described grid line, form abreast concentric line;
In the step that forms gate insulation layer, described gate insulation layer further covers described concentric line;
In forming the step of active layer, above described concentric line, form capacitance electrode, and the described capacitance electrode that overlaps each other and described concentric line have formed holding capacitor with the described gate insulation layer between described capacitance electrode and described concentric line;
In the step that forms drain contact hole, in described passivation layer, form the electric capacity contact hole, to expose described capacitance electrode;
In the step that forms the first auxiliary grid pattern, in described electric capacity contact hole, form the electric capacity contact patterns, to contact described capacitance electrode; And
In the step that forms pixel electrode, described pixel electrode further covers and contacts described electric capacity contact patterns.
21. method according to claim 15, wherein said the first auxiliary grid pattern and described the first auxiliary data pattern form by the plating method.
22. method according to claim 17, wherein said drain electrode contact patterns, described the first auxiliary grid pattern and described the first auxiliary data pattern form by the plating method.
23. method according to claim 20, wherein said electric capacity contact patterns, described drain electrode contact patterns, described the first auxiliary grid pattern and described the first auxiliary data pattern form by the plating method.
24. method according to claim 15, wherein said the first auxiliary grid pattern and described the first auxiliary data pattern are formed by copper, chromium or nickel.
25. method according to claim 17, wherein said drain electrode contact patterns, described the first auxiliary grid pattern and described the first auxiliary data pattern are formed by copper, chromium or nickel.
26. method according to claim 20, wherein said electric capacity contact patterns, described drain electrode contact patterns, described the first auxiliary grid pattern and described the first auxiliary data pattern are formed by copper, chromium or nickel.
27. method according to claim 15, wherein said the first auxiliary data pattern is integrally formed along described data line.
28. method according to claim 15, wherein form described the first auxiliary grid pattern and described the first auxiliary data pattern and comprise and form the first plating layer of being formed by copper and form the second plating layer that is formed by nickel at described the first plating layer, and wherein said the second plating layer is thinner than described the first plating layer.
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| KR10-2011-0082808 | 2011-08-19 | ||
| KR1020120067842A KR101976057B1 (en) | 2011-08-19 | 2012-06-25 | Array substrate for display device and method of fabricating the same |
| KR10-2012-0067842 | 2012-06-25 |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103558722A (en) * | 2013-11-18 | 2014-02-05 | 京东方科技集团股份有限公司 | Array substrate, production method of array substrate and display device |
| CN103680327A (en) * | 2013-12-27 | 2014-03-26 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN103744242A (en) * | 2013-12-30 | 2014-04-23 | 深圳市华星光电技术有限公司 | Thin film transistor liquid crystal display device and signal line thereof |
| CN104091818A (en) * | 2014-06-23 | 2014-10-08 | 上海天马有机发光显示技术有限公司 | OLED panel, device and manufacturing method thereof |
| CN105590936A (en) * | 2014-11-07 | 2016-05-18 | 三星显示有限公司 | Display Device And Method Of Manufacturing The Same |
| CN107045238A (en) * | 2016-02-05 | 2017-08-15 | 三星显示有限公司 | Display device |
| CN107180837A (en) * | 2017-05-17 | 2017-09-19 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof, display device |
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| CN109148381A (en) * | 2018-08-24 | 2019-01-04 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof, display panel, display device |
| CN111474790A (en) * | 2020-05-14 | 2020-07-31 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and liquid crystal display panel |
| WO2021056732A1 (en) * | 2019-09-25 | 2021-04-01 | Tcl华星光电技术有限公司 | Array substrate and preparation method therefor |
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040109121A1 (en) * | 2002-12-10 | 2004-06-10 | Lg.Philips Lcd Co., Ltd. | In-plane switching mode liquid crystal display device and method of fabricating the same |
| US20070034954A1 (en) * | 2005-08-12 | 2007-02-15 | Samsung Electronics Co., Ltd. | Thin film conductor and method of fabrication |
| CN101063781A (en) * | 2006-04-30 | 2007-10-31 | 京东方科技集团股份有限公司 | TFTLCD array substrates device structure and manufacturing method therefor |
| US20090212290A1 (en) * | 2008-02-21 | 2009-08-27 | Samsung Electronics Co., Ltd. | Display panel and method for manufacturing the same |
| US20100265447A1 (en) * | 2006-06-21 | 2010-10-21 | Bum-Sik Seo | Array substrate for in-plane switching mode liquid crystal display device and method of fabricating the same |
| WO2011062400A2 (en) * | 2009-11-17 | 2011-05-26 | 동우 화인켐 주식회사 | Manufacturing method for array substrate for liquid crystal display device |
-
2012
- 2012-08-13 CN CN201210287676.4A patent/CN102955308B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040109121A1 (en) * | 2002-12-10 | 2004-06-10 | Lg.Philips Lcd Co., Ltd. | In-plane switching mode liquid crystal display device and method of fabricating the same |
| US20070034954A1 (en) * | 2005-08-12 | 2007-02-15 | Samsung Electronics Co., Ltd. | Thin film conductor and method of fabrication |
| CN101063781A (en) * | 2006-04-30 | 2007-10-31 | 京东方科技集团股份有限公司 | TFTLCD array substrates device structure and manufacturing method therefor |
| US20100265447A1 (en) * | 2006-06-21 | 2010-10-21 | Bum-Sik Seo | Array substrate for in-plane switching mode liquid crystal display device and method of fabricating the same |
| US20090212290A1 (en) * | 2008-02-21 | 2009-08-27 | Samsung Electronics Co., Ltd. | Display panel and method for manufacturing the same |
| WO2011062400A2 (en) * | 2009-11-17 | 2011-05-26 | 동우 화인켐 주식회사 | Manufacturing method for array substrate for liquid crystal display device |
Cited By (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103558722A (en) * | 2013-11-18 | 2014-02-05 | 京东方科技集团股份有限公司 | Array substrate, production method of array substrate and display device |
| CN103558722B (en) * | 2013-11-18 | 2017-01-25 | 京东方科技集团股份有限公司 | Array substrate, production method of array substrate and display device |
| CN103680327A (en) * | 2013-12-27 | 2014-03-26 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN103680327B (en) * | 2013-12-27 | 2016-03-16 | 京东方科技集团股份有限公司 | Array base palte and display device |
| CN103744242A (en) * | 2013-12-30 | 2014-04-23 | 深圳市华星光电技术有限公司 | Thin film transistor liquid crystal display device and signal line thereof |
| WO2015100755A1 (en) * | 2013-12-30 | 2015-07-09 | 深圳市华星光电技术有限公司 | Thin film transistor liquid crystal display apparatus and signal line thereof |
| CN104091818A (en) * | 2014-06-23 | 2014-10-08 | 上海天马有机发光显示技术有限公司 | OLED panel, device and manufacturing method thereof |
| CN104091818B (en) * | 2014-06-23 | 2017-09-29 | 上海天马有机发光显示技术有限公司 | A kind of organic electroluminescence display panel, device and its manufacture method |
| US9466656B2 (en) | 2014-06-23 | 2016-10-11 | Shanghai Tianma AM-OLED Co., Ltd. | Organic light emitting diode display panel, organic light emitting diode display device, and method for fabricating organic light emitting diode display panel |
| CN105590936A (en) * | 2014-11-07 | 2016-05-18 | 三星显示有限公司 | Display Device And Method Of Manufacturing The Same |
| CN105590936B (en) * | 2014-11-07 | 2021-04-06 | 三星显示有限公司 | Display device and method for manufacturing the same |
| CN107045238A (en) * | 2016-02-05 | 2017-08-15 | 三星显示有限公司 | Display device |
| CN107045238B (en) * | 2016-02-05 | 2021-08-03 | 三星显示有限公司 | Display device |
| CN107527934A (en) * | 2016-06-17 | 2017-12-29 | 三星显示有限公司 | Organic light emitting diode display |
| CN107180837A (en) * | 2017-05-17 | 2017-09-19 | 京东方科技集团股份有限公司 | A kind of array base palte and preparation method thereof, display device |
| CN109148381B (en) * | 2018-08-24 | 2020-11-20 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof, display panel and display device |
| CN109148381A (en) * | 2018-08-24 | 2019-01-04 | 京东方科技集团股份有限公司 | Array substrate and preparation method thereof, display panel, display device |
| WO2021056732A1 (en) * | 2019-09-25 | 2021-04-01 | Tcl华星光电技术有限公司 | Array substrate and preparation method therefor |
| CN111474790A (en) * | 2020-05-14 | 2020-07-31 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and liquid crystal display panel |
| WO2022266925A1 (en) * | 2021-06-24 | 2022-12-29 | 京东方科技集团股份有限公司 | Array substrate, preparation method therefor and display panel |
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