CN102929663A - Method, device and system for loading field programmable gate array - Google Patents
Method, device and system for loading field programmable gate array Download PDFInfo
- Publication number
- CN102929663A CN102929663A CN2012103889051A CN201210388905A CN102929663A CN 102929663 A CN102929663 A CN 102929663A CN 2012103889051 A CN2012103889051 A CN 2012103889051A CN 201210388905 A CN201210388905 A CN 201210388905A CN 102929663 A CN102929663 A CN 102929663A
- Authority
- CN
- China
- Prior art keywords
- buffer area
- data
- programmable gate
- gate array
- field programmable
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The embodiment of the invention discloses a method, a device and a system for loading a field programmable gate array. A cache region is arranged to judge whether the data volume stored by the cache region is within a preset range or not, if yes, the incomplete filled indication of the data volume stored by the cache region is sent to a processor to indicate the processor to continuously transmit data so as to continuously acquire data transmitted through a data bus by the processor, and if not, the to-be-filled indication of the data volume stored by the cache region is sent to the processor to indicate the processor to stop transmitting data. Not only is the reliability of the loading data ensured not to carry away data, but also the fast loading is achieved to avoid the loading gap. Furthermore, data of multiple periods is transmitted through a data bus, and a feedback signal read by an indication signal triggering processor is sent again, so that the method for loading is configured more flexibly, the device for loading is more optimized, and the loading performance of the system for loading the whole field programmable gate array is improved.
Description
Technical field
The present invention relates to electronic technology field, be specifically related to a kind of loading method, Apparatus and system of field programmable gate array.
Background technology
At present, field programmable gate array (Field Programmable Gate Array, being called for short FPGA) technology is widely used in various special ICs, is a highest technology of integrated level, improves one of optimal selection of level of integrated system, reliability for the short run system.The duty of fpga chip is to be arranged by the program among the RAM that leaves in the chip, therefore, needs the RAM in the fpga chip is carried out programmed configurations.The user can adopt different configuration modes to be applied to fpga chip, so power at every turn, needs first fpga chip to be carried out program and loads, and could normally use fpga chip.Therefore, when using fpga chip, the loading technique of data and program is indispensable a kind of application, and loading velocity and load mass are the key indexs that the FPGA technology is used.
In the circuit of existing application fpga chip, in order to save the IO of system port number, generally use passive configuration and realize the program of fpga chip and the loading of data, mainly controlled the layoutprocedure of fpga chip by outer computer or controller.During the configuration, data are sent into fpga chip from outside reservoir part by the data input pin, and 1 clock period is transmitted 1 bit data.No matter the data source of configuration is come wherefrom, come as long as can simulate the configuration sequential of fpga chip needs, configuration data is write fpga chip just passable.After configuration was finished, internal register and I/O pin must carry out initialization, and after by the time initialization was finished, chip just can be according to the function normal operation of user's design.Yet every transmission 1 bit data just need to read feedback signal, and so transfer bus can produce twice transmission operation, has had influence on the loading velocity of data, after also needing in the time of feedback signal to wait the arrival of pending data, loads, and then has produced the loading space.
The existing transmission that also has by time-delay design cancellation feedback signal, guarantee to write again new data after current data has been written in the delay time, although alleviated the operation burden of transfer bus, promoted to a certain extent loading velocity, loaded the space yet still can produce, loaded simultaneously reliability and decrease, data writing very easily occurs delay is arranged, surpass preset value time delay, and then load data and washed out and cause whole the loading unsuccessfully, reduced loading efficiency.
Summary of the invention
The embodiment of the invention provides a kind of loading method, Apparatus and system of field programmable gate array, and the loading velocity that has solved existing field programmable gate array hangs down and the low problem of load mass.
The loading method of a kind of field programmable gate array that the first aspect of the embodiment of the invention provides comprises:
Obtain the data that processor sends;
Whether the data volume of judging buffer area storage in preset range, if so, is stored to buffer area with described data, and notifies described processor to continue the transmission of data;
And, the data in the described buffer area are loaded on described field programmable gate array.
In the possible implementation of the first, whether the described data volume of judging that buffer area is stored comprises in preset range:
Judge that the data volume of buffer area storage whether less than the waterline value L of described buffer area, if so, confirms that then the data volume of buffer area storage is in preset range; The waterline value L of described buffer area is for the operating position of the storage space that identifies described buffer area.
In conjunction with the possible implementation of the first of first aspect, in the second possibility implementation, described method also comprises:
If the data volume of described buffer area storage then sends described buffer area memory data output and will completely indicate to described processor more than or equal to the waterline value L of described buffer area, stop to transmit data to indicate described processor;
Continue to judge that data volume that buffer area stores is whether less than the waterline value L of described buffer area.
In conjunction with the first of first aspect, first aspect possible implementation or the possible implementation of the second, in the third possible implementation, describedly notify described processor to continue the transmission of data to comprise:
Send described buffer area memory data output less than indicating to described processor, continue to transmit data to indicate described processor.
In conjunction with the possible implementation of the first of first aspect, in the 4th kind of possible implementation, describedly obtain the data that described processor sends and comprise:
Obtain the data that described processor transmits in n cycle T by data bus, described n〉0, described T〉0.
In conjunction with the 4th kind of possible implementation of first aspect, in the 5th kind of possible implementation, describedly data in the described buffer area be loaded on described field programmable gate array comprise:
Data communication device in the described buffer area is crossed loaded line take t as the cycle, and 1bits/t is that loading velocity is loaded on described field programmable gate array, and described t is greater than 0.
In conjunction with the 5th kind of possible implementation of first aspect, in the 6th kind of possible implementation, the maximal value of the data volume of described buffer area storage is Hmax, and then n need satisfy inequality 0＜N/T*nT-(n+1) T/t＜Hmax; Wherein, described N is the data volume that transmits in the described cycle T.
In the 6th kind of possible implementation in conjunction with first aspect, in the 7th kind of possible implementation, whether the described data volume of judging the storage of described buffer area comprises less than the waterline value L of described buffer area:
Judge whether the n value satisfies pre-conditioned, described pre-conditioned be 0＜N/T*nT-(n+1) T/t＜L;
If so, determine that then the data volume of described buffer area storage is less than the waterline value L of described buffer area; If not, determine that then the data volume of described buffer area storage is more than or equal to the waterline value L of described buffer area.
The 7th kind of possible implementation in conjunction with first aspect, in the 8th kind of possible implementation, described n satisfies inequality 0＜N/T*nT-(n+1) T/t＜Hleft, with satisfy data that described buffer area obtains in next n cycle T less than and equal described Hleft, described Hleft is that the maximal value of the data volume of described buffer area storage is the difference of the waterline value L of Hmax and described buffer area.
The 5th kind of possible implementation in conjunction with first aspect, in the 9th kind of possible implementation, the waterline value L of described buffer area need satisfy inequality L〉2T/t, with satisfy described buffer area by described loaded line take t as the cycle, 1bits/t is that loading velocity loads data continuously to described field programmable gate array.
The second aspect of the embodiment of the invention provides a kind of charger of field programmable gate array, comprising:
Acquiring unit is used for obtaining the data that processor sends;
Judging unit is used for judging that data volume that buffer area stores is whether in preset range;
Described buffer area, being used for according to described judgment unit judges is the described data of result store that are;
Transmitting element, being used for according to described judgment unit judges is that the result who is sends notice to described processor, continues to transmit data to notify described processor;
Described transmitting element also is used for the data of described buffer area are loaded on described field programmable gate array.
In the possible implementation of the first, described judging unit, whether the concrete data volume that is used for judging the buffer area storage less than the waterline value L of described buffer area, if so, confirms that then the data volume that buffer area is stored is in preset range; The waterline value L of described buffer area is for the operating position of the storage space that identifies described buffer area.
In conjunction with the possible implementation of the first of second aspect, in the possible implementation of the second, described transmitting element, also being used for according to described judgment unit judges is no result, send described buffer area memory data output and will completely indicate to described processor, stop to transmit data to indicate described processor;
Described judging unit, also being used for according to described judgment unit judges is no result, continues to judge that data volume that described buffer area stores is whether less than the waterline value L of described buffer area.
In conjunction with the possible implementation of the first of second aspect, second aspect or the possible implementation of the second of second aspect, in the third possible implementation, described transmitting element, concrete being used for according to described judgment unit judges is that the result who is sends described buffer area memory data output less than indicating to described processor, continues to transmit data to indicate described processor.
In conjunction with the possible implementation of the first of second aspect, in the 4th kind of possible implementation, described acquiring unit, concrete for obtaining the data that described processor transmits in n cycle T by data bus, described n 0, described T〉0.
The 4th kind of possible implementation in conjunction with second aspect, in the 5th kind of possible implementation, described transmitting element, concrete being used for crosses loaded line take t as the cycle with the data communication device of described buffer area, 1bits/t is that loading velocity is loaded on described field programmable gate array, and described t is greater than 0.
In conjunction with the 5th kind of possible implementation of second aspect, in the 6th kind of possible implementation, the maximal value of the data volume of described buffer area storage is Hmax, and then n need satisfy inequality 0＜N/T*nT-(n+1) T/t＜Hmax; Wherein, described N is the data volume that transmits in the described cycle T.
In conjunction with the 6th kind of possible implementation of second aspect, in the 7th kind of possible implementation, described judging unit, it is concrete that to be used for judging whether the n value satisfies pre-conditioned, described pre-conditioned be 0＜N/T*nT-(n+1) T/t＜L; If so, determine that then the data volume of described buffer area storage is less than the waterline value L of described buffer area; If not, determine that then the data volume of described buffer area storage is more than or equal to the waterline value L of described buffer area.
The 7th kind of possible implementation in conjunction with second aspect, in the 8th kind of possible implementation, described n also need satisfy inequality 0＜N/T*nT-(n+1) T/t＜Hleft, with satisfy data that described buffer area obtains in next n cycle T less than and equal described Hleft, described Hleft is that the maximal value of the data volume of described buffer area storage is the difference of the waterline value L of Hmax and described buffer area.
The 5th kind of possible implementation in conjunction with second aspect, in the 9th kind of possible implementation, the waterline value L of described buffer area need satisfy inequality L〉2T/t, with satisfy described buffer area by described loaded line take t as the cycle, 1bits/t is that loading velocity loads data continuously to described field programmable gate array.
The third aspect of the embodiment of the invention provides a kind of loading system of field programmable gate array, comprising: processor, charger and field programmable gate array, and described charger comprises buffer area;
Wherein, described processor is used for transmitting data to described charger;
Described charger is used for obtaining the data that described processor sends, and whether the data volume of judging described buffer area storage in preset range, if so, is stored to described buffer area with described data, and notifies described processor to continue the transmission of data; And be used for the data of described buffer area are loaded on described field programmable gate array;
Described processor also for the notice of the described processor continuation of the triggering that receives described charger transmission the transmission of data, transmits extremely described charger of data with continuation;
Described field programmable gate array is used for configuring the data that described charger loads.
In the possible implementation of the first, described charger, whether the concrete data volume that is used for judging described buffer area storage less than the waterline value L of described buffer area, if so, confirms that then the data volume of described buffer area storage is in preset range; The waterline value L of described buffer area is for the operating position of the storage space that identifies described buffer area.
In conjunction with the possible implementation of the first of the third aspect, in the possible implementation of the second, described charger, also being used for sending described buffer area memory data output according to the data volume of described buffer area storage more than or equal to the judged result of the waterline value L of described buffer area will completely indicate to described processor, indicating described processor to stop to transmit data, and continue to judge that data volume that described buffer area stores is whether less than the waterline value L of described buffer area;
Described processor also will completely be indicated for the described buffer area memory data output that receives described charger transmission, to stop to transmit data to described charger.
In conjunction with the 3rd fermentation, implementation or the possible implementation of the second that the first is possible, in the third possible implementation, described charger, concrete for sending described buffer area memory data output less than indicating to described processor, continue to transmit data to indicate described processor;
Described processor, the concrete described buffer area memory data output that is used for receiving described charger transmission are less than indication, to continue transmitting data to described charger.
In conjunction with the possible implementation of the first of the third aspect, in the 4th kind of possible implementation, described preparation implement body is used for transmitting data to described charger in n cycle T by data bus;
Described charger, concrete for obtaining the data that described processor transmits in n cycle T by data bus; Described n〉0, described T〉0.
In conjunction with the 4th kind of possible implementation, in the 5th kind of possible implementation, described charger, concrete being used for by loaded line take t as the cycle, 1bits/t is that loading velocity loads data continuously to described field programmable gate array, described t is greater than 0;
Described field programmable gate array, concrete be used for configuring described charger by loaded line take t as the cycle, 1bits/t is the data that loading velocity loads continuously.
In conjunction with the 5th kind of possible implementation, in the 6th kind of possible implementation, the maximal value of the data volume of described buffer area storage is Hmax, and then n need satisfy inequality 0＜N/T*nT-(n+1) T/t＜Hmax; Wherein, described N is the data volume that transmits in the described cycle T.
In conjunction with the 6th kind of possible implementation, in the 7th kind of possible implementation, described charger, it is concrete that to be used for judging whether the n value satisfies pre-conditioned, described pre-conditioned be 0＜N/T*nT-(n+1) T/t＜L;
If so, determine that then the data volume of described buffer area storage is less than the waterline value L of described buffer area; If not, determine that then the data volume of described buffer area storage is more than or equal to the waterline value L of described buffer area.
In conjunction with the 7th kind of possible implementation, in the 8th kind of possible implementation, described n also need satisfy inequality 0＜N/T*nT-(n+1) T/t＜Hleft, with satisfy data that described buffer area obtains in next n cycle T less than and equal described Hleft, described Hleft is that the maximal value of the data volume of described buffer area storage is the difference of the waterline value L of Hmax and described buffer area.
In conjunction with the 5th kind of possible implementation, in the 9th kind of possible implementation, the waterline value L of described buffer area need satisfy inequality L〉2T/t, with satisfy described charger by described loaded line take t as the cycle, 1bits/t is that loading velocity loads data continuously to described field programmable gate array.
The loading method of the field programmable gate array that the embodiment of the invention provides, Apparatus and system by a buffer area is set, judge that the data volume of described buffer area storage is whether in preset range; If so, then send the buffer area memory data output less than indicating to described processor, continue to transmit data to indicate described processor, to continue to obtain the data that described processor transmits by described data bus; If not, then send the buffer area memory data output and will completely indicate to described processor, stop to transmit data to indicate described processor, and continue to judge that data volume that described buffer area stores is whether in preset range.Not only guaranteed the loading the reliability of the data, can not wash out data, realized simultaneously rapid loading, the phenomenon of having avoided loading the space occurs.Can transmit continuously by data bus the data in a plurality of cycles further, sending an indicator signal triggers described processor and reads feedback signal again, so that the configuration of loading method is more flexible, the realization of charger is optimized more, has promoted the loading performance of the loading system of whole field programmable gate array.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.
The loading method schematic diagram of a kind of field programmable gate array that Fig. 1 provides for the embodiment of the invention one;
The charger structural representation of a kind of field programmable gate array that Fig. 2 provides for the embodiment of the invention two;
The charger structural representation of the another kind of field programmable gate array that Fig. 3 provides for the embodiment of the invention two;
The loading system structural representation of a kind of field programmable gate array that Fig. 4 provides for the embodiment of the invention three.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that obtains under the creative work prerequisite.
Below by specific embodiment, be described in detail respectively.
See also Fig. 1, the loading method schematic diagram of a kind of field programmable gate array that Fig. 1 provides for the embodiment of the invention one.The loading method of the field programmable gate array that the present embodiment provides from the angle of charger narration the present embodiment.As shown in Figure 1, the loading method of the field programmable gate array that provides of the present embodiment may further comprise the steps:
S110, obtain the data that processor sends;
S120, judge that the data volume of buffer area storage is whether in preset range;
If so, execution in step S130 then; If not, continue then to judge that data volume that buffer area stores is whether in preset range;
S130, data are stored to buffer area, and notification processor continues the transmission of data;
S140, the data in the buffer area are loaded on field programmable gate array.
Wherein, as long as have data in the buffer area, then the execution of step S140 is carried out always, is not interrupted.After for the first time being stored to data in the buffer area after initialization, step S140 does not have the differentiation of execution sequence in the enforcement of this method, namely load continuously data to field programmable gate array.
The loading method of the field programmable gate array that the present embodiment provides by a buffer area is set, judges that the data volume of buffer area storage is whether in preset range; If, then send notice to processor, trigger processor and continue to transmit data, to guarantee that the data storage is arranged in the buffer area always, load data to field programmable gate array serially, the phenomenon of having avoided loading the space occurs, and has realized the method to field programmable gate array rapid loading data.
As a kind of optional embodiment, based on step S120 shown in Figure 1, can specifically comprise: judge that the data volume of buffer area storage whether less than the waterline value L of described buffer area, if so, confirms that then the data volume of buffer area storage is in preset range; The waterline value L of described buffer area is for the operating position of the storage space that identifies described buffer area.
Waterline value L by buffer area is set is as criterion, and whether the data volume that has simply realized reliably again judging the buffer area storage method in preset range, easily enforcement.
As a kind of optional embodiment, if the data volume of described buffer area storage is more than or equal to the waterline value L of described buffer area, be that the data volume of buffer area storage is not in preset range, the loading method of the field programmable gate array that the present embodiment provides also comprises: sending the buffer area memory data output will completely indicate to processor, stop to transmit data with instruction processorunit.
The present embodiment by the data volume judging buffer area and store whether in preset range, namely whether less than the waterline value L of buffer area, if not, then sending the buffer area memory data output will completely indicate to processor, stop to transmit data with instruction processorunit, and continue to judge that in preset range or whether data volume that buffer area stores whether less than the waterline value L of buffer area.Not only realize the reliability that data load, can not wash out data, improved simultaneously loading velocity.
As a kind of optional embodiment, refer step S130 carries out this step, i.e. notification processor continuation the transmission of data specifically can be: send the buffer area memory data output less than indicating to processor, continue to transmit data with instruction processorunit.
As a kind of optional embodiment, refer step S110 carries out this step, namely obtains the data that processor sends specifically can be: obtain the data that processor transmits in n cycle T by data bus, n〉0, T〉0.
After the loading method of the field programmable gate array that the present embodiment provides can transmit the data in a plurality of cycles continuously by data bus, send again an indicator signal triggering processor and read feedback signal, so that the configuration of loading method is more flexible, the realization of charger is optimized more, has promoted the loading performance of the loading system of whole field programmable gate array.
As a kind of optional embodiment, refer step S140, carry out this step, being about to data in the buffer area is loaded on field programmable gate array and specifically can is: the data communication device in the buffer area is crossed loaded line take t as the cycle, 1bits/t is that loading velocity is loaded on field programmable gate array, and t is greater than 0.
The loading method of the field programmable gate array that the present embodiment provides has not only satisfied the transmission rule of the data loading of field programmable gate array, namely be loaded on field programmable gate array take 1bits/t as loading velocity, also improve loading velocity, promoted the loading performance of the loading system of whole field programmable gate array.
As a kind of optional embodiment, the maximal value of the data volume of buffer area storage is Hmax, and then n need satisfy inequality 0＜N/T*nT-(n+1) T/t＜Hmax; Wherein, N is the data volume that transmits in the cycle T.
The loading method of the field programmable gate array that the present embodiment provides, namely to satisfy continuity ground and load data to field programmable gate array, when also will satisfy continuity loading data, each maximal value Hmax that within n cycle, is not less than the data volume of buffer area storage to the data volume of buffer area storage.
As a kind of optional embodiment, refer step S120, judge that namely whether the data volume of buffer area storage less than the waterline value L of described buffer area specifically can be: judge whether the n value satisfies pre-conditioned, pre-conditioned is 0＜N/T*nT-(n+1) T/t＜L; If so, determine that then the data volume of buffer area storage is less than the waterline value L of described buffer area; If not, determine that then the data volume of buffer area storage is more than or equal to the waterline value L of described buffer area.
The loading method of the field programmable gate array that the present embodiment provides, pre-conditioned by judging whether the n value satisfies, whether the data volume of judging the storage of described buffer area is less than the waterline value L of described buffer area, convenient and simple, realized the high memory property of buffer area, so that the memory property of buffer area is more stable, further improved the loading performance of data.
As a kind of optional embodiment, n satisfies inequality 0＜N/T*nT-(n+1) T/t＜Hleft, with satisfy data that buffer area obtains in next n cycle T less than and equal Hleft, wherein, Hleft is that the maximal value of the data volume of described buffer area storage is the difference of the waterline value L of Hmax and described buffer area.
The loading method of the field programmable gate array that the present embodiment provides, not only need to satisfy the current current waterline value L that within n cycle, is not less than buffer area to the data volume of buffer area storage, satisfy further the data next time within n cycle, transmit in the T less than and equal Hleft, namely Hleft has identified the scope of holding of also not storing the data storage space.
As a kind of optional embodiment, the waterline value L of buffer area need satisfy inequality L〉2T/t, with satisfy buffer area by loaded line take t as the cycle, 1bits/t is that loading velocity loads data continuously to field programmable gate array.
See also Fig. 2, the charger structural representation of a kind of field programmable gate array that Fig. 2 provides for the embodiment of the invention two.As shown in Figure 2, the charger 300 of the field programmable gate array that provides of the present embodiment comprises: acquiring unit 310, judging unit 320, buffer area 330 and transmitting element 340.
Wherein, acquiring unit 310 is used for obtaining the data that processor sends.
Judging unit 320 is used for judging that data volume that buffer area 330 stores is whether in preset range.
Transmitting element 340 is used for being judged as the result who is according to judging unit 320 and sends and notify to processor, continues to transmit data with notification processor.
Transmitting element 340 also is used for the data of buffer area 330 are loaded on field programmable gate array.
The charger 300 of the field programmable gate array that the present embodiment provides arranges a buffer area 330 by inside, judges that the data volume of buffer area 330 storage is whether in preset range; If, then send notice to processor, trigger processor and continue to transmit data, to guarantee that the data storage is arranged in the buffer area 330 always, load data to field programmable gate array serially, the phenomenon of having avoided loading the space occurs, and has realized the method to field programmable gate array rapid loading data.
As a kind of optional embodiment, judging unit, whether the concrete data volume that is used for judging the buffer area storage less than the waterline value L of described buffer area, if so, confirms that then the data volume that buffer area is stored is in preset range; The waterline value L of described buffer area is for the operating position of the storage space that identifies described buffer area.
Waterline value L by buffer area is set is as criterion, and whether the data volume that has simply realized reliably again judging the buffer area storage method in preset range, easily enforcement.
As a kind of optional embodiment, transmitting element, also being used for according to judgment unit judges is no result, sending the buffer area memory data output will completely indicate to processor, stop to transmit data with instruction processorunit.
Judging unit, also being used for according to judgment unit judges is no result, whether the data volume of cycle criterion buffer area storage is less than the waterline value L of described buffer area.
Whether the data volume of the present embodiment by judgment unit judges buffer area storage be less than the waterline value L of described buffer area, if not, then sending the buffer area memory data output by transmitting element will completely indicate to processor, stop to transmit data with instruction processorunit, and continue data volume by the storage of judgment unit judges buffer area whether less than the waterline value L of described buffer area.Not only realize the reliability that data load, can not wash out data, improved simultaneously loading velocity.
As a kind of optional embodiment, transmitting element, concrete being used for according to judgment unit judges is that the result who is sends the buffer area memory data output less than indicating to processor, continues to transmit data with instruction processorunit.
As a kind of optional embodiment, acquiring unit, concrete for obtaining the data that processor transmits in n cycle T by data bus, n 0, T〉0.
After the present embodiment obtains the data bus data in a plurality of cycles of continuous transmission by acquiring unit, send an indicator signal triggering processor by transmitting element again and read feedback signal, so that the configuration of loading method is more flexible, the realization of charger is optimized more, has promoted the loading performance of the loading system of whole field programmable gate array.
As a kind of optional embodiment, transmitting element, concrete being used for crosses loaded line take t as the cycle with the data communication device of buffer area, and 1bits/t is that loading velocity is loaded on field programmable gate array, and t is greater than 0.
The charger of the field programmable gate array that the present embodiment provides has not only satisfied the transmission rule of the data loading of field programmable gate array, namely be loaded on field programmable gate array take 1bits/t as loading velocity, also improve loading velocity, promoted the loading performance of the loading system of whole field programmable gate array.
As a kind of optional embodiment, the maximal value of the data volume of buffer area storage is Hmax, and then n need satisfy inequality 0＜N/T*nT-(n+1) T/t＜Hmax; Wherein, N is the data volume that transmits in the cycle T.
The charger of the field programmable gate array that the present embodiment provides, namely to satisfy continuity ground and load data to field programmable gate array, when also will satisfy continuity loading data, each maximal value Hmax that within n cycle, is not less than the data volume of buffer area storage to the data volume of buffer area storage.
As a kind of optional embodiment, judging unit, concrete pre-conditioned for judging whether the n value satisfies, pre-conditioned is 0＜N/T*nT-(n+1) T/t＜L; If so, determine that then the data volume of buffer area storage is less than the waterline value L of described buffer area; If not, determine that then the data volume of buffer area storage is more than or equal to the waterline value L of described buffer area.
The charger of the field programmable gate array that the present embodiment provides, further whether satisfy pre-conditioned by judgment unit judges n value, whether the data volume of judging the storage of described buffer area is less than the waterline value L of described buffer area, convenient and simple, realized the high memory property of buffer area, so that the memory property of buffer area is more stable, further improved the loading performance of data.
As a kind of optional embodiment, n also need satisfy inequality 0＜N/T*nT-(n+1) T/t＜Hleft, with satisfy data that buffer area obtains in next n cycle T less than and equal Hleft, Hleft is that the maximal value of the data volume of described buffer area storage is the difference of the waterline value L of Hmax and described buffer area.
The charger of the field programmable gate array that the present embodiment provides, not only need to satisfy the current current waterline value L that within n cycle, is not less than buffer area to the data volume of buffer area storage, satisfy further the data next time within n cycle, transmit in the T less than and equal Hleft, namely Hleft has identified the scope of holding of also not storing the data storage space.
As a kind of optional embodiment, the waterline value L of buffer area need satisfy inequality L〉2T/t, with satisfy buffer area by loaded line take t as the cycle, 1bits/t is that loading velocity loads data continuously to field programmable gate array.
See also Fig. 3, the charger structural representation of the another kind of field programmable gate array that Fig. 3 provides for the embodiment of the invention two.As shown in Figure 3, the charger 400 of the field programmable gate array that the present embodiment provides comprises: the quantity of input media 410, output unit 420, treating apparatus 430(treating apparatus 430 can be for one or more, among Fig. 4 take a treating apparatus as example) and memory storage 440.
In some embodiments of the invention, input media 410, output unit 420, treating apparatus 430 are connected with memory storage and can be connected by bus or alternate manner, wherein, among Fig. 4 to be connected to example by bus.
Wherein, input media 410 obtains the data that processor sends.
Treating apparatus 430 is carried out following steps: judge that data volume that memory storage 440 stores is whether in preset range, if, then control store device 440 is stored to memory storage 440 with data, and control output unit 420 notification processors continue the transmission of data; And control output unit 420 is loaded on field programmable gate array with the data in the memory storage 440.
The charger 400 of the field programmable gate array that the present embodiment provides arranges a memory storage 440 by inside, judges that the data volume of memory storage 440 storage is whether in preset range; If, then send notice to processor, trigger processor and continue to transmit data, to guarantee that the data storage is arranged in the memory storage 440 always, load data to field programmable gate array serially, the phenomenon of having avoided loading the space occurs, and has realized the method to field programmable gate array rapid loading data.
As a kind of optional embodiment, treating apparatus judges that whether the data volume of memory device stores specifically can be in preset range: whether the data volume of judging memory device stores is less than the waterline value L of memory storage, if so, confirm that then the data volume of memory device stores is in preset range; The waterline value L of described memory storage is used for the operating position of the storage space of sign memory storage.
Waterline value L by memory storage is set is as criterion, and whether the data volume that has simply realized reliably again judging memory device stores the method in preset range, easily enforcement.
As a kind of optional embodiment, if the data volume of storing in the memory storage is more than or equal to the waterline value L of described buffer area, then treating apparatus control output unit transmission memory storage memory data output will completely be indicated to processor, stop to transmit data with instruction processorunit.
The present embodiment judges that by treating apparatus the data volume of memory device stores is more than or equal to the waterline value L of described buffer area, then sending the memory storage memory data output by output unit will completely indicate to processor, stop to transmit data with instruction processorunit, and the data volume that continues to judge memory device stores by treating apparatus is whether less than the waterline value L of described buffer area.Not only realize the reliability that data load, can not wash out data, improved simultaneously loading velocity.
As a kind of optional embodiment, it specifically can be that the control output unit sends the memory storage memory data output less than indicating to processor that treating apparatus control output unit notification processor continues the transmission of data, continues to transmit data with instruction processorunit.
As a kind of optional embodiment, it specifically can be to obtain the data that processor transmits in n cycle T by data bus, n that input media obtains the data that processor sends〉0, T〉0.
After the present embodiment obtains the data bus data in a plurality of cycles of continuous transmission by input media, send an indicator signal triggering processor by output unit again and read feedback signal, so that the configuration of loading method is more flexible, the realization of charger is optimized more, has promoted the loading performance of the loading system of whole field programmable gate array.
As a kind of optional embodiment, treating apparatus control output unit is loaded on field programmable gate array with the data in the memory storage and specifically can is: treating apparatus control output unit is crossed loaded line take t as the cycle with the data communication device in the memory storage, 1bits/t is that loading velocity is loaded on field programmable gate array, and t is greater than 0.
The charger of the field programmable gate array that the present embodiment provides has not only satisfied the transmission rule of the data loading of field programmable gate array, namely be loaded on field programmable gate array take 1bits/t as loading velocity, also improve loading velocity, promoted the loading performance of the loading system of whole field programmable gate array.
As a kind of optional embodiment, the maximal value of the data volume of memory device stores is Hmax, and then n need satisfy inequality 0＜N/T*nT-(n+1) T/t＜Hmax; Wherein, N is the data volume that transmits in the cycle T.
The charger of the field programmable gate array that the present embodiment provides, namely to satisfy continuity ground and load data to field programmable gate array, when also will satisfy continuity loading data, within n cycle, be not less than the maximal value Hmax of the data volume of memory device stores to the data volume of memory device stores at every turn.
As a kind of optional embodiment, treating apparatus judges that whether the data volume of memory device stores less than the waterline value L of described buffer area specifically can be: it is pre-conditioned that treating apparatus judges whether the n value satisfies, and pre-conditioned is 0＜N/T*nT-(n+1) T/t＜L;
If so, determine that then the data volume of memory device stores is less than the waterline value L of memory storage; If not, determine that then the data volume of memory device stores is more than or equal to the waterline value L of memory storage.
The charger of the field programmable gate array that the present embodiment provides, further judge by treating apparatus whether the n value satisfies pre-conditioned, whether the data volume of judging memory device stores is less than the waterline value L of memory storage, convenient and simple, realized the high memory property of memory storage, so that the memory property of memory storage is more stable, further improved the loading performance of data.
As a kind of optional embodiment, n also need satisfy inequality 0＜N/T*nT-(n+1) T/t＜Hleft, with satisfy data that memory storage obtains in next n cycle T less than and equal Hleft, Hleft is that the maximal value of the data volume of memory device stores is the difference of the waterline value L of Hmax and memory storage.
The charger of the field programmable gate array that the present embodiment provides, not only need to satisfy the current current waterline value L that within n cycle, is not less than buffer area to the data volume of buffer area storage, satisfy further the data next time within n cycle, transmit in the T less than and equal Hleft, namely Hleft has identified the scope of holding of also not storing the data storage space.
As a kind of optional embodiment, the waterline value L of memory storage need satisfy inequality L〉2T/t, with satisfy memory storage by loaded line take t as the cycle, 1bits/t is that loading velocity loads data continuously to field programmable gate array.
See also Fig. 4, the loading system structural representation of a kind of field programmable gate array that Fig. 4 provides for the embodiment of the invention three.As shown in Figure 4, the loading system 500 of the field programmable gate array that the present embodiment provides comprises: processor 510, charger 520 and field programmable gate array 530, charger 520 comprises buffer area 521.
Wherein, processor 510 is used for transmitting data to charger 520.
Field programmable gate array 530 is used for the data that configuration charger 520 loads.
The loading system 500 of the field programmable gate array that the present embodiment provides arranges charger 520 by inside, judges that the data volume of buffer area 521 storages be arranged in the charger 520 is whether in preset range; If, then send notice to processor 510, trigger processor 510 and continue to transmit data, to guarantee that the data storage is arranged in the buffer area 521 always, load data to field programmable gate array serially, the phenomenon of having avoided loading the space occurs, and has realized the method to field programmable gate array rapid loading data.
As a kind of optional embodiment, charger, whether the concrete data volume that is used for judging the buffer area storage less than the waterline value L of described buffer area, if so, confirms that then data volume that buffer area stores is in preset range; The waterline value L of described buffer area is used for the operating position of the storage space of sign buffer area.
Waterline value L by buffer area is set is as criterion, and whether the data volume that has simply realized reliably again judging the buffer area storage method in preset range, easily enforcement.
As a kind of optional embodiment, charger, also be used for completely to indicate to processor more than or equal to the judged result transmission buffer area memory data output of the waterline value L of described buffer area according to the data volume of buffer area storage, stop to transmit data with instruction processorunit, and continue to judge that data volume that buffer area stores is whether less than the waterline value L of buffer area;
Processor, the buffer area memory data output that also is used for the transmission of reception charger will completely be indicated, to stop to transmit data to charger.
Whether the data volume that the present embodiment is judged buffer area storage by charger is less than the waterline value L of described buffer area, if not, then sending the buffer area memory data output will completely indicate to processor, stop to transmit data with instruction processorunit, and continue to judge that data volume that buffer area stores is whether less than the waterline value L of described buffer area.Not only realize the reliability that data load, can not wash out data, improved simultaneously loading velocity.
As a kind of optional embodiment, charger, the concrete transmission buffer area memory data output that is used for continues to transmit data less than indicating to processor with instruction processorunit.
Processor, the concrete buffer area memory data output that is used for receiving the charger transmission are less than indication, to continue transmitting data to charger.
As a kind of optional embodiment, the preparation implement body is used for transmitting data to charger in n cycle T by data bus.
Charger, concrete for obtaining the data that processor transmits in n cycle T by data bus; N〉0, T〉0.
After the present embodiment obtains the data bus data in a plurality of cycles of continuous transmission by charger, send again an indicator signal triggering processor and read feedback signal, so that the configuration of loading method is more flexible, the realization of charger is optimized more, has promoted the loading performance of the loading system of whole field programmable gate array.
As a kind of optional embodiment, charger, concrete being used for by loaded line take t as the cycle, 1bits/t is that loading velocity loads data continuously to field programmable gate array, t is greater than 0.
Field programmable gate array, concrete be used for the configuration charger by loaded line take t as the cycle, 1bits/t is the data that loading velocity loads continuously.
The loading system of the field programmable gate array that the present embodiment provides has not only satisfied the transmission rule of loading data to field programmable gate array, namely be loaded on field programmable gate array take 1bits/t as loading velocity, also improve loading velocity, promoted the loading performance of the loading system of whole field programmable gate array.
As a kind of optional embodiment, the maximal value of the data volume of buffer area storage is Hmax, and then n need satisfy inequality 0＜N/T*nT-(n+1) T/t＜Hmax; Wherein, N is the data volume that transmits in the cycle T.
The loading system of the field programmable gate array that the present embodiment provides, namely to satisfy continuity ground and load data to field programmable gate array, when also will satisfy continuity loading data, each maximal value Hmax that within n cycle, is not less than the data volume of buffer area storage to the data volume of buffer area storage.
As a kind of optional embodiment, charger, concrete pre-conditioned for judging whether the n value satisfies, pre-conditioned is 0＜N/T*nT-(n+1) T/t＜L;
If so, determine that then the data volume of buffer area storage is less than the waterline value L of described buffer area; If not, determine that then the data volume of buffer area storage is more than or equal to the waterline value L of described buffer area.
The loading system of the field programmable gate array that the present embodiment provides, judge by charger whether the n value satisfies pre-conditioned, whether the data volume of judging the storage of described buffer area is less than the waterline value L of described buffer area, convenient and simple, realized the high memory property of buffer area, so that the memory property of buffer area is more stable, further improved the loading performance of data.
As a kind of optional embodiment, n also need satisfy inequality 0＜N/T*nT-(n+1) T/t＜Hleft, with satisfy data that buffer area obtains in next n cycle T less than and equal Hleft, Hleft is that the maximal value of the data volume of described buffer area storage is the difference of the waterline value L of Hmax and described buffer area.
The loading system of the field programmable gate array that the present embodiment provides, not only need to satisfy the current current waterline value L that within n cycle, is not less than buffer area to the data volume of buffer area storage, satisfy further the data next time within n cycle, transmit in the T less than and equal Hleft, namely Hleft has identified the scope of holding of also not storing the data storage space.
As a kind of optional embodiment, the waterline value L of buffer area need satisfy inequality L〉2T/t, with satisfy charger by loaded line take t as the cycle, 1bits/t is that loading velocity loads data continuously to field programmable gate array.
One of ordinary skill in the art will appreciate that all or part of flow process that realizes in above-described embodiment method, to come the relevant hardware of instruction to finish by computer program, program can be stored in the computer read/write memory medium, this program can comprise the flow process such as the embodiment of above-mentioned each side method when carrying out.Wherein, storage medium can be magnetic disc, CD, read-only store-memory body (Read-Only Memory, ROM) or random access memory (Random Access Memory is called for short RAM) etc.
Claims (30)
1. the loading method of a field programmable gate array is characterized in that, comprising:
Obtain the data that processor sends;
Whether the data volume of judging buffer area storage in preset range, if so, is stored to buffer area with described data, and notifies described processor to continue the transmission of data;
And, the data in the described buffer area are loaded on described field programmable gate array.
2. the loading method of field programmable gate array as claimed in claim 1 is characterized in that, whether the described data volume of judging that buffer area is stored comprises in preset range:
Judge that the data volume of buffer area storage whether less than the waterline value L of described buffer area, if so, confirms that then the data volume of buffer area storage is in preset range; The waterline value L of described buffer area is for the operating position of the storage space that identifies described buffer area.
3. the loading method of field programmable gate array as claimed in claim 2 is characterized in that, described method also comprises:
If the data volume of described buffer area storage then sends described buffer area memory data output and will completely indicate to described processor more than or equal to the waterline value L of described buffer area, stop to transmit data to indicate described processor;
Continue to judge that data volume that buffer area stores is whether less than the waterline value L of described buffer area.
4. such as the claims 1 to 3 loading method of arbitrary described field programmable gate array wherein, it is characterized in that, describedly notify described processor to continue the transmission of data to comprise:
Send described buffer area memory data output less than indicating to described processor, continue to transmit data to indicate described processor.
5. the loading method of field programmable gate array as claimed in claim 2 is characterized in that, describedly obtains the data that described processor sends and comprises:
Obtain the data that described processor transmits in n cycle T by data bus, described n〉0, described T〉0.
6. the loading method of field programmable gate array as claimed in claim 5 is characterized in that, describedly data in the described buffer area are loaded on described field programmable gate array comprise:
Data communication device in the described buffer area is crossed loaded line take t as the cycle, and 1bits/t is that loading velocity is loaded on described field programmable gate array, and described t is greater than 0.
7. the loading method of field programmable gate array as claimed in claim 6 is characterized in that,
The maximal value of the data volume of described buffer area storage is Hmax, and then n need satisfy inequality 0＜N/T*nT-(n+1) T/t＜Hmax; Wherein, described N is the data volume that transmits in the described cycle T.
8. the loading method of field programmable gate array as claimed in claim 7 is characterized in that, whether the described data volume of judging the storage of described buffer area comprises less than the waterline value L of described buffer area:
Judge whether the n value satisfies pre-conditioned, described pre-conditioned be 0＜N/T*nT-(n+1) T/t＜L;
If so, determine that then the data volume of described buffer area storage is less than the waterline value L of described buffer area; If not, determine that then the data volume of described buffer area storage is more than or equal to the waterline value L of described buffer area.
9. the loading method of field programmable gate array as claimed in claim 8 is characterized in that,
Described n satisfies inequality 0＜N/T*nT-(n+1) T/t＜Hleft, with satisfy data that described buffer area obtains in next n cycle T less than and equal described Hleft, described Hleft is that the maximal value of the data volume of described buffer area storage is the difference of the waterline value L of Hmax and described buffer area.
10. the loading method of field programmable gate array as claimed in claim 6 is characterized in that,
The waterline value L of described buffer area need satisfy inequality L〉2T/t, with satisfy described buffer area by described loaded line take t as the cycle, 1bits/t is that loading velocity loads data continuously to described field programmable gate array.
11. the charger of a field programmable gate array is characterized in that, comprising:
Acquiring unit is used for obtaining the data that processor sends;
Judging unit is used for judging that data volume that buffer area stores is whether in preset range;
Described buffer area, being used for according to described judgment unit judges is the described data of result store that are;
Transmitting element, being used for according to described judgment unit judges is that the result who is sends notice to described processor, continues to transmit data to notify described processor;
Described transmitting element also is used for the data of described buffer area are loaded on described field programmable gate array.
12. the charger of field programmable gate array as claimed in claim 11 is characterized in that,
Whether described judging unit, the concrete data volume that is used for judging the buffer area storage less than the waterline value L of described buffer area, if so, confirm that then the data volume that buffer area is stored is in preset range; The waterline value L of described buffer area is for the operating position of the storage space that identifies described buffer area.
13. the charger of field programmable gate array as claimed in claim 12 is characterized in that,
Described transmitting element, also being used for according to described judgment unit judges is no result, sends described buffer area memory data output and will completely indicate to described processor, stops to transmit data to indicate described processor;
Described judging unit, also being used for according to described judgment unit judges is no result, continues to judge that data volume that described buffer area stores is whether less than the waterline value L of described buffer area.
14. the charger such as the arbitrary described field programmable gate array of claim 11 to 13 is characterized in that,
Described transmitting element, concrete being used for according to described judgment unit judges is that the result who is sends described buffer area memory data output less than indicating to described processor, continues to transmit data to indicate described processor.
15. the charger of field programmable gate array as claimed in claim 12 is characterized in that, described acquiring unit is concrete for obtaining the data that described processor transmits in n cycle T by data bus, described n〉0, described T〉0.
16. the charger of field programmable gate array as claimed in claim 15, it is characterized in that, described transmitting element, concrete being used for crosses loaded line take t as the cycle with the data communication device of described buffer area, 1bits/t is that loading velocity is loaded on described field programmable gate array, and described t is greater than 0.
17. the charger of field programmable gate array as claimed in claim 16 is characterized in that, the maximal value of the data volume of described buffer area storage is Hmax, and then n need satisfy inequality 0＜N/T*nT-(n+1) T/t＜Hmax; Wherein, described N is the data volume that transmits in the described cycle T.
18. the charger of field programmable gate array as claimed in claim 17 is characterized in that,
Described judging unit, it is concrete that to be used for judging whether the n value satisfies pre-conditioned, described pre-conditioned be 0＜N/T*nT-(n+1) T/t＜L; If so, determine that then the data volume of described buffer area storage is less than the waterline value L of described buffer area; If not, determine that then the data volume of described buffer area storage is more than or equal to the waterline value L of described buffer area.
19. the charger of field programmable gate array as claimed in claim 18, it is characterized in that, described n also need satisfy inequality 0＜N/T*nT-(n+1) T/t＜Hleft, with satisfy data that described buffer area obtains in next n cycle T less than and equal described Hleft, described Hleft is that the maximal value of the data volume of described buffer area storage is the difference of the waterline value L of Hmax and described buffer area.
20. the charger of field programmable gate array as claimed in claim 16, it is characterized in that, the waterline value L of described buffer area need satisfy inequality L〉2T/t, with satisfy described buffer area by described loaded line take t as the cycle, 1bits/t is that loading velocity loads data continuously to described field programmable gate array.
21. the loading system of a field programmable gate array is characterized in that, comprising: processor, charger and field programmable gate array, described charger comprises buffer area;
Wherein, described processor is used for transmitting data to described charger;
Described charger is used for obtaining the data that described processor sends, and whether the data volume of judging described buffer area storage in preset range, if so, is stored to described buffer area with described data, and notifies described processor to continue the transmission of data; And be used for the data of described buffer area are loaded on described field programmable gate array;
Described processor also for the notice of the described processor continuation of the triggering that receives described charger transmission the transmission of data, transmits extremely described charger of data with continuation;
Described field programmable gate array is used for configuring the data that described charger loads.
22. the loading system of field programmable gate array as claimed in claim 21 is characterized in that,
Whether described charger, the concrete data volume that is used for judging described buffer area storage less than the waterline value L of described buffer area, if so, confirm that then the data volume of described buffer area storage is in preset range; The waterline value L of described buffer area is for the operating position of the storage space that identifies described buffer area.
23. the loading system of field programmable gate array as claimed in claim 22 is characterized in that,
Described charger, also being used for sending described buffer area memory data output according to the data volume of described buffer area storage more than or equal to the judged result of the waterline value L of described buffer area will completely indicate to described processor, indicating described processor to stop to transmit data, and continue to judge that data volume that described buffer area stores is whether less than the waterline value L of described buffer area;
Described processor also will completely be indicated for the described buffer area memory data output that receives described charger transmission, to stop to transmit data to described charger.
24. the loading system such as the arbitrary described field programmable gate array of claim 21 to 23 is characterized in that,
Described charger, concrete for sending described buffer area memory data output less than indicating to described processor, continue to transmit data to indicate described processor;
Described processor, the concrete described buffer area memory data output that is used for receiving described charger transmission are less than indication, to continue transmitting data to described charger.
25. the loading system of field programmable gate array as claimed in claim 22 is characterized in that,
Described preparation implement body is used for transmitting data to described charger in n cycle T by data bus;
Described charger, concrete for obtaining the data that described processor transmits in n cycle T by data bus; Described n〉0, described T〉0.
26. the loading system of field programmable gate array as claimed in claim 25 is characterized in that,
Described charger, concrete being used for by loaded line take t as the cycle, 1bits/t is that loading velocity loads data continuously to described field programmable gate array, described t is greater than 0;
Described field programmable gate array, concrete be used for configuring described charger by loaded line take t as the cycle, 1bits/t is the data that loading velocity loads continuously.
27. the loading system of field programmable gate array as claimed in claim 26 is characterized in that, the maximal value of the data volume of described buffer area storage is Hmax, and then n need satisfy inequality 0＜N/T*nT-(n+1) T/t＜Hmax; Wherein, described N is the data volume that transmits in the described cycle T.
28. the loading system of field programmable gate array as claimed in claim 27 is characterized in that,
Described charger, it is concrete that to be used for judging whether the n value satisfies pre-conditioned, described pre-conditioned be 0＜N/T*nT-(n+1) T/t＜L;
If so, determine that then the data volume of described buffer area storage is less than the waterline value L of described buffer area; If not, determine that then the data volume of described buffer area storage is more than or equal to the waterline value L of described buffer area.
29. the loading system of field programmable gate array as claimed in claim 28, it is characterized in that, described n also need satisfy inequality 0＜N/T*nT-(n+1) T/t＜Hleft, with satisfy data that described buffer area obtains in next n cycle T less than and equal described Hleft, described Hleft is that the maximal value of the data volume of described buffer area storage is the difference of the waterline value L of Hmax and described buffer area.
30. the loading system of field programmable gate array as claimed in claim 26, it is characterized in that, the waterline value L of described buffer area need satisfy inequality L〉2T/t, with satisfy described charger by described loaded line take t as the cycle, 1bits/t is that loading velocity loads data continuously to described field programmable gate array.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210388905.1A CN102929663B (en) | 2012-10-15 | 2012-10-15 | The loading method of a kind of field programmable gate array, Apparatus and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210388905.1A CN102929663B (en) | 2012-10-15 | 2012-10-15 | The loading method of a kind of field programmable gate array, Apparatus and system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102929663A true CN102929663A (en) | 2013-02-13 |
| CN102929663B CN102929663B (en) | 2016-08-17 |
Family
ID=47644473
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210388905.1A Active CN102929663B (en) | 2012-10-15 | 2012-10-15 | The loading method of a kind of field programmable gate array, Apparatus and system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102929663B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4258418A (en) * | 1978-12-28 | 1981-03-24 | International Business Machines Corporation | Variable capacity data buffer system |
| US5313620A (en) * | 1989-04-06 | 1994-05-17 | Bell Communications Research, Inc. | Selective receiver for each processor in a multiple processor system |
| US20070150718A1 (en) * | 2005-12-28 | 2007-06-28 | Nec Corporation | Information processing apparatus and method for using reconfigurable device |
| CN101354657A (en) * | 2008-09-09 | 2009-01-28 | 京信通信系统（中国）有限公司 | Method and circuit for loading on site programmable gate array |
-
2012
- 2012-10-15 CN CN201210388905.1A patent/CN102929663B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4258418A (en) * | 1978-12-28 | 1981-03-24 | International Business Machines Corporation | Variable capacity data buffer system |
| US5313620A (en) * | 1989-04-06 | 1994-05-17 | Bell Communications Research, Inc. | Selective receiver for each processor in a multiple processor system |
| US20070150718A1 (en) * | 2005-12-28 | 2007-06-28 | Nec Corporation | Information processing apparatus and method for using reconfigurable device |
| CN101354657A (en) * | 2008-09-09 | 2009-01-28 | 京信通信系统（中国）有限公司 | Method and circuit for loading on site programmable gate array |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102929663B (en) | 2016-08-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103279309B (en) | Based on DDR control device and the method for FPGA | |
| US8489780B2 (en) | Power saving in NAND flash memory | |
| WO2008079788A1 (en) | Command-based control of nand flash memory | |
| CN102831090A (en) | Address line for space-borne DSP (Digital Signal Processor) and FPGA (Field Programmable Gate Array) communication interfaces and optimization method for address line | |
| CN103455419B (en) | Field programmable gate array platform and adjustment method thereof | |
| CN101944075B (en) | Bus system and method and device for reading and writing low-speed bus device | |
| CN107305504A (en) | Data storage device, control unit thereof and task sequencing method thereof | |
| RU2416819C2 (en) | Method, computer programme product and device for connecting to memory card | |
| CN103870323A (en) | Trigger routing unit | |
| CN105279116A (en) | DDR (Double Data Rate) controller and controlling method based on FPGA (Field Programmable Gate Array) | |
| CN101169673B (en) | Real-time timepiece chip interface circuit control method and real-time timepiece control circuit | |
| CN104238957A (en) | Serial peripheral interface controller, serial peripheral interface flash memory, access method and access control method | |
| CN113918500A (en) | Device and system conforming to specification of extended interface serial peripheral interface | |
| CN103530215A (en) | Self-inspection method and device of inter integrated circuit host and host | |
| CN102855199B (en) | Data processing equipment and data processing equipment | |
| CN103729165A (en) | PCI (peripheral component interconnect) slave unit core control module applied to high-speed motion control system | |
| US5442800A (en) | Parallel input-output circuit permitting reduce number of pins in a single chip microcomputer | |
| CN105718396B (en) | A kind of I of big data master transmissions2C bus units and its means of communication | |
| CN104571942A (en) | Data storage system and method analyzing non-signal | |
| EP2188726A1 (en) | Token protocol | |
| CN104424142B (en) | The method and apparatus of shared resource is accessed in a kind of multi-core processor system | |
| CN102929663A (en) | Method, device and system for loading field programmable gate array | |
| CN102388359B (en) | Method and device for remaining signal sequence | |
| CN105573947A (en) | APB (Advanced Peripheral Bus) based SD/MMC (Secure Digital/ MultiMedia Card) control method | |
| CN108153485B (en) | Method and system for multi-device cooperative access to SRAM |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20191220 Address after: No.1, floor 3, No.319, zhanggongshan Road, Yuhui District, Bengbu City, Anhui Province Patentee after: Bengbu guijiu Intellectual Property Service Co., Ltd Address before: 518129 Bantian HUAWEI headquarters office building, Longgang District, Guangdong, Shenzhen Patentee before: Huawei Technologies Co., Ltd. |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20201014 Address after: 226000 No. 998 Century Avenue, hi tech Zone, Jiangsu, Nantong Patentee after: NANTONG HANGDA ELECTRONIC TECHNOLOGY Co.,Ltd. Address before: No.1, floor 3, No.319, zhanggongshan Road, Yuhui District, Bengbu City, Anhui Province Patentee before: Bengbu guijiu Intellectual Property Service Co.,Ltd. |
|
| TR01 | Transfer of patent right |