CN102915952A

CN102915952A - Manufacturing method for semiconductor device

Info

Publication number: CN102915952A
Application number: CN2011102223547A
Authority: CN
Inventors: 周鸣
Original assignee: Semiconductor Manufacturing International Shanghai Corp
Current assignee: Semiconductor Manufacturing International Shanghai Corp
Priority date: 2011-08-04
Filing date: 2011-08-04
Publication date: 2013-02-06
Anticipated expiration: 2031-08-04
Also published as: CN102915952B

Abstract

The invention provides a manufacturing method for a semiconductor device, comprising the following steps: a semiconductor substrate is provided, an insulation layer is formed on the semiconductor substrate, and a copper interconnecting wire is formed in the insulation layer; a silicon-rich nitride layer is formed on the insulation layer and the copper interconnecting wire; and a thermal oxide layer is formed on the silicon-rich nitride layer; and nitrogen-doped silicon carbide is formed on the thermal oxide layer. According to the manufacturing method for a semiconductor device, the silicon-rich nitride layer and the thermal oxide layer constitute a dual-layer copper diffusion barrier layer, and thermal oxide layer can effectively improve the damage of current, induced by plasma induced damage (PID), to the semiconductor device.

Description

A kind of manufacture method of semiconductor device

Technical field

The present invention relates to semiconductor fabrication process, have the copper metal diffusion barrier layer of new construction in particular to a kind of employing to improve the method for plasma-induced damage (PID).

Background technology

In existing advanced copper metal interconnect technology, usually use the silicon oxide carbide (SiCO) of porous as the material of dielectric layer, form carbonitride of silicium (SiCN) layer of a densification simultaneously thereon as copper metal diffusion barrier layer and etch stop layer.

Described SiCN layer stop the copper metal to be diffused into the SiCO layer of porous and prevent through the time play vital effect aspect the dielectric breakdown, simultaneously as etch stop layer, the etching selectivity of itself and porous SiC O can be controlled the etched shape of through hole well greater than 8:1.

But described SiCN layer can run into the problem of plasma-induced damage (PID), power when adopting plasma reinforced chemical vapour deposition (PECVD) technique to form described SiCN layer is greater than 200W, obvious PID phenomenon can occur, affect the electrology characteristic of described SiCN layer and porous SiC O layer.

Therefore, needing to propose a kind of method of improving plasma-induced damage (PID) induces the electric current of generation to the damage of device to reduce PID.

Summary of the invention

For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprising: Semiconductor substrate is provided, forms an insulating barrier in described Semiconductor substrate, and in described insulating barrier, form the copper metal interconnecting wires; Form the silicon-rich silicon nitride layer at described insulating barrier and copper metal interconnecting wires; Form thermal oxide layer at described silicon-rich silicon nitride layer; Form the silicon carbide layer of doping nitrogen at described thermal oxide layer.

Preferably, adopt chemical vapor deposition method to form described silicon-rich silicon nitride layer.

Preferably, the precursor material that forms described silicon-rich silicon nitride layer comprises silane and ammonia.

Preferably, the flow of described silane is 100-1000sccm; The flow of described ammonia is 100-500sccm.

Preferably, described chemical vapor deposition processes is at pressure 1-7Torr, carries out under the condition of power 50-100W.

Preferably, the thickness of described silicon-rich silicon nitride layer is the 30-150 dust.

Preferably, adopt chemical vapor deposition method to form described thermal oxide layer.

Preferably, the precursor material that forms described thermal oxide layer comprises tetraethoxysilane and ozone.

Preferably, the flow of described tetraethoxysilane is 50-500sccm; The flow of described ozone is 50-1000sccm.

Preferably, described chemical vapor deposition processes is to carry out under the condition of pressure 1-7Torr.

Preferably, the thickness of described thermal oxide layer is the 100-500 dust.

Preferably, adopt chemical vapor deposition method to form the silicon carbide layer of described doping nitrogen.

Preferably, the thickness of the silicon carbide layer of described doping nitrogen is the 50-300 dust.

Preferably, described silicon-rich silicon nitride layer and described thermal oxide layer consist of double-deck copper metal diffusion barrier layer.

Preferably, the silicon carbide layer of described doping nitrogen consists of the through hole etch stop layer.

Preferably, described insulating barrier is the material layer with low-k.

According to the present invention, can effectively improve the electric current of plasma-induced damage (PID) generation of inducing to the infringement of device.

Description of drawings

Following accompanying drawing of the present invention is used for understanding the present invention at this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.

In the accompanying drawing:

Figure 1A-Fig. 1 D is copper metal diffusion barrier layer with new construction of employing that the present invention proposes with the schematic cross sectional view of each step of the method for improving plasma-induced damage (PID);

Fig. 2 is copper metal diffusion barrier layer with new construction of employing that the present invention proposes with the flow chart of the method for improving plasma-induced damage (PID).

Embodiment

In the following description, a large amount of concrete details have been provided in order to more thorough understanding of the invention is provided.Yet, it is obvious to the skilled person that the present invention can need not one or more these details and implemented.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.

In order thoroughly to understand the present invention, detailed step will be proposed, so that how explaination the present invention adopts the copper metal diffusion barrier layer with new construction to improve plasma-induced damage (PID) in following description.Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution modes.

Should be understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, integral body, step, operation, element and/or assembly, does not exist or additional one or more other features, integral body, step, operation, element, assembly and/or their combination but do not get rid of.

Below, copper metal diffusion barrier layer that employing that the present invention proposes has a new construction is described with the detailed step of the method for improving plasma-induced damage (PID) with reference to Figure 1A-Fig. 1 D and Fig. 2.

With reference to Figure 1A-Fig. 1 D, wherein show copper metal diffusion barrier layer that employing that the present invention proposes has a new construction with the schematic cross sectional view of each step of the method for improving plasma-induced damage (PID).

At first, shown in Figure 1A, provide Semiconductor substrate 100, the constituent material of described Semiconductor substrate 100 can adopt unadulterated monocrystalline silicon, is doped with the monocrystalline silicon of impurity, silicon-on-insulator (SOI) etc.As example, in the present embodiment, Semiconductor substrate 100 selects single crystal silicon material to consist of.Be formed with isolation channel in Semiconductor substrate 100, buried regions, and various trap (well) structure in order to simplify, are omitted in the diagram.

On described Semiconductor substrate 100, be formed with various elements, in order to simplify, omitted in the diagram, an insulating barrier 101 only is shown here, it typically is the material layer with low-k.Be formed with in the described insulating barrier 101 for the groove of filling metal interconnecting wires.Deposit a metal level, copper metal layer for example on described insulating barrier 101, and fills up groove in the described insulating barrier 101.Adopt chemical mechanical milling tech to remove unnecessary copper metal layer, the surface that is ground to described insulating barrier 101 stops, and forms copper metal interconnecting wires 102 in described insulating barrier 101.

Then, as shown in Figure 1B, form a silicon-rich silicon nitride layer 103 at described insulating barrier 101 and copper metal interconnecting wires 102.Adopt chemical vapor deposition method to form described silicon-rich silicon nitride layer 103, wherein, with silane (SiH ₄) and ammonia (NH ₃) as the precursor material that forms described silicon-rich silicon nitride layer 103.

The concrete technology parameter of described chemical vapor deposition method is as follows: pressure 1-7Torr, power 50-100W, SiH ₄Flow be 100-1000sccm, NH ₃Flow be 100-500sccm.The thickness of the described silicon-rich silicon nitride layer 103 that deposition forms is the 30-150 dust.

Then, shown in Fig. 1 C, form a thermal oxide layer 104 at described silicon-rich silicon nitride layer 103.Adopt chemical vapor deposition method to form described thermal oxide layer 104, wherein, with tetraethoxysilane (TEOS) and ozone (O ₃) as the precursor material that forms described thermal oxide layer 104.

The concrete technology parameter of described chemical vapor deposition method is as follows: pressure 1-7Torr, the flow of TEOS are 50-500sccm, O ₃Flow be 50-1000sccm.The thickness of the described thermal oxide layer 104 that deposition forms is the 100-500 dust.

Then, shown in Fig. 1 D, form the silicon carbide layer 105 of a doping nitrogen at described thermal oxide layer 104.Adopt chemical vapor deposition method to form the silicon carbide layer 105 of described doping nitrogen, wherein, use trimethyl silane (3MS) and ammonia (NH ₃) as the precursor material of the silicon carbide layer 105 that forms described doping nitrogen.

The concrete technology parameter of described chemical vapor deposition method is as follows: pressure 0.2-0.9Torr, the flow of 3MS are 100-1000sccm, NH ₃Flow be 100-1000sccm.The thickness of the silicon carbide layer 105 of the described doping nitrogen that deposition forms is the 50-300 dust.

So far, according to an exemplary embodiment of the present invention whole processing steps of method enforcement have been finished, formation has the copper metal diffusion barrier layer of new construction: described silicon-rich silicon nitride layer 103 and thermal oxide layer 104 consist of double-deck copper metal diffusion barrier layer, wherein, described silicon-rich silicon nitride layer also plays the effect of the oxygen diffusion that stops in the described thermal oxide layer, and described thermal oxide layer can improve plasma-induced damage; The silicon carbide layer 105 of described doping nitrogen is as the through hole etch stop layer, and described thermal oxide layer 104 also can play the effect of through hole etch-stop.Because required power lower (50-100W) and do not need the mode of using plasma deposition when forming described thermal oxide layer when forming described silicon-rich silicon nitride layer, thereby can reduce PID and induce the electric current of generation to the damage of device.

With reference to Fig. 2, wherein show copper metal diffusion barrier layer that employing that the present invention proposes has a new construction with the flow chart of the method for improving plasma-induced damage (PID), be used for schematically illustrating the flow process of whole manufacturing process.

In step 201, Semiconductor substrate is provided, form insulating barrier in described Semiconductor substrate, and in described insulating barrier, form the copper metal interconnecting wires;

In step 202, form the silicon-rich silicon nitride layer at described insulating barrier and copper metal interconnecting wires;

In step 203, form thermal oxide layer at described silicon-rich silicon nitride layer;

In step 204, form the silicon carbide layer of doping nitrogen at described thermal oxide layer.

The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment just is used for for example and the purpose of explanation, but not is intended to the present invention is limited in the described scope of embodiments.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.

Claims

1. the manufacture method of a semiconductor device comprises:

Semiconductor substrate is provided, forms an insulating barrier in described Semiconductor substrate, and in described insulating barrier, form the copper metal interconnecting wires;

Form the silicon-rich silicon nitride layer at described insulating barrier and copper metal interconnecting wires;

Form thermal oxide layer at described silicon-rich silicon nitride layer;

Form the silicon carbide layer of doping nitrogen at described thermal oxide layer.

2. method according to claim 1 is characterized in that, adopts chemical vapor deposition method to form described silicon-rich silicon nitride layer.

3. method according to claim 1 and 2 is characterized in that, the precursor material that forms described silicon-rich silicon nitride layer comprises silane and ammonia.

4. method according to claim 3 is characterized in that, the flow of described silane is 100-1000sccm.

5. method according to claim 3 is characterized in that, the flow of described ammonia is 100-500sccm.

6. method according to claim 2 is characterized in that, described chemical vapor deposition processes is at pressure 1-7Torr, carries out under the condition of power 50-100W.

7. method according to claim 1 and 2 is characterized in that, the thickness of described silicon-rich silicon nitride layer is the 30-150 dust.

8. method according to claim 1 is characterized in that, adopts chemical vapor deposition method to form described thermal oxide layer.

9. according to claim 1 or 8 described methods, it is characterized in that the precursor material that forms described thermal oxide layer comprises tetraethoxysilane and ozone.

10. method according to claim 9 is characterized in that, the flow of described tetraethoxysilane is 50-500sccm.

11. method according to claim 9 is characterized in that, the flow of described ozone is 50-1000sccm.

12. method according to claim 8 is characterized in that, described chemical vapor deposition processes is to carry out under the condition of pressure 1-7Torr.

13. according to claim 1 or 8 described methods, it is characterized in that the thickness of described thermal oxide layer is the 100-500 dust.

14. method according to claim 1 is characterized in that, adopts chemical vapor deposition method to form the silicon carbide layer of described doping nitrogen.

15. according to claim 1 or 14 described methods, it is characterized in that the thickness of the silicon carbide layer of described doping nitrogen is the 50-300 dust.

16. method according to claim 1 is characterized in that, described silicon-rich silicon nitride layer and described thermal oxide layer consist of double-deck copper metal diffusion barrier layer.

17. method according to claim 1 is characterized in that, the silicon carbide layer of described doping nitrogen consists of the through hole etch stop layer.

18. method according to claim 1 is characterized in that, described insulating barrier is the material layer with low-k.