CN102891124B - Package structure and method for fabricating the same - Google Patents
Package structure and method for fabricating the same Download PDFInfo
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- CN102891124B CN102891124B CN201110229563.4A CN201110229563A CN102891124B CN 102891124 B CN102891124 B CN 102891124B CN 201110229563 A CN201110229563 A CN 201110229563A CN 102891124 B CN102891124 B CN 102891124B
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- trace
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- electrodeposited coating
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- 238000000034 method Methods 0.000 title claims description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 46
- 239000000463 material Substances 0.000 claims abstract description 26
- 239000011248 coating agent Substances 0.000 claims description 64
- 238000000576 coating method Methods 0.000 claims description 64
- 239000002184 metal Substances 0.000 claims description 44
- 238000003466 welding Methods 0.000 claims description 29
- 238000000059 patterning Methods 0.000 claims description 16
- 230000000994 depressogenic effect Effects 0.000 claims description 3
- 229910000679 solder Inorganic materials 0.000 abstract description 11
- 230000000694 effects Effects 0.000 abstract description 10
- 235000002017 Zea mays subsp mays Nutrition 0.000 abstract description 7
- 241000482268 Zea mays subsp. mays Species 0.000 abstract description 7
- 238000004806 packaging method and process Methods 0.000 abstract description 4
- 239000013078 crystal Substances 0.000 abstract 3
- 238000002360 preparation method Methods 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005538 encapsulation Methods 0.000 description 2
- 230000002950 deficient Effects 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 238000005323 electroforming Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/32257—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
A packaging structure and its preparation method, the packaging structure includes putting the crystal cushion, trace, electric contact, the first electroplated layer, the second electroplated layer, the third electroplated layer, the semiconductor chip, encapsulated material and solder mask, the thickness of the trace is smaller than the thickness of the electric contact, the first electroplated layer is formed on one surface of the trace and the electric contact, the second electroplated layer is formed on another surface of the electric contact and the crystal cushion, the third electroplated layer is formed on another surface of the trace, the semiconductor chip is set on the crystal cushion, the encapsulated material coats the semiconductor chip, the first electroplated layer, partial side surface of the trace and partial side surface of the electric contact, the solder mask covers the third electroplated layer, encapsulated material, partial side surface of the trace and partial side surface of the electric contact. The invention can avoid the solder bridging between the trace and the electrical contact, and can prevent the solder mask layer from generating bubbles which can cause popcorn effect.
Description
Technical field
The present invention has about a kind of encapsulating structure and method for making thereof, and espespecially a kind of quad flat is without the encapsulating structure of lead foot and method for making thereof.
Background technology
Along with the evolution of semiconductor packaging, except traditional routing type (wire bonding) semiconductor packaging, current semiconductor package has developed multiple encapsulation kenel, such as quad flat is without lead foot (Quad Flat No-lead, be called for short QFN) semiconductor package, it is placed on a lead frame or loading plate and in addition routing by directly being connect by semiconductor chip, again with encapsulating material this semiconductor chip coated and bonding wire, and bottom encapsulating structure, expose the electrical contact as connecting external electronic.This kind of semiconductor package can reduce overall volume and promote electrical functionality, then becomes a kind of trend of encapsulation.
Refer to Figure 1A, existing quad flat is without the cutaway view of lead foot semiconductor package.As shown in the figure, tradition is as the 6th, 238, 952, 6, 306, 685, 6, 700, 188, or 7, 060, No. 535 U.S.As enclose quad flat disclosed by patent without lead foot semiconductor package by the line layer of its part as trace (trace) 11, and the line layer of another part is as electrical contact (terminal) 12, but, because the distance between trace 11 and electrical contact 12 is usually very little, so be easy to the phenomenon that solder 13 bridge joint (solder bridge) occurs, and cause the generation of defective products, as the trace 11 of Figure 1A lower-left or bottom right and the situation of electrical contact 12.
In order to avoid the problem of above-mentioned solder bridge joint, then the mode be formed at by welding resisting layer between this trace and electrical contact is had, the existing quad flat of another kind as Figure 1B without lead foot semiconductor package cutaway view shown in, but because the distance between trace 11 and electrical contact 12 is too small, easily there is bubble 15 to produce betwixt when inserting this welding resisting layer 14, these bubbles 15 can cause popcorn effect (popcorn effect) in successive process, and then have a strong impact on overall yield.
Therefore, how to avoid above-mentioned variety of problems of the prior art, to make quad flat, without lead foot semiconductor package, solder bridge joint phenomenon or popcorn effect not easily occur, become the problem of desiring most ardently solution at present in fact.
Summary of the invention
Because the disappearance of above-mentioned prior art, main purpose of the present invention is to provide a kind of encapsulating structure and method for making thereof, to avoid the solder bridge joint of this trace and electrical contact, and make this welding resisting layer not easily generation can cause the bubble of popcorn effect.
Encapsulating structure provided by the present invention comprises: put brilliant pad, many traces and multiple electrical contact, it has relative first surface and second surface separately, this is put brilliant pad, trace and electrical contact and flushes each other in this first surface, and the second surface of this trace is depressed in the second surface that this puts brilliant pad and electrical contact; First electrodeposited coating, is formed on the first surface of this trace and the first surface of this electrical contact; Second electrodeposited coating, is formed at the second surface of this electrical contact and this puts on the brilliant second surface padded; 3rd electrodeposited coating, is formed on the second surface of this trace; Semiconductor chip, is located at this and puts on brilliant pad, and be electrically connected to this first electrodeposited coating; Encapsulating material, this semiconductor chip coated, the first electrodeposited coating, the component side surface of trace and the component side surface of electrical contact; And welding resisting layer, cover the 3rd electrodeposited coating, encapsulating material, the component side surface of trace and the component side surface of electrical contact by this second surface side, and there is the welding resisting layer perforate exposing this second electrodeposited coating.
The present invention also provides a kind of method for making of encapsulating structure, comprise: prepare the metal loading plate that has relative first surface and second surface, this metal loading plate has puts brilliant pad, on this first surface, form the first resistance layer, this first resistance layer has the first patterning open region of this metal loading plate of exposed parts; Remove this metal loading plate in this first patterning open region, and form the first recess, and define trace protuberance and electrical contact protuberance; Remove this first resistance layer; On this second surface, form the second resistance layer, this second resistance layer has the second patterning open region of this metal loading plate of exposed parts, and the position of this second patterning open region is to should trace protuberance; Remove this metal loading plate in this second patterning open region, and form the second recess; Remove this second resistance layer; On the end face of this trace protuberance and electrical contact protuberance, form the first electrodeposited coating, and on this second surface, form the second electrodeposited coating to brilliant pad and electrical contact protuberance should be put, and form the 3rd electrodeposited coating in this second recess; Put on brilliant pad in this semiconductor chip is set; This semiconductor chip is electrically connected to this first electrodeposited coating; The encapsulating material of this semiconductor chip coated and the first electrodeposited coating is formed on this metal loading plate; From this second surface remove not by this second electrodeposited coating and the 3rd electrodeposited coating this metal loading plate of covering, and form many traces and multiple electrical contact; The welding resisting layer covering this second electrodeposited coating, the 3rd electrodeposited coating, encapsulating material and metal loading plate is formed from the side of this second surface; And remove this welding resisting layer of part, to form the welding resisting layer perforate exposing this second electrodeposited coating.
The present invention also provides the method for making of another kind of encapsulating structure, comprising: prepare the metal loading plate that has relative first surface and second surface, and this metal loading plate has puts brilliant pad; From this first surface sidesway except this metal loading plate of part, to form the first recess, and define trace protuberance and electrical contact protuberance; From this second surface sidesway except this metal loading plate of part, to form the second recess, the position of this second recess is to should trace protuberance; Put on brilliant pad in this semiconductor chip is set; This semiconductor chip is electrically connected to this trace protuberance and electrical contact protuberance; The encapsulating material of this semiconductor chip coated, trace protuberance and electrical contact protuberance is formed on this metal loading plate; Remove not to this metal loading plate should putting brilliant pad, trace protuberance and electrical contact protuberance from this second surface, and form many traces and multiple electrical contact; The welding resisting layer covering this encapsulating material and metal loading plate is formed from the side of this second surface; And remove this welding resisting layer of part, expose to be formed the welding resisting layer perforate that this puts brilliant pad and electrical contact.
As from the foregoing, encapsulating structure of the present invention is by reducing the thickness of trace, increase to make the distance between trace and electrical contact, therefore the welding resisting layer of follow-up covering is easier to be filled between trace and electrical contact, and not easily have bubble to produce, final can reach can not solder bridge joint with can not cause the two-fold advantage of popcorn effect, and thus yield also improves.
Accompanying drawing explanation
Figure 1A is the cutaway view of a kind of existing quad flat without lead foot semiconductor package;
Figure 1B is the cutaway view of another kind of existing quad flat without lead foot semiconductor package; And
Fig. 2 A to Fig. 2 K is the cutaway view of encapsulating structure of the present invention and method for making thereof, wherein, and another embodiment that Fig. 2 K ' is Fig. 2 K.
Primary clustering symbol description
Embodiment
Below by way of particular specific embodiment, embodiments of the present invention are described, those skilled in the art can understand other advantage of the present invention and effect easily by content disclosed in the present specification.
Notice, structure, ratio, size etc. that this specification institute accompanying drawings illustrates, content all only in order to coordinate specification to disclose, for understanding and the reading of those skilled in the art, and be not used to limit the enforceable qualifications of the present invention, therefore the not technical essential meaning of tool, the adjustment of the modification of any structure, the change of proportionate relationship or size, do not affecting under effect that the present invention can produce and the object that can reach, still all should drop on disclosed technology contents and obtain in the scope that can contain.Simultaneously, quote in this specification as " on ", " top ", " end ", the term such as " side " and " ", be also only be convenient to describe understand, and be not used to limit the enforceable scope of the present invention, its change of relatively closing or adjustment, under changing technology contents without essence, also when being considered as the enforceable category of the present invention.
Refer to Fig. 2 A to Fig. 2 K, the cutaway view of encapsulating structure of the present invention and method for making thereof, wherein, another embodiment that Fig. 2 K ' is Fig. 2 K.
First, as shown in Figure 2 A, prepare one and there is relative first surface 20a and the metal loading plate 20 of second surface 20b, this metal loading plate 20 has puts brilliant pad 20c, formation first resistance layer 21 on this first surface 20a, this first resistance layer 21 has the first patterning open region 210 of this metal loading plate 20 of exposed parts.
As shown in Figure 2 B, remove this metal loading plate 20 of part in this first patterning open region 210, and form the first recess 202 and this is put brilliant pad 20c puts brilliant recess 201, and define trace protuberance 203a and electrical contact protuberance 203b.
As shown in Figure 2 C, this first resistance layer 21 is removed.
As shown in Figure 2 D, formation second resistance layer 22 on this second surface 20b, this second resistance layer 22 has the second patterning open region 220 of this metal loading plate 20 of exposed parts, and the position of this second patterning open region 220 is to should trace protuberance 203a.
As shown in Figure 2 E, remove this metal loading plate 20 of part in this second patterning open region 220, and form the second recess 204.
As shown in Figure 2 F, this second resistance layer 22 is removed.
As shown in Figure 2 G, the first electrodeposited coating 23 is formed on the end face of this trace protuberance 203a and electrical contact protuberance 203b, and formed the second electrodeposited coating 24 should putting brilliant recess 201 and electrical contact protuberance 203b on this second surface 20b, and form the 3rd electrodeposited coating 25 in this second recess 204; Wherein, the mode of this first electrodeposited coating 23, second electrodeposited coating 24 of above-mentioned formation and the 3rd electrodeposited coating 25 is can first form the resistance layer with open region, and electroplate in this open region, finally remove this resistance layer again and complete, what aforementioned electro forming method should be art knows that the knowledgeable can understand usually, therefore at this not icon and detailed description in addition.
As illustrated in figure 2h, semiconductor chip 26 is provided, this semiconductor chip 26 has relative acting surface 26a and non-active face 26b, be placed in this by adhesion coating 27 put brilliant recess 201 so that this non-active face 26b is connect, and by multiple bonding wire 28, this semiconductor chip 26 is electrically connected to this first electrodeposited coating 23, and on this metal loading plate 20, form the encapsulating material 29 of this semiconductor chip 26 coated, bonding wire 28 and the first electrodeposited coating 23.
As shown in figure 2i, from this second surface 20b remove not by this second electrodeposited coating 24 and the 3rd electrodeposited coating 25 this metal loading plate 20 of covering, and form many traces 205 and multiple electrical contact 206.
As shown in fig. 2j, the welding resisting layer 30 covering this second electrodeposited coating 24, the 3rd electrodeposited coating 25, encapsulating material 29 and metal loading plate 20 is formed from that side of this second surface 20b.
As shown in figure 2k, remove this welding resisting layer 30 of part, to form the welding resisting layer perforate 300 exposing this second electrodeposited coating 24, in the present embodiment, the bottom surface of the 3rd electrodeposited coating 25 finally protrudes from the bottom surface of this encapsulating material 29; Or in another embodiment such as shown in Fig. 2 K ', the bottom surface of the 3rd electrodeposited coating 25 finally flushes with the bottom surface of this encapsulating material 29.
In aforesaid method for making, the mode removing this metal loading plate 20 can be etching.
The present invention also discloses a kind of encapsulating structure, comprise: put brilliant pad 20c, many traces 205 and multiple electrical contact 206, it has relative first surface 20a and second surface 20b separately, this is put brilliant pad 20c, trace 205 and electrical contact 206 and flushes each other in this first surface 20a, and the second surface 20b of this trace 205 is depressed in the second surface 20b that this puts brilliant pad 20c and electrical contact 206; First electrodeposited coating 23, is formed on the first surface 20a of this trace 205 and first surface 20a of this electrical contact 206; Second electrodeposited coating 24, is formed at the second surface 20b of this electrical contact 206 and this is put and brilliantly pads on the second surface 20b of 20c; 3rd electrodeposited coating 25, is formed on the second surface 20b of this trace 205; Semiconductor chip 26, is located at this and puts on brilliant pad 20c, and be electrically connected to this first electrodeposited coating 23; Encapsulating material 29, coated this semiconductor chip 26, first electrodeposited coating 23, the component side surface of trace 205 and component side surface of electrical contact 206; And welding resisting layer 30, cover the 3rd electrodeposited coating 25, encapsulating material 29, the component side surface of trace 205 and the component side surface of electrical contact 206 by this second surface 20b side, and there is the welding resisting layer perforate 300 exposing this second electrodeposited coating 24.
According to upper described encapsulating structure, in this put brilliant pad 20c can be formed be communicated to this first surface 20a put brilliant recess 201, and this semiconductor chip 26 can be located at this and put in brilliant recess 201.
In aforesaid encapsulating structure, the bottom surface of the 3rd electrodeposited coating 25 can flush with the bottom surface of this encapsulating material 29, or the bottom surface of the 3rd electrodeposited coating 25 can protrude from the bottom surface of this encapsulating material 29.
Again in encapsulating structure of the present invention, this semiconductor chip 26 is electrically connected to this first electrodeposited coating 23 by multiple bonding wire 28.
In sum, compared to prior art, encapsulating structure of the present invention is by reducing the thickness of trace to strengthen the distance between trace and electrical contact, therefore follow-up welding resisting layer is easier to fill up, and not easily have bubble to produce, final namely reaching can not solder bridge joint and the two-fold advantage that can not cause popcorn effect, and significantly improves yield.
Above-described embodiment only in order to illustrative principle of the present invention and effect thereof, but not for limiting the present invention.Any those skilled in the art all without prejudice under spirit of the present invention and category, can modify to above-described embodiment.Therefore the scope of the present invention, should listed by claims.
Claims (11)
1. an encapsulating structure, comprising:
Put brilliant pad, many traces and multiple electrical contact, it has relative first surface and second surface separately, this is put brilliant pad, trace and electrical contact and flushes each other in this first surface, and the second surface of this trace is depressed in the second surface that this puts brilliant pad and electrical contact;
First electrodeposited coating, is formed on the first surface of this trace and the first surface of this electrical contact;
Second electrodeposited coating, is formed at the second surface of this electrical contact and this puts on the brilliant second surface padded;
3rd electrodeposited coating, is formed on the second surface of this trace;
Semiconductor chip, is located at this and puts on brilliant pad, and be electrically connected to this first electrodeposited coating;
Encapsulating material, this semiconductor chip coated, the first electrodeposited coating, the component side surface of trace and the component side surface of electrical contact; And
Welding resisting layer, the 3rd electrodeposited coating, encapsulating material, the component side surface of trace and the component side surface of electrical contact is covered by this second surface side, and this welding resisting layer is filled between this trace and this electrical contact, this welding resisting layer has the welding resisting layer perforate exposing this second electrodeposited coating.
2. encapsulating structure according to claim 1, is characterized in that, in this put brilliant pad be formed be communicated to this first surface put brilliant recess, and this semiconductor chip is located at this and is put in brilliant recess.
3. encapsulating structure according to claim 1, is characterized in that, the bottom surface of the 3rd electrodeposited coating protrudes from the bottom surface of this encapsulating material.
4. encapsulating structure according to claim 1, is characterized in that, this semiconductor chip is electrically connected to this first electrodeposited coating by multiple bonding wire.
5. a method for making for encapsulating structure, comprising:
Prepare the metal loading plate that has relative first surface and second surface, this metal loading plate has puts brilliant pad, and on this first surface, form the first resistance layer, this first resistance layer has the first patterning open region of this metal loading plate of exposed parts;
Remove this metal loading plate in this first patterning open region, and form the first recess, and define trace protuberance and electrical contact protuberance;
Remove this first resistance layer;
On this second surface, form the second resistance layer, this second resistance layer has the second patterning open region of this metal loading plate of exposed parts, and the position of this second patterning open region is to should trace protuberance;
Remove this metal loading plate in this second patterning open region, and form the second recess;
Remove this second resistance layer;
On the end face of this trace protuberance and electrical contact protuberance, form the first electrodeposited coating, and on this second surface, form the second electrodeposited coating to brilliant pad and electrical contact protuberance should be put, and form the 3rd electrodeposited coating in this second recess;
Put on brilliant pad in this semiconductor chip is set;
This semiconductor chip is electrically connected to this first electrodeposited coating;
The encapsulating material of this semiconductor chip coated and the first electrodeposited coating is formed on this metal loading plate;
From this second surface remove not by this second electrodeposited coating and the 3rd electrodeposited coating this metal loading plate of covering, and form many traces and multiple electrical contact;
The welding resisting layer covering this second electrodeposited coating, the 3rd electrodeposited coating, encapsulating material and metal loading plate is formed from the side of this second surface; And
Remove this welding resisting layer of part, to form the welding resisting layer perforate exposing this second electrodeposited coating.
6. the method for making of encapsulating structure according to claim 5, is characterized in that, this metal loading plate removed in this first patterning open region is also included in this and puts in brilliant pad to form and put brilliant recess, and this semiconductor chip is located at this and is put in brilliant recess.
7. the method for making of encapsulating structure according to claim 5, is characterized in that, the bottom surface of the 3rd electrodeposited coating protrudes from the bottom surface of this encapsulating material.
8. the method for making of encapsulating structure according to claim 5, is characterized in that, this semiconductor chip is electrically connected to this first electrodeposited coating by multiple bonding wire.
9. a method for making for encapsulating structure, comprising:
Prepare the metal loading plate that has relative first surface and second surface, this metal loading plate has puts brilliant pad;
From this first surface sidesway except this metal loading plate of part, to form the first recess, and define trace protuberance and electrical contact protuberance;
From this second surface sidesway except this metal loading plate of part, to form the second recess, the position of this second recess is to should trace protuberance;
Put on brilliant pad in this semiconductor chip is set;
This semiconductor chip is electrically connected to this trace protuberance and electrical contact protuberance;
The encapsulating material of this semiconductor chip coated, trace protuberance and electrical contact protuberance is formed on this metal loading plate;
Remove not to this metal loading plate should putting brilliant pad, trace protuberance and electrical contact protuberance from this second surface, and form many traces and multiple electrical contact;
Form from the side of this second surface the welding resisting layer covering this encapsulating material and metal loading plate, and this welding resisting layer is filled between this trace and this electrical contact; And
Remove this welding resisting layer of part, expose to be formed the welding resisting layer perforate that this puts brilliant pad and electrical contact.
10. the method for making of encapsulating structure according to claim 9, is characterized in that, puts brilliant pad to form from this first surface sidesway and puts brilliant recess except this metal loading plate of part is also included in this, and this semiconductor chip is located at this and is put in brilliant recess.
The method for making of 11. encapsulating structures according to claim 9, is characterized in that, this semiconductor chip is electrically connected to this trace protuberance and electrical contact protuberance by multiple bonding wire.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100125400 | 2011-07-19 | ||
| TW100125400A TWI441296B (en) | 2011-07-19 | 2011-07-19 | Package structure and fabrication method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
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| US6306685B1 (en) * | 2000-02-01 | 2001-10-23 | Advanced Semiconductor Engineering, Inc. | Method of molding a bump chip carrier and structure made thereby |
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| US8115285B2 (en) * | 2008-03-14 | 2012-02-14 | Advanced Semiconductor Engineering, Inc. | Advanced quad flat no lead chip package having a protective layer to enhance surface mounting and manufacturing methods thereof |
| US20110042794A1 (en) * | 2008-05-19 | 2011-02-24 | Tung-Hsien Hsieh | Qfn semiconductor package and circuit board structure adapted for the same |
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| TWI441296B (en) | 2014-06-11 |
| TW201306201A (en) | 2013-02-01 |
| CN102891124A (en) | 2013-01-23 |
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