CN102830345B - FPGA (field programmable gate array) test configuration analyzing and evaluating method based on configuration dictionary - Google Patents
FPGA (field programmable gate array) test configuration analyzing and evaluating method based on configuration dictionary Download PDFInfo
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Abstract
The invention discloses an FPGA (field programmable gate array) test configuration analyzing and evaluating method based on a configuration dictionary and relates to a programmable logic piece technology, which is used for analyzing and evaluating the completeness of FPGA test configuration. The method comprises the steps of firstly establishing the configuration dictionary of the FPGA in combination with the structure characteristics of FPGA; secondly analyzing the test configuration by adopting a modulation method, and calculating the coverage rate of the test configuration to the configuration dictionary; and finally evaluating the completeness of the test configuration according to the calculated coverage rate. With the adoption of the method, the test configuration of the FPGA can be analyzed and evaluated rapidly without fault simulation, including the steps of analyzing all testable or untestable FPGA resources of the test configuration, and evaluating the completeness of the test configuration, so that instructing the improvement of the FPGA test configuration is instructed, and the development efficiency of the FPGA test configuration is improved.
Description
Technical field
The present invention relates to technology of CPLD field, is that one kind is tested suitable for FPGA
The assay method of configuration.
Background technology
Field programmable gate array (FPGA) is a kind of field programmable gate function, by programmed logical module (CLB), even
Line resource, input/output module (IOB) are constituted.Wherein programmed logical module is used for realizing the logic function of subscriber's line circuit；Even
Line resource is used for providing the annexation between logical block；Input/output module is used for allowing user to define input/output signal.Configuration
File is stored in chip external memory (such as PROM), and the configuration mode provided by FPGA is downloaded in chip, so as to realize phase
The circuit function answered.
FPGA is a kind of complicated IC-components.If the Virtex-2 Series FPGAs of Xilinx companies are comprising millions of
Individual gate, and millions of circuit connections.If some of them gate circuit or line occur defect, and (defect is a kind of physics
Damage, introduce during production, transport, use), circuit cisco unity malfunction can be caused.So will carry out to FPGA complete
Test, with ensure device be in acceptable quality level.
A major issue in integrated circuit testing is exactly that test vector is estimated, and it has influence on the efficiency of test
And the quality of test.In field tests by setting up fault model, reflect physical imperfection with logic fault, and covered by failure
Lid rate is estimated to test vector.Such as conventional stuck-at fault model, it is assumed that circuit node keeps fixed logical value no matter
Which type of logical value drives the circuit node, and it is all fixed as 0 or fixes 1, for the open circuit or short-circuit scarce reflected in circuit
Fall into.Fault coverage is the ratio of the fault model and all fault models tested.
The test vector of FPGA includes test configurations, test and excitation and test response.In test process, apply test configurations
Time be Millisecond, it is Microsecond grade to apply test and excitation, obtain testing the time for responding and comparing, and the testing time is main
Determined by setup time.FPGA tests need Test Engineer to develop special test configurations, and these test configurations need to carry out failure
Coverage rate assessment is to improve fault coverage, and reduces the test configurations number of needs.At present, currently for FPGA test configurations
Evaluation methodology also mainly using fault simulation method.But the expansion of the scale with FPGA, is calculated by fault simulation and is surveyed
The method of the vectorial fault coverage of examination takes very much, the XCV1000E about 1000K gate of series of such as Xilinx, leads to
Crossing fault simulation assessment fault coverage needs hundreds of hours.Therefore need to study the quick assay of FPGA test configurations
Method, to improve the development efficiency of test configurations.
The content of the invention
The purpose of the present invention is to disclose a kind of FPGA test configurations assay methods based on configuration dictionary, for analyzing
Evaluate the completeness of FPGA test configurations.
For reaching above-mentioned purpose, the technical solution of the present invention is：
A kind of FPGA test configurations assay methods based on configuration dictionary, match somebody with somebody for field programmable gate array test
Put, which comprises the following steps：
(1) set up the configuration dictionary of the basic programmable unit of field programmable gate array；
(2) resource according to test configurations test, sets up the analysis template of test configurations；
(3) set up the configuration dictionary corresponding to analysis template；
(4) process is analyzed parallel using Templated method to test configurations；
(5) result according to analyzing and processing, evaluates to the completeness of test configurations, and analyzes this group of test configurations institute
Have and can survey and immesurable resource.
Described test configurations assay method, in its described field programmable gate array, basic programmable unit matches somebody with somebody
Dictionary is put, has to comprising test configurations and often assemble put correspondence measurable failure structure when being tested by basic programmable unit
Into for evaluating to the completeness of basic programmable unit configuration code；The analysis method of test configurations, it is all comprising setting up
The step of configuration dictionary of basic programmable unit.
Described test configurations assay method, test configurations analysis template in (2) step described in which, with field-programmable
Based on the functional unit of gate array, and corresponding to the resource of test configurations test；Each module in field programmable gate array
Function is different, and relatively independent, is separately carried out during test mostly, and during test, special test configurations are entered just for specific resource
Row test, sets up different templates according to the resource of test configurations test, flexibly to analyze the test configurations of different resource.
Described test configurations assay method, corresponding to the configuration dictionary for analyzing template in (3) step described in which, with base
Based on the configuration dictionary of this programmable unit, while considering the measurability of basic programmable unit in template；Matching somebody with somebody in template
Put dictionary to evaluate to the completeness to template configuration code, and according to completeness evaluate result determine analysis template in can
Survey and immesurable resource.
Described test configurations assay method, Templated method in (4) step described in which, is to utilize field-programmable
The characteristics of gate array repeat array structure, the analyzing and processing to whole test configurations is realized by the multiplexing of template；All templates
Analysis carry out parallel, so as to reduce the run time of methods described.
Described test configurations assay method, the completeness of evaluation test configuration in (5) step described in which, according to test
The coverage condition of the configuration configuration code to be tested to all basic programmable units in FPGA, the completeness to this group of test configurations
Evaluated；Or according to the corresponding fault model of configuration code in configuration dictionary, calculate the fault coverage that test configurations can reach.
A kind of FPGA test configurations assay methods based on configuration dictionary of the present invention, just can be right without the need for fault simulation
The test configurations of FPGA carry out quick assay：Test configurations are all surveys and immesurable FPGA resource for analysis, evaluate
The completeness of test configurations.Such that it is able to instruct the improvement of FPGA test configurations, the development efficiency of FPGA test configurations is improved.
Description of the drawings
Fig. 1 is a kind of FPGA test configurations assay method flow schematic diagrams based on configuration dictionary of the present invention；
Fig. 2 is the basic programmable unit schematic diagram in FPGA；Wherein：
Fig. 2 a are by the MUX (MUX) at SRAM control selections end；
Fig. 2 b are the buffers (BUF) for being controlled gating by SRAM；
Fig. 2 c are the lookup logic tables (LUT) for being made up of memory element SRAM；
Configuration dictionary schematic diagrams of the Fig. 3 for the basic programmable units of FPGA；Wherein：
Fig. 3 a are the configuration dictionaries of MUX；
Fig. 3 b are the configuration dictionaries of BUF；
Fig. 3 c are the configuration dictionaries of two input LUT under persistent fault；
Test configurations processing template schematic diagrams of the Fig. 4 for fpga logic functional module；
Fig. 5 is that basic programmable unit is corresponding in template configures dictionary schematic diagram.
Specific embodiment
In order that those skilled in the art more fully understand the present invention program, below in conjunction with accompanying drawing and implementation pair
A kind of FPGA test configurations assay methods based on configuration dictionary of the present invention are described in further detail.Fig. 1 is this
The concrete execution flow process of bright method, below in conjunction with the embodiment that the step in Fig. 1 describes the inventive method in detail.
Step 101 sets up the configuration dictionary of basic programmable unit in FPGA.Basic programmable unit such as Fig. 2 in FPGA
Shown, Fig. 2 a are by the MUX (MUX) at SRAM control selections end, wherein M0It is the SRAM control bits of MUX, works as M0It is 0
When, input a is strobed into outfan O；Work as M0When being 1, input b is strobed into outfan O.Fig. 2 b are gated by SRAM controls
Buffer (BUF), wherein M0It is the SRAM control bits of BUF, works as M0When being 0, BUF disconnects, and the value of outfan o does not receive input i values
Impact；Work as M0When being 1, BUF conductings, the value of outfan o are consistent with the value of input i.Fig. 2 c are to be made up of to deposit SRAM
The lookup logic table (LUT) of storage unit, wherein M0To Mm- 1 is the SRAM control bits of LUT, and the value of m is 2k, k is the input of LUT
Number.To M0To Mm- 1 carries out different configurations, it is possible to achieve the logic function of different k inputs.These basic programmable units
Programmable wiring and the logical resource of FPGA is constituted, is the basis that FPGA programmable functions are realized.Basic programmable unit
Measurability is related to configuration code, and under single configuration code, only partial fault can be surveyed, and its complete test needs multiple configuration codes.
For example to the MUX in Fig. 2 a, its input is controllable, exports Observable.As configuration bit M0For 0 when, on input a and outfan c
Failure can be surveyed.As configuration bit M0For 1 when, the failure on input b and outfan c can be surveyed.The complete test request of MUX this two
Plant and tested under configuration code respectively.Based on the fact that, it is proposed that a kind of assay method of TC：By analyzing TC to base
The coverage rate of the configuration code of this programmable unit, is analyzed and evaluated to TC.Calculating of the TC to configuration dictionary coverage rate, is borrowed first
The concept of mirror fault dictionary, sets up the configuration dictionary of the basic programmable units of FPGA.Fault dictionary is built during fault simulation
Vertical error listing, comprising chip test in need failure, the process of fault simulation be exactly analyze fault dictionary in include
Result at the end of the measurability of failure, fault simulation according to analysis calculates the fault coverage of test vector.Substantially may be programmed
The configuration dictionary of unit has to measurable fault model under the test configurations for including and corresponding configuration and constitutes when being tested by which, right
Whether the analysis process of TC is exactly to analyze in TC comprising the configuration code in configuration dictionary..Fig. 3 is programmable elementary cell in FPGA
Configuration dictionary, Fig. 3 a are the configuration dictionaries of MUX, a in figures0Represent the stuck at 0 fault of MUX input a, as1Represent MUX inputs
The stuck at 1 fault of end a, bs0Represent the stuck at 0 fault of MUX input b, bs1Represent the stuck at 1 fault of MUX input a, os0Table
Show the stuck at 0 fault of MUX output o, os1Represent the stuck at 1 fault of MUX output o, M0s0Represent MUX configuration bit M0Fix 0
Failure, M0s1Represent MUX configuration bit M0Stuck at 1 fault.Fig. 3 b are the configuration dictionaries of BUF, i in figures0Represent BUF input i's
Stuck at 0 fault, is1Represent the stuck at 1 fault of BUF input i, os0Represent the stuck at 0 fault of BUF outfan o, os1Represent BUF
The stuck at 1 fault of outfan o, M0s0Represent BUF configuration bit M0Stuck at 0 fault, M0s1Represent BUF configuration bit M0Fix 1 therefore
Barrier.Fig. 3 c are the two configuration dictionaries for being input into LUT, M in figure under persistent fault0s1, M1s1, M2s1, M3s1Correspondence LUT configurations are represented respectively
Position M0, M1, M2, M3Stuck at 1 fault, M0s0, M1s0, M2s0, M3s0Correspondence configuration bit M is represented respectively0, M1, M2, M3Fix 0 therefore
Barrier.i0s1, i1s1The stuck at 1 fault of correspondence input, i is represented respectively0s0, i1s0Represent correspondence LUT inputs respectively fixes 0 event
Barrier, os0Represent the stuck at 0 fault of LUT outfan o, os1Represent the stuck at 1 fault of LUT outfan o.Wherein MUX's and BUF matches somebody with somebody
Put dictionary to be made up of its all test configurations, only need to LUT partial test configuration just complete its complete test, to different events
Hinder the configured number difference of its needs of model, be the fault dictionary of two input LUT under fault model in Fig. 3 c.
The resource that step 102 is tested according to test configurations, sets up corresponding test configurations processing template.Logic in FPGA
Resource module, interconnection resources and input/output module function are different and relatively independent, to their test point when FPGA is tested
Drive row into, special FPGA test configurations are just for specific resource in FPGA, therefore need to only be directed to the complete of resource to be tested
Standby property is estimated.The processing template of test configurations, FPGA are the two-dimensional structure arrays that a large amount of repeat function units are constituted, with work(
The processing template of TC is set up based on energy module, only a limited number of template need to be set up, and be can be achieved with to whole by multiplexing
The analyzing and processing of FPGA test configurations.Fig. 4 is the example of FPGA basic logic module templates.
Step 103 sets up the configuration dictionary corresponding to template.The configuration dictionary of template is with the configuration of basic programmable unit
Based on dictionary, while considering the measurability of basic programmable unit in template.For example to the MUX S in Fig. 4 templates0, work as S1,
S2Configuration code be 11 when, S0Output it is unobservable, now analyze S0Configuration it is nonsensical, therefore S in template0Configuration
Dictionary will consider S1, S2Impact, then it is original configuration dictionary on the basis of add S0S during Observable1, S2Configuration code, in template
S0Configuration dictionary it is as shown in Figure 5.True value in Fig. 5 corresponding to configuration bit has three groups, and this three groups of configuration codes match somebody with somebody code for of equal value, it
Corresponding MUX S0The failure for measuring is identical, measures one of them and just can consider that this assembles to put and surveys.To other function lists
In first, other programmable units do similar process, set up the configuration dictionary of template.
Step 104 to 107 is that test configurations are analyzed with process, to a test configurations (104), is tested first
The configuration code of all functional modules take out, and dictionary configured to which according to the measurability of functional module port under test configurations enter
Row adjustment (105).Then process is analyzed to the test configurations of all templates parallel, the configuration code of template is configured into word with which
Allusion quotation is compared, if effective configuration of the configuration code comprising configuration dictionary, the configuration code is labeled as surveying, while by configuration code
Corresponding fault flag is to survey (106).Templated method only analyzes the functional module that test configurations are tested, and simplifies survey
The difficulty of examination Allocation Analysis, increased versatility and the motility of the present invention, be easy to the transplanting and extension of the present invention, according to function
Adjustment of the module port measurability to configuration dictionary, solves the problem analysis of failed transmission between module.Simultaneously to all of
Template is processed parallel, makes the run time of the present invention unrelated with the scale of FPGA in theory, the expansion of FPGA scales, simply
Increased the template number of parallel processing.
Test configurations are evaluated (108), and are analyzed by the result that step 108 to 109 is analyzed and processed according to test configurations
This group of test configurations are all to be surveyed and immesurable FPGA resource (109).Substantially can be compiled to all in FPGA according to test configurations
The coverage condition of configuration code Cheng Danyuan to be tested, can evaluate to the completeness of this group of test configurations, and test is arrived more
Configuration code, it is meant that the completeness of this group of test configurations is higher.According to the corresponding fault model of configuration code, it is also possible to calculate and survey
Trial puts the fault coverage that can be reached.Simultaneously according to the basic programmable unit configuration code surveyed in template He do not survey, can be with
It is all in quick positioning FPGA to survey and immesurable resource, it is easy to instruct the improvement of test configurations, there is provided fault coverage.Step
The execution flow process of rapid 110 the inventive method terminates.
The inventive method is not limited by specific implementation method.
Claims (4)
1. a kind of FPGA test configurations assay methods based on configuration dictionary, match somebody with somebody for field programmable gate array test
Put, it is characterised in that：Comprise the steps of：
1) set up the configuration dictionary of the basic programmable unit of field programmable gate array；
2) resource according to test configurations test, sets up the analysis template of test configurations；
3) set up the configuration dictionary corresponding to analysis template；
4) process is analyzed parallel using Templated method to test configurations；
5) according to analyzing and processing result, the completeness of test configurations is evaluated, and analyze test configurations it is all survey and
Immesurable resource；
Wherein, in the field programmable gate array basic programmable unit configuration dictionary, tested by basic programmable unit
When have to the test configurations that include and the measurable failure of test configurations correspondence is constituted, for testing to basic programmable unit
The completeness of configuration is evaluated；It is described that test configurations are analyzed with process, comprising setting up all basic programmable units
The step of configuration dictionary；
5) in the step, the completeness of evaluation test configuration, will survey to all basic programmable units in FPGA according to test configurations
The coverage condition of the configuration code of examination, evaluates to the completeness of test configurations；Or according to corresponding to analysis template test configuration
Fault model, calculate the fault coverage that can reach of test configurations.
2. test configurations assay method as claimed in claim 1, it is characterised in that：2) test configurations analysis in the step
Template, based on the basic programmable unit of field programmable gate array, and corresponding to the resource of test configurations test；Scene
In programmable gate array, the function of each module is different, and relatively independent, separately carries out mostly, special test during test during test
Configuration is tested just for specific resource, sets up different templates according to the resource of test configurations test, flexibly to analyze
The test configurations of different resource.
3. test configurations assay method as claimed in claim 1, it is characterised in that：3) corresponding to analysis mould in the step
The configuration dictionary of plate, based on the configuration dictionary of basic programmable unit, while consider basic programmable unit in template
Measurability；Configuration dictionary in template is evaluated to the completeness to test configurations, and the result evaluated according to completeness
Determine to survey and immesurable resource in analysis template.
4. test configurations assay method as claimed in claim 1, it is characterised in that：4) Templated side in the step
The characteristics of method is using field programmable gate array repeat array structure, is realized to whole test configurations by the multiplexing of template
Analyzing and processing；The analysis of all templates is carried out parallel, so as to reduce the run time of methods described.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6594610B1 (en) * | 2001-02-21 | 2003-07-15 | Xilinx, Inc. | Fault emulation testing of programmable logic devices |
| CN1488953A (en) * | 2002-10-08 | 2004-04-14 | ƽ | Method for predicting plate-detection coverage rate |
| CN101561777A (en) * | 2008-04-14 | 2009-10-21 | 中兴通讯股份有限公司 | System and method for realizing coverage rate test |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6594610B1 (en) * | 2001-02-21 | 2003-07-15 | Xilinx, Inc. | Fault emulation testing of programmable logic devices |
| CN1488953A (en) * | 2002-10-08 | 2004-04-14 | ƽ | Method for predicting plate-detection coverage rate |
| CN101561777A (en) * | 2008-04-14 | 2009-10-21 | 中兴通讯股份有限公司 | System and method for realizing coverage rate test |
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