CN102751982B - Clock selection circuit suitable for backboard spending treatment of communication equipment - Google Patents
Clock selection circuit suitable for backboard spending treatment of communication equipment Download PDFInfo
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- CN102751982B CN102751982B CN201210239046.XA CN201210239046A CN102751982B CN 102751982 B CN102751982 B CN 102751982B CN 201210239046 A CN201210239046 A CN 201210239046A CN 102751982 B CN102751982 B CN 102751982B
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Abstract
The invention relates to a clock selection circuit suitable for backboard spending treatment of communication equipment. The clock selection circuit utilizes an FPGA (field programmable gata array) of a field programmable device on a single plate to be realized, and is provided with a double phase-locked loop structure which can automatically and rapidly reset; and the clock selection circuit comprises first and second clock losing detection units, first and second automatic reset signal generating units, first and second phase-locked loop reset signal generating units, first and second phase locking loop (PLL) units and a clock selection unit MUX (multiplexer). The clock selection circuit suitable for the backboard spending treatment of the communication equipment, provided by the invention, solves the problems that a phase position of a backboard spending clock needs to be adjusted, a utilized phase locked loop circuit is easy for loose of lock when a main preparing clock source is switched; and the clock selection circuit has an automatic rapid resetting function when the phase locking loop is in the loose of lock, the resource requirement on single plate software is reduced, losing lock times of the phase locking loop can be reduced to the greatest extent, and the stability of a system is improved.
Description
Technical field
The present invention relates to the selection circuit of backboard expense clock, is a kind of clock selection circuit that is applicable to communication equipment back plate overhead processing specifically.That is: be applicable to the selection circuit of communication equipment dorsulum expense clock, espespecially utilize field programmable device (FPGA) on veneer to realize, the clock selection circuit of the backboard overhead processing of the two phase-locked loop structure of automatic Rapid reset while possessing phase-locked loop losing lock.
Background technology
In order to ensure the performance of communication equipment, for the unit of some particular importance, such as the Hot Spare of employing 1+1 conventionally such as cross board, clock board, master control borad, in the time that primary veneer breaks down, can be switched to automatically standby board work, the normally operation to ensure communication equipment not interrupt.Between cross board, master control borad and the wiring board of communication equipment, carry out board-to-board information transmission by backboard overhead bus, the expense clock of these veneers derives from master/backup clock plate, when equipment is normally worked, need to switch according to the standby usage state of clock board, select active clock sending and receiving expense.
In order to develop the communication equipment of stable performance, generally all formulate backboard overhead bus specification in the equipment development stage, the overhead signal output timing of each veneer on equipment (including but not limited to cross board, clock board, master control borad etc.) is all followed this specification, so also be conducive to the follow-up maintenance work of each veneer, a wherein veneer of change of avoiding not meeting backboard specification and cause, another associated piece veneer also needs the problem of change.
Follow backboard overhead bus specification and correct sampling input overhead signal in order to ensure to export the sequential of overhead signal, sometimes need to adjust the phase place of expense clock.Special phase place adjustment, such as adjusting 180 degree to realize by inverter, phase place postpones the less number of degrees backward, can realize by add delay cell on clock path.Can only adjust the phase place of 180 degree by inverter, can play the object of phase modulation by adding delay cell, but be difficult for accurately controlling, so the application scenario of these two kinds of methods is limited.Adopt phase-locked loop to adjust a kind of mode that phase place is most convenient, but while switching in master/backup clock source, phase-locked loop is easy to losing lock, must resets and could normally work, conventionally resetted by board software.
Summary of the invention
For the defect existing in prior art, the object of the present invention is to provide a kind of clock selection circuit that is applicable to communication equipment back plate overhead processing, solve in the time need to adjusting the phase place of backboard expense clock, the problem of easy losing lock when the phase-locked loop circuit using switches in master/backup clock source, the function of automatic Rapid reset while possessing phase-locked loop losing lock, reduce the resource requirement to board software, and can at utmost reduce phase-locked loop losing lock number of times, improve the stability of system.
For reaching above object, the technical scheme that the present invention takes is:
A kind of clock selection circuit that is applicable to communication equipment back plate overhead processing, it is characterized in that: this circuit is to utilize the on-site programmable device FPGA on veneer to realize, the clock selection circuit of the backboard overhead processing of the two phase-locked loop structure of automatic Rapid reset while possessing phase-locked loop losing lock.
On the basis of technique scheme, this clock selection circuit comprises:
First, second loss of clock detecting unit, first, second signal generation unit that automatically resets, first, second phase-locked loop reset signal generation unit, first, second phase-locked loop pll unit and a clock selecting unit MUX,
Clock selecting cell call on-site programmable gate array FPGA manufacturer provides logic primitive,
Phase locked-loop unit is directly called the IP kernel that on-site programmable gate array FPGA manufacturer provides,
Loss of clock detecting unit, automatically reset signal generation unit and phase-locked loop reset signal generation unit adopt hardware description language to design, and then utilize FPGA design tool to carry out comprehensively, and generation can download to the BIT file of fpga chip,
Active clock plate produces active clock SCLKA, and standby clock plate produces standby clock SCLKB,
Two phase locked-loop unit are respectively used to adjust the clock phase of active clock SCLKA and standby clock SCLKB, and export the active clock SCLKA_PLL_A adjusting after phase place and adjust the standby clock SCLKA_PLL_B after phase place,
Clock selecting unit receives the clock of two phase locked-loop unit outputs and after selecting, exports the clock sclk after selecting, and the selection signal SEL_AB of clock selecting unit is determined by the operating state of active clock plate and standby clock plate.
On the basis of technique scheme, first, second phase-locked loop reset signal generation unit produces respectively the first phase-locked loop reset signal RST_PLL_A and the second phase-locked loop reset signal RST_PLL_B,
The first phase locked-loop unit is carried out reset operation according to the first phase-locked loop reset signal RST_PLL_A,
The second phase locked-loop unit is carried out reset operation according to the second phase-locked loop reset signal RST_PLL_B.
On the basis of technique scheme, automatically reset signal RST_UNLOCKED_A and active clock of the comprehensive CPU direct reduction of the first phase-locked loop reset signal generation unit signal RST_CPU, the first phase-locked loop losing lock lost alarm signal LOS_CLK_A and carries out after exclusive disjunction, form the first phase-locked loop reset signal RST_PLL_A
Automatically reset signal RST_UNLOCKED_B and standby clock of the comprehensive CPU direct reduction of the second phase-locked loop reset signal generation unit signal RST_CPU, the second phase-locked loop losing lock lost alarm signal LOS_CLK_B and carries out after exclusive disjunction, forms the second phase-locked loop reset signal RST_PLL_B.
On the basis of technique scheme, it is consistent with phase locked-loop unit effective reset signal level with standby clock loss alarm signal LOS_CLK_B that described active clock is lost alarm signal LOS_CLK_A.
On the basis of technique scheme, active clock SCLKA and standby clock SCLKB send into respectively first, second loss of clock detecting unit,
Whether first, second loss of clock detecting unit utilizes veneer cpu clock CLK_CPU detection to lose from active clock SCLKA and the standby clock SCLKB of backboard,
If active clock dropout, the first loss of clock detecting unit output active clock is lost alarm signal LOS_CLK_A, and is transferred to the first phase-locked loop reset signal generation unit,
If standby clock signal is lost, second clock loss detection unit output standby clock is lost alarm signal LOS_CLK_B, and is transferred to the second phase-locked loop reset signal generation unit.
On the basis of technique scheme, the first phase locked-loop unit in the time of losing lock, to the first the first phase-locked loop lock-out state index signal LOCKED_A that automatically resets signal generation unit output high level,
The second phase locked-loop unit in the time of losing lock, to the second the second phase-locked loop lock-out state index signal LOCKED_B that automatically resets signal generation unit output high level,
First automatically resets after signal generation unit comprehensive veneer cpu clock CLK_CPU and the first phase-locked loop lock-out state index signal LOCKED_A, forms the first phase-locked loop losing lock signal RST_UNLOCKED_A that automatically resets,
Second automatically resets after signal generation unit comprehensive veneer cpu clock CLK_CPU and the second phase-locked loop lock-out state index signal LOCKED_B, forms the second phase-locked loop losing lock signal RST_UNLOCKED_B that automatically resets.
On the basis of technique scheme, first, second loss of clock detecting unit structure is identical, and each loss of clock detecting unit includes:
Inverter, it exports reverse clock signal SCLK_N after receiving active clock SCLKA or standby clock SCLKB,
The first counter and the second counter, the first counter produces count signal COUNTER1, and the second counter produces count signal COUNTER2,
Described the first counter and the second counter all make triggering clock with veneer cpu clock CLK_CPU,
Described the first counter adopts reverse clock signal SCLK_N as reset signal,
Described the second counter adopts active clock SCLKA or standby clock SCLKB as reset signal,
Count signal COUNTER1 and count signal COUNTER2 send into respectively comparator, when any one default value reaching of value of two counters of comparator judgement, illustrate that active clock SCLKA or standby clock SCLKB do not overturn for a long time, produce accordingly active clock and lose alarm signal LOS_CLK_A or standby clock loss alarm signal LOS_CLK_B.
On the basis of technique scheme, complex signal generation unit produces the automatic complex signal RST_UNLOCKED of phase-locked loop losing lock automatically, and it comprises:
Frequency divider, receives veneer cpu clock CLK_CPU and veneer cpu clock CLK_CPU frequency division is produced to a low-frequency clock CLK_DIV,
Counter COUNTER, it does enable signal with clock CLK_DIV, uses veneer cpu clock CLK_CPU as reset signal,
Count signal, clock CLK_DIV and phase-locked loop lock-out state index signal LOCKED that veneer cpu clock CLK_CPU, counter COUNTER are produced send into reset signal o controller,
In the time that reset signal o controller detects that the count signal of counter COUNTER generation equals the numerical value of setting, export the effective phase-locked loop losing lock signal RST_UNLOCKED that automatically resets, otherwise export the invalid phase-locked loop losing lock signal RST_UNLOCKED that automatically resets
Wherein, the automatically reset length of significant level duration of signal RST_UNLOCKED of phase-locked loop losing lock, can export the effective phase-locked loop losing lock signal RST_UNLOCKED that automatically resets and realize by adjusting the frequency sum counter width of clock CLK_DIV and being arranged on when which value counter equal.
The clock selection circuit that is applicable to communication equipment back plate overhead processing of the present invention, solve in the time need to adjusting the phase place of backboard expense clock, the problem of easy losing lock when the phase-locked loop circuit using switches in master/backup clock source, the function of automatic Rapid reset while possessing phase-locked loop losing lock, reduce the resource requirement to board software, and can at utmost reduce phase-locked loop losing lock number of times, improve the stability of system.
Brief description of the drawings
The present invention has following accompanying drawing:
Fig. 1 is circuit structure block diagram of the present invention,
Fig. 2 is the circuit structure block diagram of loss of clock detecting unit of the present invention,
Fig. 3 is the circuit structure block diagram of automatic complex signal generation unit of the present invention.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in further detail.
The clock selection circuit that is applicable to communication equipment back plate overhead processing of the present invention, as shown in Figure 1, this clock selection circuit comprises:
First, second loss of clock detecting unit, first, second signal generation unit that automatically resets, first, second phase-locked loop reset signal generation unit, first, second phase-locked loop (PLL) unit and a clock selecting unit (MUX),
Clock selecting cell call on-site programmable gate array FPGA manufacturer provides logic primitive (Slice/CLB Primitives),
Phase locked-loop unit is directly called the IP kernel that on-site programmable gate array FPGA manufacturer provides,
Loss of clock detecting unit, automatically reset signal generation unit and phase-locked loop reset signal generation unit adopt hardware description language (such as Verilog HDL) to design, then utilize FPGA design tool to carry out comprehensively, generation can download to the BIT file of fpga chip
Active clock plate produces active clock SCLKA, and standby clock plate produces standby clock SCLKB,
Two phase locked-loop unit are respectively used to adjust the clock phase of active clock SCLKA and standby clock SCLKB, and export the active clock SCLKA_PLL_A adjusting after phase place and adjust the standby clock SCLKA_PLL_B after phase place,
The clock (adjust the active clock SCLKA_PLL_A after phase place and adjust the standby clock SCLKA_PLL_B after phase place) of two phase locked-loop unit outputs of clock selecting unit reception is also exported the clock sclk after selecting after selecting, and the selection signal SEL_AB of clock selecting unit is determined by the operating state of active clock plate and standby clock plate.
On the basis of technique scheme, first, second phase-locked loop reset signal generation unit produces respectively the first phase-locked loop reset signal RST_PLL_A and the second phase-locked loop reset signal RST_PLL_B,
The first phase locked-loop unit is carried out reset operation according to the first phase-locked loop reset signal RST_PLL_A,
The second phase locked-loop unit is carried out reset operation according to the second phase-locked loop reset signal RST_PLL_B.
On the basis of technique scheme, automatically reset signal RST_UNLOCKED_A and active clock of the comprehensive CPU direct reduction of the first phase-locked loop reset signal generation unit signal RST_CPU, the first phase-locked loop losing lock lost alarm signal LOS_CLK_A and carries out after exclusive disjunction, form the first phase-locked loop reset signal RST_PLL_A
Automatically reset signal RST_UNLOCKED_B and standby clock of the comprehensive CPU direct reduction of the second phase-locked loop reset signal generation unit signal RST_CPU, the second phase-locked loop losing lock lost alarm signal LOS_CLK_B and carries out after exclusive disjunction, forms the second phase-locked loop reset signal RST_PLL_B.
Described CPU direct reduction signal RST_CPU is used for realizing CPU direct reduction, and for example after Board Power up, FPGA Global reset can use this signal to realize.
On the basis of technique scheme, it is consistent with phase locked-loop unit effective reset signal level with standby clock loss alarm signal LOS_CLK_B that described active clock is lost alarm signal LOS_CLK_A.That is: alarm signal is that high level or low level are determined by the significant level of the reset signal of phase locked-loop unit.
On the basis of technique scheme, active clock SCLKA and standby clock SCLKB send into respectively first, second loss of clock detecting unit,
Whether first, second loss of clock detecting unit utilizes veneer cpu clock CLK_CPU detection to lose from active clock SCLKA and the standby clock SCLKB of backboard,
If active clock dropout, the first loss of clock detecting unit output active clock is lost alarm signal LOS_CLK_A, and is transferred to the first phase-locked loop reset signal generation unit,
If standby clock signal is lost, second clock loss detection unit output standby clock is lost alarm signal LOS_CLK_B, and is transferred to the second phase-locked loop reset signal generation unit.
Due under normal circumstances, whether it is high that the frequency ratio active clock SCLKA of veneer cpu clock CLK_CPU or the frequency of standby clock SCLKB are wanted, lose from the SCLK (SCLK_A/SCLK_B) of backboard therefore system clock loss detection unit can utilize CLK_CPU to detect.When the frequency ratio active clock SCLKA of CLK_CPU or the frequency of standby clock SCLKB are when low, can adopt the clock that on veneer, other reliable and stable frequencies than active clock SCLKA or standby clock SCLKB are high to replace CLK_CPU.
On the basis of technique scheme, the first phase locked-loop unit in the time of losing lock, to the first the first phase-locked loop lock-out state index signal LOCKED_A that automatically resets signal generation unit output high level,
The second phase locked-loop unit in the time of losing lock, to the second the second phase-locked loop lock-out state index signal LOCKED_B that automatically resets signal generation unit output high level,
First automatically resets after signal generation unit comprehensive veneer cpu clock CLK_CPU and the first phase-locked loop lock-out state index signal LOCKED_A, forms the first phase-locked loop losing lock signal RST_UNLOCKED_A that automatically resets,
Second automatically resets after signal generation unit comprehensive veneer cpu clock CLK_CPU and the second phase-locked loop lock-out state index signal LOCKED_B, forms the second phase-locked loop losing lock signal RST_UNLOCKED_B that automatically resets.
On the basis of technique scheme, first, second loss of clock detecting unit structure is identical, and as shown in Figure 2, each loss of clock detecting unit includes:
Inverter, it exports reverse clock signal SCLK_N after receiving active clock SCLKA or standby clock SCLKB,
The first counter and the second counter, the first counter produces count signal COUNTER1, and the second counter produces count signal COUNTER2,
Described the first counter and the second counter all make triggering clock with veneer cpu clock CLK_CPU,
Described the first counter adopts reverse clock signal SCLK_N as reset signal,
Described the second counter adopts active clock SCLKA or standby clock SCLKB as reset signal,
Count signal COUNTER1 and count signal COUNTER2 send into respectively comparator, when any one default value reaching of value of two counters of comparator judgement, illustrate that active clock SCLKA or standby clock SCLKB do not overturn for a long time, produce accordingly active clock and lose alarm signal LOS_CLK_A or standby clock loss alarm signal LOS_CLK_B.
Because if when active clock SCLKA or standby clock SCLKB are normal, COUNTER1 and COUNTER2 can often reset, and the not accounting of value of counter is to default value.The preset value of COUNTER1/ COUNTER2 can be for detecting 2 times of above integers of clock (CLK_CPU) frequency and detected clock (SCLKA/SCLKB) clock frequency ratio.
The frequency of supposing CLK_CPU is 60MHz, the frequency of SCLKA/SCLKB is 20MHz, the preset value of COUNTER1/ COUNTER2 is 6, and COUNTER1/ COUNTER2 count down at 2 o'clock under normal circumstances, can zero clearing when arriving at the sampling clock of next CLK_CPU.
On the basis of technique scheme, as shown in Figure 3, complex signal generation unit produces the automatic complex signal RST_UNLOCKED of phase-locked loop losing lock automatically, and it comprises:
Frequency divider, reception veneer cpu clock CLK_CPU for example, clock CLK_DIV by a veneer cpu clock CLK_CPU frequency division low frequency of generation (1Khz),
Counter COUNTER, it does enable signal with clock CLK_DIV, uses veneer cpu clock CLK_CPU as reset signal,
Count signal, clock CLK_DIV and phase-locked loop lock-out state index signal LOCKED(that veneer cpu clock CLK_CPU, counter COUNTER are produced correspond to Fig. 1 and are the first phase-locked loop lock-out state index signal LOCKED_A or the second phase-locked loop lock-out state index signal LOCKED_B) send into reset signal o controller
In the time that reset signal o controller detects that the count signal of counter COUNTER generation equals the numerical value of setting, export the effective phase-locked loop losing lock signal RST_UNLOCKED that automatically resets, otherwise export the invalid phase-locked loop losing lock signal RST_UNLOCKED that automatically resets
Wherein, the automatically reset length of significant level duration of signal RST_UNLOCKED of phase-locked loop losing lock, can export the effective phase-locked loop losing lock signal RST_UNLOCKED that automatically resets and realize by adjusting the frequency sum counter width of clock CLK_DIV and being arranged on when which value counter equal.
The clock selection circuit that is applicable to communication equipment back plate overhead processing of the present invention, has the following advantages:
(1) parameter of phase locked-loop unit can be set by FPGA design software in the equipment debugging stage, find most suitable output clock phase, to meet core bus specification; Adopt phase locked-loop unit can adjust flexibly the phase place of output clock, the limitation of can only phase modulation 180 while avoiding adopting inverter spending, also can avoid adding delay cell formula on clock path time, every comprehensive larger problem of phase place possible deviation.
(2) adopt two phase-locked loop Unit Design, clock is selected after going out phase locked-loop unit again, can farthest reduce phase locked-loop unit losing lock number of times, avoids unnecessary reset operation.
(3) while adopting the phase locked-loop unit losing lock in technique scheme, automatically reset, reduced the resource requirement to board software, and reset speed is fast.Because the common scheme that phase locked-loop unit resets is the lock-out state that veneer CPU detects phase locked-loop unit, when losing lock, reset, need in single-deck software, add a phase locked-loop unit losing lock reset task.
The content not being described in detail in this specification belongs to the known prior art of professional and technical personnel in the field.
Claims (3)
1. one kind is applicable to the clock selection circuit of communication equipment back plate overhead processing, it is characterized in that: this circuit is to utilize the on-site programmable device FPGA on veneer to realize, the clock selection circuit of the backboard overhead processing of the two phase-locked loop structure of automatic Rapid reset while possessing phase-locked loop losing lock; This clock selection circuit comprises:
First, second loss of clock detecting unit, first, second signal generation unit that automatically resets, first, second phase-locked loop reset signal generation unit, first, second phase-locked loop pll unit and a clock selecting unit MUX,
Clock selecting cell call on-site programmable gate array FPGA manufacturer provides logic primitive,
Phase locked-loop unit is directly called the IP kernel that on-site programmable gate array FPGA manufacturer provides,
Loss of clock detecting unit, automatically reset signal generation unit and phase-locked loop reset signal generation unit adopt hardware description language to design, and then utilize FPGA design tool to carry out comprehensively, and generation can download to the BIT file of fpga chip,
Active clock plate produces active clock SCLKA, and standby clock plate produces standby clock SCLKB,
Two phase locked-loop unit are respectively used to adjust the clock phase of active clock SCLKA and standby clock SCLKB, and export the active clock SCLKA_PLL_A adjusting after phase place and adjust the standby clock SCLKA_PLL_B after phase place,
Clock selecting unit receives the clock of two phase locked-loop unit outputs and after selecting, exports the clock sclk after selecting, and the selection signal SEL_AB of clock selecting unit is determined by the operating state of active clock plate and standby clock plate;
First, second phase-locked loop reset signal generation unit produces respectively the first phase-locked loop reset signal RST_PLL_A and the second phase-locked loop reset signal RST_PLL_B,
The first phase locked-loop unit is carried out reset operation according to the first phase-locked loop reset signal RST_PLL_A,
The second phase locked-loop unit is carried out reset operation according to the second phase-locked loop reset signal RST_PLL_B;
Automatically reset signal RST_UNLOCKED_A and active clock of the comprehensive CPU direct reduction of the first phase-locked loop reset signal generation unit signal RST_CPU, the first phase-locked loop losing lock lost alarm signal LOS_CLK_A and carries out after exclusive disjunction, form the first phase-locked loop reset signal RST_PLL_A
Automatically reset signal RST_UNLOCKED_B and standby clock of the comprehensive CPU direct reduction of the second phase-locked loop reset signal generation unit signal RST_CPU, the second phase-locked loop losing lock lost alarm signal LOS_CLK_B and carries out after exclusive disjunction, forms the second phase-locked loop reset signal RST_PLL_B;
It is consistent with phase locked-loop unit effective reset signal level with standby clock loss alarm signal LOS_CLK_B that described active clock is lost alarm signal LOS_CLK_A;
Active clock SCLKA and standby clock SCLKB send into respectively first, second loss of clock detecting unit,
Whether first, second loss of clock detecting unit utilizes veneer cpu clock CLK_CPU detection to lose from active clock SCLKA and the standby clock SCLKB of backboard,
If active clock dropout, the first loss of clock detecting unit output active clock is lost alarm signal LOS_CLK_A, and is transferred to the first phase-locked loop reset signal generation unit,
If standby clock signal is lost, second clock loss detection unit output standby clock is lost alarm signal LOS_CLK_B, and is transferred to the second phase-locked loop reset signal generation unit;
The first phase locked-loop unit in the time of losing lock, to the first the first phase-locked loop lock-out state index signal LOCKED_A that automatically resets signal generation unit output high level,
The second phase locked-loop unit in the time of losing lock, to the second the second phase-locked loop lock-out state index signal LOCKED_B that automatically resets signal generation unit output high level,
First automatically resets after signal generation unit comprehensive veneer cpu clock CLK_CPU and the first phase-locked loop lock-out state index signal LOCKED_A, forms the first phase-locked loop losing lock signal RST_UNLOCKED_A that automatically resets,
Second automatically resets after signal generation unit comprehensive veneer cpu clock CLK_CPU and the second phase-locked loop lock-out state index signal LOCKED_B, forms the second phase-locked loop losing lock signal RST_UNLOCKED_B that automatically resets.
2. the clock selection circuit that is applicable to communication equipment back plate overhead processing as claimed in claim 1, is characterized in that: first, second loss of clock detecting unit structure is identical, and each loss of clock detecting unit includes:
Inverter, it exports reverse clock signal SCLK_N after receiving active clock SCLKA or standby clock SCLKB,
The first counter and the second counter, the first counter produces count signal COUNTER1, and the second counter produces count signal COUNTER2,
Described the first counter and the second counter all make triggering clock with veneer cpu clock CLK_CPU,
Described the first counter adopts reverse clock signal SCLK_N as reset signal,
Described the second counter adopts active clock SCLKA or standby clock SCLKB as reset signal,
Count signal COUNTER1 and count signal COUNTER2 send into respectively comparator, when any one default value reaching of value of two counters of comparator judgement, illustrate that active clock SCLKA or standby clock SCLKB do not overturn for a long time, produce accordingly active clock and lose alarm signal LOS_CLK_A or standby clock loss alarm signal LOS_CLK_B.
3. the clock selection circuit that is applicable to communication equipment back plate overhead processing as claimed in claim 1, it is characterized in that: the signal generation unit that automatically resets produces the phase-locked loop losing lock signal RST_UNLOCKED that automatically resets, described in the signal generation unit that automatically resets comprise:
Frequency divider, receives veneer cpu clock CLK_CPU and veneer cpu clock CLK_CPU frequency division is produced to a low-frequency clock CLK_DIV,
Counter COUNTER, it does enable signal with clock CLK_DIV, uses veneer cpu clock CLK_CPU as reset signal,
Count signal, clock CLK_DIV and phase-locked loop lock-out state index signal LOCKED that veneer cpu clock CLK_CPU, counter COUNTER are produced send into reset signal o controller,
In the time that reset signal o controller detects that the count signal of counter COUNTER generation equals the numerical value of setting, export the effective phase-locked loop losing lock signal RST_UNLOCKED that automatically resets, otherwise export the invalid phase-locked loop losing lock signal RST_UNLOCKED that automatically resets
Wherein, the automatically reset length of significant level duration of signal RST_UNLOCKED of phase-locked loop losing lock, can export the effective phase-locked loop losing lock signal RST_UNLOCKED that automatically resets and realize by adjusting the frequency sum counter width of clock CLK_DIV and being arranged on when which value counter equal.
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| CN201210239046.XA CN102751982B (en) | 2012-07-11 | 2012-07-11 | Clock selection circuit suitable for backboard spending treatment of communication equipment |
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| CN103678014A (en) * | 2013-12-18 | 2014-03-26 | 浪潮(北京)电子信息产业有限公司 | Method for effectively detecting and analyzing SGPIO signals |
| CN105681068A (en) * | 2014-11-19 | 2016-06-15 | 中兴通讯股份有限公司 | Automatic single board switching method and system |
| CN105763250B (en) * | 2016-02-23 | 2018-01-02 | 烽火通信科技股份有限公司 | A kind of method and system for preventing wrong overhead byte transmission |
| CN109687866A (en) * | 2018-12-24 | 2019-04-26 | 中国电子科技集团公司第五十八研究所 | A kind of compensation device ensureing PLL output clock |
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| US4305045A (en) * | 1979-11-14 | 1981-12-08 | Bell Telephone Laboratories, Incorporated | Phase locked loop clock synchronizing circuit with programmable controller |
| US5822387A (en) * | 1996-03-25 | 1998-10-13 | Cypress Semiconductor Corporation | Apparatus for fast phase-locked loop (PLL) frequency slewing during power on |
| CN101453215A (en) * | 2007-11-30 | 2009-06-10 | 瑞昱半导体股份有限公司 | Frequency synthesizer having multiple frequency locking circuits |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4305045A (en) * | 1979-11-14 | 1981-12-08 | Bell Telephone Laboratories, Incorporated | Phase locked loop clock synchronizing circuit with programmable controller |
| US5822387A (en) * | 1996-03-25 | 1998-10-13 | Cypress Semiconductor Corporation | Apparatus for fast phase-locked loop (PLL) frequency slewing during power on |
| CN101453215A (en) * | 2007-11-30 | 2009-06-10 | 瑞昱半导体股份有限公司 | Frequency synthesizer having multiple frequency locking circuits |
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