CN102751982A - Clock selection circuit suitable for backboard spending treatment of communication equipment - Google Patents
Clock selection circuit suitable for backboard spending treatment of communication equipment Download PDFInfo
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Abstract
The invention relates to a clock selection circuit suitable for backboard spending treatment of communication equipment. The clock selection circuit utilizes an FPGA (field programmable gata array) of a field programmable device on a single plate to be realized, and is provided with a double phase-locked loop structure which can automatically and rapidly reset; and the clock selection circuit comprises first and second clock losing detection units, first and second automatic reset signal generating units, first and second phase-locked loop reset signal generating units, first and second phase locking loop (PLL) units and a clock selection unit MUX (multiplexer). The clock selection circuit suitable for the backboard spending treatment of the communication equipment, provided by the invention, solves the problems that a phase position of a backboard spending clock needs to be adjusted, a utilized phase locked loop circuit is easy for loose of lock when a main preparing clock source is switched; and the clock selection circuit has an automatic rapid resetting function when the phase locking loop is in the loose of lock, the resource requirement on single plate software is reduced, losing lock times of the phase locking loop can be reduced to the greatest extent, and the stability of a system is improved.
Description
Technical field
The present invention relates to the selection circuit of backboard expense clock, is a kind of clock selection circuit that is applicable to communication equipment backboard overhead processing specifically.That is: be applicable to the selection circuit of communication equipment dorsulum expense clock; Especially refer to utilize field programmable device (FPGA) on the veneer to realize, the clock selection circuit of the backboard overhead processing of the two phase-locked loop structure that resets fast automatically when possessing the phase-locked loop losing lock.
Background technology
In order to ensure the performance of communication equipment; For the unit of some particular importance, such as the common Hot Spare that adopts 1+1 such as cross board, clock board, master control borad, promptly when the master is broken down with veneer; Can switch to standby board work automatically, not interrupt and normal operation with the assurance communication equipment.Carry out the board-to-board information transmission through the backboard overhead bus between the cross board of communication equipment, master control borad and the wiring board; The expense clock of these veneers derives from active/standby clock board; During the equipment operate as normal; Need switch with state according to the active and standby of clock board, select active clock to send and the reception expense.
In order to develop the communication equipment of stable performance; Generally all formulated backboard overhead bus standard in the equipment development stage; The overhead signal output timing of each veneer on the equipment (including but not limited to cross board, clock board, master control borad etc.) is all followed this standard; So also help the follow-up maintenance work of each veneer, avoid not satisfying the backboard standard and the change that causes veneer wherein the problem that another relevant with it piece veneer also need be changed.
Follow backboard overhead bus standard and correct sampling input overhead signal for the sequential that guarantees to export overhead signal, need adjust the phase place of expense clock sometimes.Special phase place adjustment such as transferring 180 degree to realize that phase place postpones lesser degree backward through inverter, can realize through on clock path, adding delay cell.Can only adjust the phase place of 180 degree through inverter, can play the purpose of phase modulation through adding delay cell, but be difficult for accurately control, so the application scenario of these two kinds of methods is limited.Adopt phase-locked loop to adjust a kind of mode that phase place is a most convenient, but when switching in the master/backup clock source, phase-locked loop is easy to losing lock, the ability that must reset operate as normal is resetted by board software usually.
Summary of the invention
To the defective that exists in the prior art; The object of the present invention is to provide a kind of clock selection circuit that is applicable to communication equipment backboard overhead processing, solved when needing the phase place of adjustment backboard expense clock the problem of easy losing lock when the phase-locked loop circuit of use switches in the master/backup clock source; Automatically the function that resets fast when possessing the phase-locked loop losing lock; Reduction is to the resource requirement of board software, and can at utmost reduce phase-locked loop losing lock number of times, improves the stability of system.
For reaching above purpose, the technical scheme that the present invention takes is:
A kind of clock selection circuit that is applicable to communication equipment backboard overhead processing; It is characterized in that: this circuit is to utilize the on-site programmable device FPGA on the veneer to realize the clock selection circuit of the backboard overhead processing of the two phase-locked loop structure that resets fast automatically when possessing the phase-locked loop losing lock.
On the basis of technique scheme, this clock selection circuit comprises:
First, second loss of clock detecting unit, first, second signal generation unit that automatically resets, first, second phase-locked loop reset signal generation unit, first, second phase-locked loop pll unit and a clock selecting unit MUX,
Clock selecting cell call on-site programmable gate array FPGA manufacturer provides logic primitive,
Phase locked-loop unit is directly called the IP kernel that on-site programmable gate array FPGA manufacturer provides,
Loss of clock detecting unit, automatically reset signal generation unit and phase-locked loop reset signal generation unit adopt hardware description language to design, and utilize the FPGA design tool to carry out comprehensively then, and generation can download to the BIT file of fpga chip,
The active clock plate produces active clock SCLKA, and the standby clock plate produces standby clock SCLKB,
Two phase locked-loop unit are respectively applied for the clock phase of adjustment active clock SCLKA and standby clock SCLKB, and active clock SCLKA_PLL_A after the output adjustment phase place and the standby clock SCLKA_PLL_B after the adjustment phase place,
The clock selecting unit receives the clock of two phase locked-loop unit outputs and at the clock sclk of selecting after back output is selected, the selection signal SEL_AB of clock selecting unit is confirmed by the operating state of active clock plate and standby clock plate.
On the basis of technique scheme, first, second phase-locked loop reset signal generation unit produces the first phase-locked loop reset signal RST_PLL_A and the second phase-locked loop reset signal RST_PLL_B respectively,
First phase locked-loop unit is carried out reset operation according to the first phase-locked loop reset signal RST_PLL_A,
Second phase locked-loop unit is carried out reset operation according to the second phase-locked loop reset signal RST_PLL_B.
On the basis of technique scheme; The direct reset signal RST_CPU of the first comprehensive CPU of phase-locked loop reset signal generation unit, the first phase-locked loop losing lock automatically reset after signal RST_UNLOCKED_A and active clock lose alarm signal LOS_CLK_A and carry out exclusive disjunction; Form the first phase-locked loop reset signal RST_PLL_A
The direct reset signal RST_CPU of the second comprehensive CPU of phase-locked loop reset signal generation unit, the second phase-locked loop losing lock automatically reset after signal RST_UNLOCKED_B and standby clock lose alarm signal LOS_CLK_B and carry out exclusive disjunction, form the second phase-locked loop reset signal RST_PLL_B.
On the basis of technique scheme, said active clock is lost alarm signal LOS_CLK_A and standby clock, and to lose alarm signal LOS_CLK_B consistent with phase locked-loop unit effective reset signal level.
On the basis of technique scheme, active clock SCLKA and standby clock SCLKB send into first, second loss of clock detecting unit respectively,
Whether active clock SCLKA and standby clock SCLKB that first, second loss of clock detecting unit utilizes veneer cpu clock CLK_CPU to detect from backboard lose,
If active clock dropout then first loss of clock detecting unit output active clock is lost alarm signal LOS_CLK_A, and is transferred to the first phase-locked loop reset signal generation unit,
Second clock loss detection unit output standby clock is lost alarm signal LOS_CLK_B if standby clock signal is lost, and is transferred to the second phase-locked loop reset signal generation unit.
On the basis of technique scheme, first phase locked-loop unit when losing lock, to first automatically reset signal generation unit output high level the first pll lock condition indicative signal LOCKED_A,
Second phase locked-loop unit when losing lock, to second automatically reset signal generation unit output high level the second pll lock condition indicative signal LOCKED_B,
First automatically resets behind the signal generation unit comprehensive veneer cpu clock CLK_CPU and the first pll lock condition indicative signal LOCKED_A, forms the first phase-locked loop losing lock signal RST_UNLOCKED_A that automatically resets,
Second automatically resets behind the signal generation unit comprehensive veneer cpu clock CLK_CPU and the second pll lock condition indicative signal LOCKED_B, forms the second phase-locked loop losing lock signal RST_UNLOCKED_B that automatically resets.
On the basis of technique scheme, first, second loss of clock detecting unit structure is identical, and each loss of clock detecting unit includes:
Inverter, it exports reverse clock signal SCLK_N after receiving active clock SCLKA or standby clock SCLKB,
First counter and second counter, first counter produces count signal COUNTER1, and second counter produces count signal COUNTER2,
Said first counter and second counter are all made the triggering clock with veneer cpu clock CLK_CPU,
Said first counter adopts reverse clock signal SCLK_N as reset signal,
Said second counter adopts active clock SCLKA or standby clock SCLKB as reset signal,
Count signal COUNTER1 and count signal COUNTER2 send into comparator respectively; Judge any preset value that reaches of value of two counters when comparator; Active clock SCLKA or standby clock SCLKB not upset for a long time then is described, is produced accordingly then that active clock is lost alarm signal LOS_CLK_A or standby clock is lost alarm signal LOS_CLK_B.
On the basis of technique scheme, the complex signal generation unit produces the automatic complex signal RST_UNLOCKED of phase-locked loop losing lock automatically, and it comprises:
Frequency divider receives veneer cpu clock CLK_CPU and veneer cpu clock CLK_CPU frequency division is produced a low-frequency clock CLK_DIV,
Counter COUNTER, it does enable signal with clock CLK_DIV, with veneer cpu clock CLK_CPU as reset signal,
Count signal, clock CLK_DIV and pll lock condition indicative signal LOCKED that veneer cpu clock CLK_CPU, counter COUNTER are produced send into the reset signal o controller,
When the reset signal o controller detects the numerical value that count signal that counter COUNTER produces equals to set; Export the effective phase-locked loop losing lock signal RST_UNLOCKED that automatically resets; Otherwise export the invalid phase-locked loop losing lock signal RST_UNLOCKED that automatically resets
Wherein, The automatically reset length of significant level duration of signal RST_UNLOCKED of phase-locked loop losing lock, the frequency sum counter width through adjustment clock CLK_DIV and being arranged on can be exported the effective phase-locked loop losing lock signal RST_UNLOCKED that automatically resets and realize when which value counter equal.
The clock selection circuit that is applicable to communication equipment backboard overhead processing of the present invention; Solved when needing the phase place of adjustment backboard expense clock; The problem of easy losing lock when the phase-locked loop circuit that uses switches in the master/backup clock source, the function that resets fast automatically when possessing the phase-locked loop losing lock reduces the resource requirement to board software; And can at utmost reduce phase-locked loop losing lock number of times, improve the stability of system.
Description of drawings
The present invention has following accompanying drawing:
Fig. 1 is a circuit structure block diagram of the present invention,
Fig. 2 is the circuit structure block diagram of loss of clock detecting unit of the present invention,
Fig. 3 is the circuit structure block diagram of automatic complex signal generation unit of the present invention.
Embodiment
Below in conjunction with accompanying drawing the present invention is done further explain.
The clock selection circuit that is applicable to communication equipment backboard overhead processing of the present invention, as shown in Figure 1, this clock selection circuit comprises:
First, second loss of clock detecting unit, first, second signal generation unit that automatically resets, first, second phase-locked loop reset signal generation unit, first, second phase-locked loop (PLL) unit and a clock selecting unit (MUX),
Clock selecting cell call on-site programmable gate array FPGA manufacturer provides logic primitive (Slice/CLB Primitives),
Phase locked-loop unit is directly called the IP kernel that on-site programmable gate array FPGA manufacturer provides,
Loss of clock detecting unit, automatically reset signal generation unit and phase-locked loop reset signal generation unit adopt hardware description language (such as Verilog HDL) to design; Utilize the FPGA design tool to carry out comprehensively then; Generation can download to the BIT file of fpga chip
The active clock plate produces active clock SCLKA, and the standby clock plate produces standby clock SCLKB,
Two phase locked-loop unit are respectively applied for the clock phase of adjustment active clock SCLKA and standby clock SCLKB, and active clock SCLKA_PLL_A after the output adjustment phase place and the standby clock SCLKA_PLL_B after the adjustment phase place,
The clock selecting unit receives the clock (the standby clock SCLKA_PLL_B after active clock SCLKA_PLL_A after the adjustment phase place and the adjustment phase place) of two phase locked-loop unit outputs and at the clock sclk of selecting after back output is selected, the selection signal SEL_AB of clock selecting unit is definite by the operating state of active clock plate and standby clock plate.
On the basis of technique scheme, first, second phase-locked loop reset signal generation unit produces the first phase-locked loop reset signal RST_PLL_A and the second phase-locked loop reset signal RST_PLL_B respectively,
First phase locked-loop unit is carried out reset operation according to the first phase-locked loop reset signal RST_PLL_A,
Second phase locked-loop unit is carried out reset operation according to the second phase-locked loop reset signal RST_PLL_B.
On the basis of technique scheme; The direct reset signal RST_CPU of the first comprehensive CPU of phase-locked loop reset signal generation unit, the first phase-locked loop losing lock automatically reset after signal RST_UNLOCKED_A and active clock lose alarm signal LOS_CLK_A and carry out exclusive disjunction; Form the first phase-locked loop reset signal RST_PLL_A
The direct reset signal RST_CPU of the second comprehensive CPU of phase-locked loop reset signal generation unit, the second phase-locked loop losing lock automatically reset after signal RST_UNLOCKED_B and standby clock lose alarm signal LOS_CLK_B and carry out exclusive disjunction, form the second phase-locked loop reset signal RST_PLL_B.
The direct reset signal RST_CPU of said CPU is used to realize that CPU directly resets, and for example the FPGA Global reset can use this signal to realize behind the Board Power up.
On the basis of technique scheme, said active clock is lost alarm signal LOS_CLK_A and standby clock, and to lose alarm signal LOS_CLK_B consistent with phase locked-loop unit effective reset signal level.That is: alarm signal is the significant level decision by the reset signal of phase locked-loop unit of high level or low level.
On the basis of technique scheme, active clock SCLKA and standby clock SCLKB send into first, second loss of clock detecting unit respectively,
Whether active clock SCLKA and standby clock SCLKB that first, second loss of clock detecting unit utilizes veneer cpu clock CLK_CPU to detect from backboard lose,
If active clock dropout then first loss of clock detecting unit output active clock is lost alarm signal LOS_CLK_A, and is transferred to the first phase-locked loop reset signal generation unit,
Second clock loss detection unit output standby clock is lost alarm signal LOS_CLK_B if standby clock signal is lost, and is transferred to the second phase-locked loop reset signal generation unit.
Because generally; It is high that the frequency ratio active clock SCLKA of veneer cpu clock CLK_CPU or the frequency of standby clock SCLKB are wanted, so whether the SCLK (SCLK_A/SCLK_B) that system clock loss detection unit CLK_CPU capable of using detects from backboard loses.When the frequency of the frequency ratio active clock SCLKA of CLK_CPU or standby clock SCLKB is low, can adopt the high clock replaced C LK_CPU of other reliable and stable frequencies on the veneer than active clock SCLKA or standby clock SCLKB.
On the basis of technique scheme, first phase locked-loop unit when losing lock, to first automatically reset signal generation unit output high level the first pll lock condition indicative signal LOCKED_A,
Second phase locked-loop unit when losing lock, to second automatically reset signal generation unit output high level the second pll lock condition indicative signal LOCKED_B,
First automatically resets behind the signal generation unit comprehensive veneer cpu clock CLK_CPU and the first pll lock condition indicative signal LOCKED_A, forms the first phase-locked loop losing lock signal RST_UNLOCKED_A that automatically resets,
Second automatically resets behind the signal generation unit comprehensive veneer cpu clock CLK_CPU and the second pll lock condition indicative signal LOCKED_B, forms the second phase-locked loop losing lock signal RST_UNLOCKED_B that automatically resets.
On the basis of technique scheme, first, second loss of clock detecting unit structure is identical, as shown in Figure 2, and each loss of clock detecting unit includes:
Inverter, it exports reverse clock signal SCLK_N after receiving active clock SCLKA or standby clock SCLKB,
First counter and second counter, first counter produces count signal COUNTER1, and second counter produces count signal COUNTER2,
Said first counter and second counter are all made the triggering clock with veneer cpu clock CLK_CPU,
Said first counter adopts reverse clock signal SCLK_N as reset signal,
Said second counter adopts active clock SCLKA or standby clock SCLKB as reset signal,
Count signal COUNTER1 and count signal COUNTER2 send into comparator respectively; Judge any preset value that reaches of value of two counters when comparator; Active clock SCLKA or standby clock SCLKB not upset for a long time then is described, is produced accordingly then that active clock is lost alarm signal LOS_CLK_A or standby clock is lost alarm signal LOS_CLK_B.
If because active clock SCLKA or standby clock SCLKB are just often, COUNTER1 and COUNTER2 can often reset, the not accounting of value of counter is to preset value.The preset value of COUNTER1/ COUNTER2 can be for detecting the integer more than 2 times of clock (CLK_CPU) frequency and clock to be detected (SCLKA/SCLKB) clock frequency ratio.
The frequency of supposing CLK_CPU is 60MHz; The frequency of SCLKA/SCLKB is 20MHz; The preset value of COUNTER1/ COUNTER2 is 6, and then COUNTER1/ COUNTER2 count down at 2 o'clock under the normal condition, can zero clearing when arriving at the sampling clock of next CLK_CPU.
On the basis of technique scheme, as shown in Figure 3, the complex signal generation unit produces the automatic complex signal RST_UNLOCKED of phase-locked loop losing lock automatically, and it comprises:
Frequency divider receives veneer cpu clock CLK_CPU and veneer cpu clock CLK_CPU frequency division is produced the clock CLK_DIV of a low frequency (for example 1Khz),
Counter COUNTER, it does enable signal with clock CLK_DIV, with veneer cpu clock CLK_CPU as reset signal,
Count signal, clock CLK_DIV and pll lock condition indicative signal LOCKED (correspond to Fig. 1 and be the first pll lock condition indicative signal LOCKED_A or the second pll lock condition indicative signal LOCKED_B) that veneer cpu clock CLK_CPU, counter COUNTER are produced send into the reset signal o controller
When the reset signal o controller detects the numerical value that count signal that counter COUNTER produces equals to set; Export the effective phase-locked loop losing lock signal RST_UNLOCKED that automatically resets; Otherwise export the invalid phase-locked loop losing lock signal RST_UNLOCKED that automatically resets
Wherein, The automatically reset length of significant level duration of signal RST_UNLOCKED of phase-locked loop losing lock, the frequency sum counter width through adjustment clock CLK_DIV and being arranged on can be exported the effective phase-locked loop losing lock signal RST_UNLOCKED that automatically resets and realize when which value counter equal.
The clock selection circuit that is applicable to communication equipment backboard overhead processing of the present invention has the following advantages:
(1) parameter of phase locked-loop unit can be set in the equipment debugging stage through the FPGA design software, seek only output clock phase, to satisfy the core bus standard; Adopt phase locked-loop unit can adjust the phase place of output clock flexibly, limitation that can only phase modulation 180 degree when avoiding adopting inverter, in the time of also can avoiding on clock path, adding the delay cell formula, every comprehensive bigger problem of phase place possible deviation.
(2) adopt the two phase-locked loop cell design, clock is selected after going out phase locked-loop unit again, can farthest reduce phase locked-loop unit losing lock number of times, avoids unnecessary reset operation.
Automatically reset when (3) adopting phase locked-loop unit losing lock in the technique scheme, reduced resource requirement, and reset speed is fast board software.Detect the lock-out state of phase locked-loop unit because the common scheme that phase locked-loop unit resets is veneer CPU, reset during losing lock, need in single-deck software, add the phase locked-loop unit losing lock task that resets.
The content of not doing in this specification to describe in detail belongs to this area professional and technical personnel's known prior art.
Claims (9)
1. clock selection circuit that is applicable to communication equipment backboard overhead processing; It is characterized in that: this circuit is to utilize the on-site programmable device FPGA on the veneer to realize the clock selection circuit of the backboard overhead processing of the two phase-locked loop structure that resets fast automatically when possessing the phase-locked loop losing lock.
2. the clock selection circuit that is applicable to communication equipment backboard overhead processing as claimed in claim 1 is characterized in that, this clock selection circuit comprises:
First, second loss of clock detecting unit, first, second signal generation unit that automatically resets, first, second phase-locked loop reset signal generation unit, first, second phase-locked loop pll unit and a clock selecting unit MUX,
Clock selecting cell call on-site programmable gate array FPGA manufacturer provides logic primitive,
Phase locked-loop unit is directly called the IP kernel that on-site programmable gate array FPGA manufacturer provides,
Loss of clock detecting unit, automatically reset signal generation unit and phase-locked loop reset signal generation unit adopt hardware description language to design, and utilize the FPGA design tool to carry out comprehensively then, and generation can download to the BIT file of fpga chip,
The active clock plate produces active clock SCLKA, and the standby clock plate produces standby clock SCLKB,
Two phase locked-loop unit are respectively applied for the clock phase of adjustment active clock SCLKA and standby clock SCLKB, and active clock SCLKA_PLL_A after the output adjustment phase place and the standby clock SCLKA_PLL_B after the adjustment phase place,
The clock selecting unit receives the clock of two phase locked-loop unit outputs and at the clock sclk of selecting after back output is selected, the selection signal SEL_AB of clock selecting unit is confirmed by the operating state of active clock plate and standby clock plate.
3. the clock selection circuit that is applicable to communication equipment backboard overhead processing as claimed in claim 2; It is characterized in that: first, second phase-locked loop reset signal generation unit produces the first phase-locked loop reset signal RST_PLL_A and the second phase-locked loop reset signal RST_PLL_B respectively
First phase locked-loop unit is carried out reset operation according to the first phase-locked loop reset signal RST_PLL_A,
Second phase locked-loop unit is carried out reset operation according to the second phase-locked loop reset signal RST_PLL_B.
4. the clock selection circuit that is applicable to communication equipment backboard overhead processing as claimed in claim 3; It is characterized in that: the direct reset signal RST_CPU of the first comprehensive CPU of phase-locked loop reset signal generation unit, the first phase-locked loop losing lock automatically reset after signal RST_UNLOCKED_A and active clock lose alarm signal LOS_CLK_A and carry out exclusive disjunction; Form the first phase-locked loop reset signal RST_PLL_A
The direct reset signal RST_CPU of the second comprehensive CPU of phase-locked loop reset signal generation unit, the second phase-locked loop losing lock automatically reset after signal RST_UNLOCKED_B and standby clock lose alarm signal LOS_CLK_B and carry out exclusive disjunction, form the second phase-locked loop reset signal RST_PLL_B.
5. the clock selection circuit that is applicable to communication equipment backboard overhead processing as claimed in claim 4 is characterized in that: said active clock is lost alarm signal LOS_CLK_A and standby clock, and to lose alarm signal LOS_CLK_B consistent with phase locked-loop unit effective reset signal level.
6. the clock selection circuit that is applicable to communication equipment backboard overhead processing as claimed in claim 4 is characterized in that: active clock SCLKA and standby clock SCLKB send into first, second loss of clock detecting unit respectively,
Whether active clock SCLKA and standby clock SCLKB that first, second loss of clock detecting unit utilizes veneer cpu clock CLK_CPU to detect from backboard lose,
If active clock dropout then first loss of clock detecting unit output active clock is lost alarm signal LOS_CLK_A, and is transferred to the first phase-locked loop reset signal generation unit,
Second clock loss detection unit output standby clock is lost alarm signal LOS_CLK_B if standby clock signal is lost, and is transferred to the second phase-locked loop reset signal generation unit.
7. the clock selection circuit that is applicable to communication equipment backboard overhead processing as claimed in claim 6; It is characterized in that: first phase locked-loop unit is when losing lock; To first automatically reset signal generation unit output high level the first pll lock condition indicative signal LOCKED_A
Second phase locked-loop unit when losing lock, to second automatically reset signal generation unit output high level the second pll lock condition indicative signal LOCKED_B,
First automatically resets behind the signal generation unit comprehensive veneer cpu clock CLK_CPU and the first pll lock condition indicative signal LOCKED_A, forms the first phase-locked loop losing lock signal RST_UNLOCKED_A that automatically resets,
Second automatically resets behind the signal generation unit comprehensive veneer cpu clock CLK_CPU and the second pll lock condition indicative signal LOCKED_B, forms the second phase-locked loop losing lock signal RST_UNLOCKED_B that automatically resets.
8. the clock selection circuit that is applicable to communication equipment backboard overhead processing as claimed in claim 2 is characterized in that: first, second loss of clock detecting unit structure is identical, and each loss of clock detecting unit includes:
Inverter, it exports reverse clock signal SCLK_N after receiving active clock SCLKA or standby clock SCLKB,
First counter and second counter, first counter produces count signal COUNTER1, and second counter produces count signal COUNTER2,
Said first counter and second counter are all made the triggering clock with veneer cpu clock CLK_CPU,
Said first counter adopts reverse clock signal SCLK_N as reset signal,
Said second counter adopts active clock SCLKA or standby clock SCLKB as reset signal,
Count signal COUNTER1 and count signal COUNTER2 send into comparator respectively; Judge any preset value that reaches of value of two counters when comparator; Active clock SCLKA or standby clock SCLKB not upset for a long time then is described, is produced accordingly then that active clock is lost alarm signal LOS_CLK_A or standby clock is lost alarm signal LOS_CLK_B.
9. the clock selection circuit that is applicable to communication equipment backboard overhead processing as claimed in claim 2 is characterized in that: the complex signal generation unit produces the automatic complex signal RST_UNLOCKED of phase-locked loop losing lock automatically, and it comprises:
Frequency divider receives veneer cpu clock CLK_CPU and veneer cpu clock CLK_CPU frequency division is produced a low-frequency clock CLK_DIV,
Counter COUNTER, it does enable signal with clock CLK_DIV, with veneer cpu clock CLK_CPU as reset signal,
Count signal, clock CLK_DIV and pll lock condition indicative signal LOCKED that veneer cpu clock CLK_CPU, counter COUNTER are produced send into the reset signal o controller,
When the reset signal o controller detects the numerical value that count signal that counter COUNTER produces equals to set; Export the effective phase-locked loop losing lock signal RST_UNLOCKED that automatically resets; Otherwise export the invalid phase-locked loop losing lock signal RST_UNLOCKED that automatically resets
Wherein, The automatically reset length of significant level duration of signal RST_UNLOCKED of phase-locked loop losing lock, the frequency sum counter width through adjustment clock CLK_DIV and being arranged on can be exported the effective phase-locked loop losing lock signal RST_UNLOCKED that automatically resets and realize when which value counter equal.
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| CN105681068A (en) * | 2014-11-19 | 2016-06-15 | 中兴通讯股份有限公司 | Automatic single board switching method and system |
| CN105763250A (en) * | 2016-02-23 | 2016-07-13 | 烽火通信科技股份有限公司 | Method and system for preventing transfer of error overhead bytes |
| CN109687866A (en) * | 2018-12-24 | 2019-04-26 | 中国电子科技集团公司第五十八研究所 | A kind of compensation device ensureing PLL output clock |
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| CN105681068A (en) * | 2014-11-19 | 2016-06-15 | 中兴通讯股份有限公司 | Automatic single board switching method and system |
| CN105763250A (en) * | 2016-02-23 | 2016-07-13 | 烽火通信科技股份有限公司 | Method and system for preventing transfer of error overhead bytes |
| CN105763250B (en) * | 2016-02-23 | 2018-01-02 | 烽火通信科技股份有限公司 | A kind of method and system for preventing wrong overhead byte transmission |
| CN109687866A (en) * | 2018-12-24 | 2019-04-26 | 中国电子科技集团公司第五十八研究所 | A kind of compensation device ensureing PLL output clock |
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|---|---|
| CN102751982B (en) | 2014-10-29 |
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