CN102751172B - Integrated passive device and manufacture method thereof - Google Patents
Integrated passive device and manufacture method thereof Download PDFInfo
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- CN102751172B CN102751172B CN201110103127.2A CN201110103127A CN102751172B CN 102751172 B CN102751172 B CN 102751172B CN 201110103127 A CN201110103127 A CN 201110103127A CN 102751172 B CN102751172 B CN 102751172B
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Abstract
An embodiment of the invention provides an integrated passive device and a manufacture method thereof. The method includes: providing a semi-conductor substrate; forming a first electric conducting layer in the semi-conductor substrate; forming interconnection holes and a capacitance hole in the semi-conductor substrate, wherein the capacitance hole is adjacent to the first electric conducting layer; forming interconnection plugs in the interconnecting holes; forming an insulation layer on the lateral wall and the bottom of the capacitance hole; and forming a second electric conducting layer in the capacitance hole. The second electric conducting layer, the insulation layer and the first electric conducting layer form a capacitor. The integrated passive device and the manufacture method increase a capacitance range of interconnecting capacitors connected vertically between chips and meet application requirements.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly integrated passive devices including electric capacity and preparation method thereof.
Background technology
Silicon through hole technology (TSV, Through-Silicon-Via) is by making vertical conducting between chip and chip, realizes the state-of-the-art technology interconnected between chip.Encapsulate bonding from IC in the past and use the superimposing technique of salient point different, TSV technology can make chip maximum in the density that three-dimensional is stacking, and overall dimension is minimum, and greatly improves the performance of chip speed and low-power consumption.
Existing silicon through hole technology forms integrated passive devices usually on the semiconductor substrate.Described integrated passive devices comprises: interconnection capacitance and interconnection connector.The manufacture method of connector of wherein interconnecting comprises: on the surface of Semiconductor substrate side, form interconnected pores, be also formed with semiconductor device in described Semiconductor substrate; Then in described interconnected pores, fill metal, form interconnection connector; Then need to carry out thinning to the surface of the opposite side of described Semiconductor substrate, until expose the bottom of described interconnection connector, described interconnection connector is as the interconnection line be electrically connected between the semiconductor device formed in described Semiconductor substrate with the semiconductor device formed in other Semiconductor substrate.The manufacture method of described interconnection capacitance comprises: on the surface of described Semiconductor substrate side, form the first battery lead plate, insulating barrier and the second battery lead plate that are parallel to each other successively, described first battery lead plate, insulating barrier are parallel with the surface of described Semiconductor substrate side with the second battery lead plate.Particularly, please refer to the structural representation of the integrated passive devices of the prior art shown in Fig. 1.Described integrated passive devices comprises:
Semiconductor substrate 10, can be formed with semiconductor device in described Semiconductor substrate 10, described semiconductor device can be diode, triode etc.; Interlayer dielectric layer 12, is positioned in described Semiconductor substrate 10; First battery lead plate 002, is positioned at the surface of the close described interlayer dielectric layer 12 of described Semiconductor substrate 10, and described first battery lead plate 002 is adjacent with described interlayer dielectric layer 12; Insulating barrier 003, is positioned on described first battery lead plate 002, and described insulating barrier 003 is adjacent with described interlayer dielectric layer 12, and the thickness of described insulating barrier 003 is greater than 500 dusts; Second battery lead plate 001, is positioned on described insulating barrier 003, and described second battery lead plate 001 forms interconnection capacitance with described insulating barrier 003, first battery lead plate 002, and described second battery lead plate 001 is adjacent with described interlayer dielectric layer 12; Interconnected pores, runs through described interlayer dielectric layer 12 and Semiconductor substrate 10; Interconnection connector 11, fill with in described interconnected pores, the material of described interconnection connector 11 is metal.Described interconnection connector 11 and interconnection capacitance are for realizing the electrical connection between the semiconductor device in Semiconductor substrate 10 and the semiconductor device in other Semiconductor substrate.
The scope of the capacitance of the interconnection capacitance of the integrated passive devices of prior art is less, cannot meet the requirement of application.
Summary of the invention
The problem that the embodiment of the present invention solves is to provide a kind of integrated passive devices and preparation method thereof, and the capacitance value range of the interconnection capacitance of the vertical conducting between improve for chip, meets the requirement of application.
For solving the problem, the embodiment of the present invention provides a kind of manufacture method of integrated passive devices, comprising:
Semiconductor substrate is provided;
The first conductive layer is formed in described Semiconductor substrate;
In described Semiconductor substrate, form interconnected pores and electric capacity hole, described electric capacity hole and described first conductive layer adjacent;
Interconnection connector is formed in described interconnected pores;
Insulating barrier is formed on the sidewall in described electric capacity hole and bottom;
In described electric capacity hole, form the second conductive layer, described second conductive layer, insulating barrier and described first conductive layer form electric capacity.
Alternatively, the thickness range of described insulating barrier is 10 ~ 300 dusts.
Alternatively, the material of described insulating barrier is: silica, silicon nitride, carborundum, silicon oxynitride or high K dielectric.
Alternatively, described interconnected pores and electric capacity hole are formed in same etching technics.
Alternatively, the depth bounds of described interconnected pores is 10 microns ~ 100 microns.
Alternatively, the thickness range of described Semiconductor substrate is 200 microns ~ 800 microns.
Alternatively, the depth bounds in described electric capacity hole is 10 microns ~ 100 microns.
Alternatively, described first conductive layer is by carrying out ion implantation technology formation to Semiconductor substrate, and the conduction type of the Doped ions of described ion implantation technology is N-type or P type.
Alternatively in, the depth bounds of described ion implantation is 0.1 ~ 1 micron, and energy range is 13 ~ 400KeV, and dosage range is 5E13 ~ 1E16/cm
2.
Alternatively, described second conductive layer is identical with the material of interconnection connector, and the material of described second conductive layer and interconnection connector is metal.
Alternatively, the material of described second conductive layer and interconnection connector is copper or tungsten, and described second conductive layer and interconnection connector utilize same processing step to make.
Alternatively, after forming described interconnection connector and electric capacity, also comprise: carry out thinning to the surface of the side away from described interconnection connector and electric capacity of described Semiconductor substrate, until by the bottom-exposed of described interconnection connector, the thickness range of the Semiconductor substrate after thinning is 10 ~ 100 microns.
Correspondingly, the present invention also provides a kind of integrated passive devices, comprising:
Semiconductor substrate;
Interconnected pores, is positioned at described Semiconductor substrate, is filled with interconnection connector in described interconnected pores;
Electric capacity hole, is positioned at described Semiconductor substrate, and sidewall and the bottom in described electric capacity hole are formed with insulating barrier, are filled with the second conductive layer in described electric capacity hole;
First conductive layer, adjacent with described electric capacity hole, described first conductive layer, insulating barrier, the second conductive layer form electric capacity.
Alternatively, described first conductive layer is monocrystalline silicon or the polysilicon of doping.
Alternatively, the thickness range of described Semiconductor substrate is 10 ~ 100 microns.
Compared with prior art, the present invention has the following advantages:
The embodiment of the present invention forms insulating barrier and becomes the second conductive layer in electric capacity hole, be positioned at the first conductive layer of side, described electric capacity hole and described second conductive layer and insulating barrier and form electric capacity, and the interconnection capacitance of vertical conducting is compared with the parallel plate capacitor of arranging successively along semiconductor substrate surface between the chip of prior art, the depth bounds in electric capacity hole of the present invention is maximum can reach the degree of depth identical with described Semiconductor substrate, thus the area that can realize electric capacity two battery lead plates be oppositely arranged is improved, thus improve the capacitance of described electric capacity on a large scale; The electric capacity hole adjacent relative to formation two in Semiconductor substrate, and utilize oxidation technology in two electric capacity holes, form the scheme of insulating barrier, last filled conductive layer formation electric capacity in described two electric capacity holes, the present invention only needs an electric capacity hole, this makes etching technics more easily carry out, and reduces the stress that etching technics causes Semiconductor substrate;
Further, in an embodiment of the present invention, the thickness range of the insulating barrier of described electric capacity can be 10 ~ 300 dusts, thus make the distance of two of electric capacity battery lead plates more close, when taking the area of identical Semiconductor substrate, the capacitance of the electric capacity that the embodiment of the present invention is formed is larger;
Further, in an embodiment of the present invention, described interconnected pores and electric capacity hole can be formed in same etching technics, thus only need to form described electric capacity hole while formation interconnected pores, do not increase the complexity of technique;
Further, described first conductive layer is by carrying out ion implantation technology formation to Semiconductor substrate, thus the degree of depth of described first conductive layer can be adjusted by the degree of depth and dosage regulating ion implantation, thus the right opposite that can adjust the battery lead plate of electric capacity flexibly amasss, be more prone to the capacitance adjusting electric capacity accordingly, make technique flexible;
Further, described second conductive layer and interconnection connector utilize same electroplating technology to make, thus form described electric capacity while forming described interconnection connector, further simplification of flowsheet, reduce the cost of manufacture of electric capacity.
Accompanying drawing explanation
Fig. 1 is the structural representation of the interconnection capacitance of prior art.
Fig. 2 is the manufacture method schematic flow sheet of the integrated passive devices of one embodiment of the invention.
Fig. 3 ~ Fig. 9 is the cross-sectional view of the formation method of the integrated passive devices of one embodiment of the invention.
Embodiment
Because existing interconnection capacitance is parallel plate capacitor, described interconnection capacitance is included in the metal-insulator-metal being parallel to semiconductor substrate surface, thus forms the interconnection capacitance of vertical conducting between chip.
Incorporated by reference to Fig. 1, when needing the capacitance of electric capacity that formed larger, the right opposite between increase by first battery lead plate and the second battery lead plate is needed to amass, but due to the limited area of Semiconductor substrate, being limited in scope of the capacitance of described electric capacity.Further, because the thickness of described insulating barrier is greater than 500 dusts usually, make the capacitance of described electric capacity bigger than normal.
In order to solve the problem, the embodiment of the present invention proposes the manufacture method of integrated passive devices, and incorporated by reference to the manufacture method schematic flow sheet of the integrated passive devices of the one embodiment of the invention shown in Fig. 2, described method comprises:
Step S1, provides Semiconductor substrate;
Step S2, forms the first conductive layer in described Semiconductor substrate;
Step S3, forms interconnected pores and electric capacity hole in described Semiconductor substrate, described electric capacity hole and described first conductive layer adjacent;
Step S4, forms interconnection connector in described interconnected pores;
Step S5, insulating barrier is formed on the sidewall in described electric capacity hole and bottom;
Step S6, forms the second conductive layer in described electric capacity hole, and described second conductive layer, insulating barrier and described first conductive layer form electric capacity.
Below in conjunction with specific embodiment, technical scheme of the present invention is described in detail.In order to technical scheme of the present invention is described better, incorporated by reference to the cross-sectional view of the manufacture method of the integrated passive devices of the one embodiment of the invention shown in Fig. 3 ~ Fig. 9.
First, please refer to Fig. 3, Semiconductor substrate 100 is provided.The material of described Semiconductor substrate 100 can be silicon or germanium silicon, can be also silicon-on-insulator, or can also comprise other material, such as GaAs etc.In the present embodiment, the material of described Semiconductor substrate 100 is silicon, and the thickness range of described Semiconductor substrate 100 is 200 ~ 800 microns.Can form semiconductor device in described Semiconductor substrate 100, described semiconductor device can be the circuit that diode, triode or some diodes, triode etc. are formed.
Then, please refer to Fig. 4, in described Semiconductor substrate 100, form the first conductive layer 101.Described first conductive layer 101 is as a battery lead plate of electric capacity.In the present embodiment, described first conductive layer 101 is the monocrystalline silicon of doping.As an embodiment, described first conductive layer 101 can be formed by the ion implantation of Semiconductor substrate being carried out to local.Before carrying out described ion implantation, need to form mask layer on described Semiconductor substrate 100 surface, described mask layer will not need the locality protection carrying out ion implantation, and described mask layer can be photoresist layer.In the present embodiment, the conduction type of the Doped ions of described ion implantation can be N-type or P type.In the present embodiment, the conduction type of the Doped ions of described ion implantation is P type, and energy range is 13 ~ 400KeV, and dosage range is 5E13 ~ 1E16/cm
2.In other examples, the degree of depth of the battery lead plate formed as required and width, can also to the conduction type of the energy of described ion implantation and dosage and Doped ions, to obtain the first conductive layer meeting technological requirement.
As another embodiment of the present invention, the material of described first conductive layer 101 can also be the polysilicon of doping.The polysilicon of described doping can by carrying out etching technics in the corresponding region of Semiconductor substrate 100, groove is formed in described Semiconductor substrate 100, then carry out chemical vapor deposition method, in described groove, fill the polysilicon of doping, form described first conductive layer 101.The conduction type of the impurity of the polysilicon of described doping can be N-type or P type.
In other examples, the material of described first conductive layer 101 can also be monocrystalline germanium, polycrystalline germanium, germanium silicon or other semiconductor material.
Then, please refer to Fig. 5, as an embodiment, described Semiconductor substrate 100 forms interlayer dielectric layer 102, described interlayer dielectric layer 102 is as the hard mask layer in follow-up formation interconnected pores and electric capacity hole.Be formed with opening in described interlayer dielectric layer 102, described opening defines position and the shape in the follow-up interconnected pores that will be formed and electric capacity hole.
Then, please continue to refer to Fig. 5, carry out etching technics along the opening in described interlayer dielectric layer 102, formation interconnected pores and electric capacity hole in described interlayer dielectric layer 102 and semiconductor lining 100, the side in described electric capacity hole and the side of described first conductive layer 101 adjacent.Described electric capacity hole will form the insulating barrier of electric capacity and the another battery lead plate of electric capacity follow-up.
As one embodiment of the present of invention, described interconnected pores and electric capacity hole are formed in same etching technics.Described etching can adopt dry etching or wet-etching technology, to save processing step.As another embodiment of the present invention, described interconnected pores and electric capacity hole can also adopt etching technics to be formed respectively.
In the present embodiment, the thickness range of described Semiconductor substrate is 200 ~ 800 microns, and the depth bounds of described interconnected pores is 10 ~ 100 microns, and the depth bounds in described electric capacity hole is 10 ~ 100 microns.The degree of depth in described electric capacity hole can be identical with the degree of depth of described interconnected pores, also can be different.In the present embodiment, the degree of depth in described electric capacity hole is identical with the degree of depth of described interconnected pores.In other examples, the degree of depth in described electric capacity hole can also be larger than the degree of depth of described interconnected pores or little.
It should be noted that, as an embodiment, the present invention first forms the first conductive layer, then interconnected pores and electric capacity hole is formed, in other examples, the order of described interconnected pores, electric capacity hole and the first conductive layer can exchange, such as first can form interconnected pores and electric capacity hole, and then form described first conductive layer, even, multiple step can be utilized to form described interconnected pores, the first conductive layer and electric capacity hole successively or utilize multiple step to form described electric capacity hole, the first conductive layer and interconnected pores successively.
Then, form insulating barrier 103 at the sidewall of described electric capacity hole and interconnected pores and the surface of bottom and described interlayer dielectric layer 102, the material of described insulating barrier 103 is electrical insulation material.
Described electrical insulation material can be: silica, silicon nitride, carborundum, silicon oxynitride or high K dielectric.The thickness range of described insulating barrier 103 is 10 ~ 300 dusts.
As one embodiment of the present of invention, the material of described insulating barrier 103 is high K dielectric, described high K dielectric can be hafnium oxide, hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium or aluminium oxide etc., and described high K dielectric can utilize chemical vapor deposition method to make.
As another embodiment of the present invention, described insulating barrier 103 is only formed in sidewall and the bottom of described electric capacity hole and interconnected pores, and the material of described insulating barrier 103 is silica, and described insulating barrier 103 can utilize oxidation technology to make.
Described insulating barrier 103 is using the dielectric layer as electric capacity, because the thickness of the described insulating barrier 103 of embodiments of the invention formation is only 10 ~ 300 dusts, with the thickness of existing insulating barrier be greater than compared with 500 dusts, the thickness of insulating barrier 103 of the present invention is less, thus when taking the area of identical Semiconductor substrate, the capacitance of the electric capacity that the embodiment of the present invention is formed is larger.
Then, please refer to Fig. 7, form capacitance groove in the interlayer dielectric layer 102 on described first conductive layer 101, described capacitance groove exposes described first conductive layer 101, described capacitance groove is for filling the 3rd conductive layer, and described 3rd conductive layer is by the electric capacity of described follow-up formation and external electrical connections.The method forming described capacitance groove is the method for etching, and described etching can adopt dry etching or wet etching, and described dry etching or wet etching, as the known technology of those skilled in the art, are not described in detail at this.
Then, please refer to Fig. 8, in described interconnected pores, form interconnection connector 104, in described capacitance groove, form the 3rd conductive layer 106, in described electric capacity hole, form the second conductive layer 105.
As one embodiment of the present of invention, the material of described interconnection connector 104, described 3rd conductive layer 106, described second conductive layer 105 is identical.Described material can be metal, and described metal can be copper, aluminium, tungsten, titanium, cobalt.As an embodiment, described interconnection connector 104, described 3rd conductive layer 106, described second conductive layer 105 can adopt same processing step to make, and described processing step can be physical gas-phase deposition, sputtering or plating.In the present embodiment, the material of described interconnection connector 104, described 3rd conductive layer 106, described second conductive layer 105 is copper, and described interconnection connector 104, described 3rd conductive layer 106, described second conductive layer 105 utilize electroplating technology to make.
In other examples, the material of described interconnection connector 104, described 3rd conductive layer 106, described second conductive layer 105 is aluminium, and described interconnection connector 104, described 3rd conductive layer 106, described second conductive layer 105 utilize physical gas-phase deposition to make.Described second conductive layer 105, insulating barrier 103 between described second conductive layer 105 and the first conductive layer 101 and described first conductive layer 101 form electric capacity, and described electric capacity is as the interconnection capacitance of chip chamber vertical conducting.Described 3rd conductive layer 106 for by described electric capacity in external electrical connections.Described interconnection connector 104 is as the interconnection line of vertical conducting between chip.Because the thickness of described second conductive layer 105 and the maximum of the thickness of the first conductive layer 101 can be identical with the thickness of described Semiconductor substrate 100, thus the right opposite having increased substantially the second conductive layer 105 and the first conductive layer 101 amasss, thus the scope of the capacitance of the electric capacity of formation can be improved.And, the energy of the ion implantation of described first conductive layer 101, the degree of depth and dosage is formed by adjustment, can adjust the degree of depth and the width of the first conductive layer 105, thus the right opposite that can adjust described first conductive layer 101 and the second conductive layer 105 amasss, be conducive to the capacitance adjusting electric capacity.And due to the thinner thickness of the insulating barrier 103 between described first conductive layer 101 and the second conductive layer 105, thus the electric capacity had compared with bulky capacitor value can be formed, and be conducive to the area saving chip.
Then, please refer to Fig. 9, carry out thinning, until by the bottom-exposed of described interconnection connector 104 to the surface of the side away from described interconnection connector 104 and electric capacity of described Semiconductor substrate 100.As an embodiment, the thickness of the Semiconductor substrate 100 after thinning should equal the thickness of described interconnected pores, and the thickness range of the Semiconductor substrate 100 after thinning is 10 ~ 100 microns.
Correspondingly, the embodiment of the present invention also provides a kind of integrated passive devices, comprising:
Semiconductor substrate 100;
Interlayer dielectric layer 102, is positioned in described Semiconductor substrate 100;
Interconnected pores, is positioned at described Semiconductor substrate 100 and interlayer dielectric layer 102, is filled with interconnection connector 104 in described interconnected pores;
Electric capacity hole, is positioned at described interlayer dielectric layer 102;
Insulating barrier 103, covers the surface of the sidewall in described interconnected pores and electric capacity hole, bottom and interlayer dielectric layer 102;
Second conductive layer 105, be positioned at described electric capacity hole and interlayer dielectric layer 102, described second conductive layer 105 is positioned on described insulating barrier 103, and described electric capacity hole is filled full by described second conductive layer 105, and described second conductive layer 105 is as a battery lead plate of electric capacity;
First conductive layer 101, adjacent with described electric capacity hole, be positioned at described Semiconductor substrate 100, described first conductive layer 101 has a battery lead plate as electric capacity, thus described first conductive layer 101, insulating barrier 103, second conductive layer 105 between described second conductive layer 105 and the first conductive layer 101 form electric capacity;
Capacitance groove, is positioned at the interlayer dielectric layer 102 above described first conductive layer 101, is filled with the 3rd conductive layer 106 in described interconnected grooves, and described 3rd conductive layer 106 is for by described electric capacity and external electrical connections.
As an embodiment, described first conductive layer 101 is the semiconductor material of doping.Such as described first conductive layer 101 can be the monocrystalline silicon of doping or polysilicon.The conduction type of the impurity of described first conductive layer 101 can be N-type or P type.
The surface away from described interconnection connector 104 and electric capacity side of described Semiconductor substrate 100 is by the bottom-exposed of described interconnection connector 104 and electric capacity.The thickness range of described Semiconductor substrate 100 is 10 ~ 100 microns.
To sum up, the embodiment of the present invention forms insulating barrier and becomes the second conductive layer in electric capacity hole, be positioned at the first conductive layer of side, described electric capacity hole and described second conductive layer and insulating barrier and form electric capacity, and the interconnection capacitance of vertical conducting is compared with the parallel plate capacitor of arranging successively along semiconductor substrate surface between the chip of prior art, the depth bounds in electric capacity hole of the present invention is maximum can reach the degree of depth identical with described Semiconductor substrate, thus the area that can realize electric capacity two battery lead plates be oppositely arranged is improved, thus improve the capacitance of described electric capacity on a large scale; The electric capacity hole adjacent relative to formation two in Semiconductor substrate, and utilize oxidation technology in two electric capacity holes, form the scheme of insulating barrier, last filled conductive layer formation electric capacity in described two electric capacity holes, the present invention only needs an electric capacity hole, this makes etching technics more easily carry out, and reduces the stress that etching technics causes Semiconductor substrate;
Further, in an embodiment of the present invention, the thickness range of the insulating barrier of described electric capacity can be 10 ~ 300 dusts, thus make the distance of two of electric capacity battery lead plates more close, when taking the area of identical Semiconductor substrate, the capacitance of the electric capacity that the embodiment of the present invention is formed is larger;
Further, in an embodiment of the present invention, described interconnected pores and electric capacity hole can be formed in same etching technics, thus only need to form described electric capacity hole while formation interconnected pores, do not increase the complexity of technique;
Further, described first conductive layer is by carrying out ion implantation technology formation to Semiconductor substrate, thus the degree of depth of described first conductive layer can be adjusted by the degree of depth and dosage regulating ion implantation, thus the right opposite that can adjust the battery lead plate of electric capacity flexibly amasss, be more prone to the capacitance adjusting electric capacity accordingly, make technique flexible;
Further, described second conductive layer and interconnection connector utilize same electroplating technology to make, thus form described electric capacity while forming described interconnection connector, further simplification of flowsheet, reduce the cost of manufacture of electric capacity.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (15)
1. a manufacture method for integrated passive devices, is characterized in that, comprising:
Semiconductor substrate is provided;
Described Semiconductor substrate is carried out to the ion implantation technology of local, form the first conductive layer;
In described Semiconductor substrate, form interconnected pores and electric capacity hole, outside side wall and described first conductive layer in described electric capacity hole are adjacent;
Interconnection connector is formed in described interconnected pores;
Insulating barrier is formed on the inside side walls in described electric capacity hole and bottom;
In described electric capacity hole, form the second conductive layer, described second conductive layer, insulating barrier and described first conductive layer form electric capacity.
2. the manufacture method of integrated passive devices as claimed in claim 1, it is characterized in that, the thickness range of described insulating barrier is 10 ~ 300 dusts.
3. the manufacture method of integrated passive devices as claimed in claim 1, it is characterized in that, the material of described insulating barrier is: silica, silicon nitride, carborundum, silicon oxynitride, hafnium oxide, hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium or aluminium oxide.
4. the manufacture method of integrated passive devices as claimed in claim 1, it is characterized in that, described interconnected pores and electric capacity hole are formed in same etching technics.
5. the manufacture method of integrated passive devices as claimed in claim 1, it is characterized in that, the depth bounds of described interconnected pores is 10 microns ~ 100 microns.
6. the manufacture method of integrated passive devices as claimed in claim 1, it is characterized in that, the thickness range of described Semiconductor substrate is 200 microns ~ 800 microns.
7. the manufacture method of integrated passive devices as claimed in claim 1, it is characterized in that, the depth bounds in described electric capacity hole is 10 microns ~ 100 microns.
8. the manufacture method of integrated passive devices as claimed in claim 7, it is characterized in that, the conduction type of the Doped ions of described ion implantation technology is N-type or P type.
9. the manufacture method of integrated passive devices as claimed in claim 8, it is characterized in that, the depth bounds of described ion implantation is 0.1 ~ 1 micron, and energy range is 13 ~ 400KeV, and dosage range is 5E13 ~ 1E16/cm
2.
10. the manufacture method of integrated passive devices as claimed in claim 1, is characterized in that, described second conductive layer is identical with the material of interconnection connector, and the material of described second conductive layer and interconnection connector is metal.
The manufacture method of 11. integrated passive devices as claimed in claim 1, is characterized in that, the material of described second conductive layer and interconnection connector is copper or tungsten, and described second conductive layer and interconnection connector utilize same processing step to make.
The manufacture method of 12. integrated passive devices as claimed in claim 1, it is characterized in that, after forming described interconnection connector and electric capacity, also comprise: carry out thinning to the surface of the side away from described interconnection connector and electric capacity of described Semiconductor substrate, until by the bottom-exposed of described interconnection connector, the thickness range of the Semiconductor substrate after thinning is 10 ~ 100 microns.
13. 1 kinds of integrated passive devices, is characterized in that, comprising:
Semiconductor substrate;
Interconnected pores, is positioned at described Semiconductor substrate, is filled with interconnection connector in described interconnected pores;
Electric capacity hole, is positioned at described Semiconductor substrate, and inside side walls and the bottom in described electric capacity hole are formed with insulating barrier, are filled with the second conductive layer in described electric capacity hole;
First conductive layer, is formed after described Semiconductor substrate being carried out to the ion implantation technology of local, and adjacent with the outside side wall in described electric capacity hole, and described first conductive layer, insulating barrier, the second conductive layer form electric capacity.
14. integrated passive devices as claimed in claim 13, is characterized in that, described first conductive layer is monocrystalline silicon or the polysilicon of doping.
15. integrated passive devices as claimed in claim 13, is characterized in that, the thickness range of described Semiconductor substrate is 10 ~ 100 microns.
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| CN104486907B (en) * | 2014-12-10 | 2017-08-11 | 华进半导体封装先导技术研发中心有限公司 | The three-dimensionally integrated wafer level packaging structure of high-frequency I PD modules and method for packing |
| US10155656B2 (en) * | 2015-10-19 | 2018-12-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Inter-poly connection for parasitic capacitor and die size improvement |
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