CN102751172A - Integrated passive device and manufacture method thereof - Google Patents
Integrated passive device and manufacture method thereof Download PDFInfo
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- CN102751172A CN102751172A CN2011101031272A CN201110103127A CN102751172A CN 102751172 A CN102751172 A CN 102751172A CN 2011101031272 A CN2011101031272 A CN 2011101031272A CN 201110103127 A CN201110103127 A CN 201110103127A CN 102751172 A CN102751172 A CN 102751172A
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Abstract
An embodiment of the invention provides an integrated passive device and a manufacture method thereof. The method includes: providing a semi-conductor substrate; forming a first electric conducting layer in the semi-conductor substrate; forming interconnection holes and a capacitance hole in the semi-conductor substrate, wherein the capacitance hole is adjacent to the first electric conducting layer; forming interconnection plugs in the interconnecting holes; forming an insulation layer on the lateral wall and the bottom of the capacitance hole; and forming a second electric conducting layer in the capacitance hole. The second electric conducting layer, the insulation layer and the first electric conducting layer form a capacitor. The integrated passive device and the manufacture method increase a capacitance range of interconnecting capacitors connected vertically between chips and meet application requirements.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly include integrated passive devices of electric capacity and preparation method thereof.
Background technology
(TSV is through between chip and chip, making vertical conducting, realizing the state-of-the-art technology that interconnects between the chip Through-Silicon-Via) to silicon through hole technology.Different with the superimposing technique of using salient point with IC encapsulation bonding in the past, the TSV technology can make chip maximum in the density that three-dimensional piles up, and overall dimension is minimum, and improves the performance of chip speed and low-power consumption greatly.
Existing silicon through hole technology forms integrated passive devices usually on said Semiconductor substrate.Said integrated passive devices comprises: interconnection capacitance and interconnection connector.The manufacture method of connector of wherein interconnecting comprises: on the surface of Semiconductor substrate one side, form interconnected pores, also be formed with semiconductor device in the said Semiconductor substrate; In said interconnected pores, fill metal then, form the interconnection connector; Then need carry out attenuate to the surface of the opposite side of said Semiconductor substrate; Until the bottom of exposing said interconnection connector, said interconnection connector is as the interconnection line that is electrically connected between the semiconductor device that forms in the semiconductor device that forms in the said Semiconductor substrate and other Semiconductor substrate.The manufacture method of said interconnection capacitance comprises: on the surface of said Semiconductor substrate one side, form first battery lead plate, insulating barrier and second battery lead plate that is parallel to each other successively, said first battery lead plate, insulating barrier and second battery lead plate are surperficial parallel with said Semiconductor substrate one side.Particularly, please refer to the structural representation of the integrated passive devices of prior art shown in Figure 1.Said integrated passive devices comprises:
The scope of the capacitance of the interconnection capacitance of the integrated passive devices of prior art is less, can't satisfy the requirement of application.
Summary of the invention
The problem that the embodiment of the invention solves provides a kind of integrated passive devices and preparation method thereof, has improved the capacitance scope of the interconnection capacitance that is used for the vertical conducting between the chip, has satisfied the requirement of using.
For addressing the above problem, the embodiment of the invention provides a kind of manufacture method of integrated passive devices, comprising:
Semiconductor substrate is provided;
In said Semiconductor substrate, form first conductive layer;
In said Semiconductor substrate, form interconnected pores and electric capacity hole, said electric capacity hole and said first conductive layer are adjacent;
In said interconnected pores, form the interconnection connector;
Insulating barrier is formed on sidewall and bottom in said electric capacity hole;
In said electric capacity hole, form second conductive layer, said second conductive layer, insulating barrier and said first conductive layer constitute electric capacity.
Alternatively, the thickness range of said insulating barrier is 10～300 dusts.
Alternatively, the material of said insulating barrier is: silica, silicon nitride, carborundum, silicon oxynitride or high K medium.
Alternatively, said interconnected pores and electric capacity hole form in same etching technics.
Alternatively, the depth bounds of said interconnected pores is 10 microns～100 microns.
Alternatively, the thickness range of said Semiconductor substrate is 200 microns～800 microns.
Alternatively, the depth bounds in said electric capacity hole is 10 microns～100 microns.
Alternatively, said first conductive layer forms through Semiconductor substrate being carried out ion implantation technology, and the conduction type of the dopant ion of said ion implantation technology is N type or P type.
Alternatively in, the depth bounds that said ion injects is 0.1～1 micron, energy range is 13～400KeV, dosage range is 5E13～1E16/cm
2
Alternatively, said second conductive layer is identical with the material of interconnection connector, and said second conductive layer is a metal with the material of interconnection connector.
Alternatively, said second conductive layer is copper or tungsten with the material of interconnection connector, and said second conductive layer utilizes same processing step to make with the interconnection connector.
Alternatively; After forming said interconnection connector and electric capacity; Also comprise: attenuate is carried out on the surface away from a side of said interconnection connector and electric capacity to said Semiconductor substrate, and until the bottom-exposed with said interconnection connector, the thickness range of the Semiconductor substrate behind the attenuate is 10～100 microns.
Correspondingly, the present invention also provides a kind of integrated passive devices, comprising:
Semiconductor substrate;
Interconnected pores is positioned at said Semiconductor substrate, is filled with the interconnection connector in the said interconnected pores;
The electric capacity hole is positioned at said Semiconductor substrate, and the sidewall and the bottom in said electric capacity hole are formed with insulating barrier, and said electric capacity is filled with second conductive layer in the hole;
First conductive layer, adjacent with said electric capacity hole, said first conductive layer, insulating barrier, second conductive layer form electric capacity.
Alternatively, monocrystalline silicon or the polysilicon of said first conductive layer for mixing.
Alternatively, the thickness range of said Semiconductor substrate is 10～100 microns.
Compared with prior art, the present invention has the following advantages:
The embodiment of the invention forms insulating barrier and becomes second conductive layer in the electric capacity hole; Be positioned at first conductive layer and said second conductive layer and the insulating barrier formation electric capacity of said electric capacity hole one side; Compare for the parallel plate capacitor of arranging successively with the interconnection capacitance of vertical conducting between the chip of prior art along semiconductor substrate surface; The depth bounds maximum in electric capacity of the present invention hole can reach the degree of depth identical with said Semiconductor substrate; Thereby the area that can realize two battery lead plates that are oppositely arranged of electric capacity is improved on a large scale, thereby improves the capacitance of said electric capacity; With respect in Semiconductor substrate, forming two adjacent electric capacity holes; And utilize oxidation technology in two electric capacity holes, form insulating barrier, last in said two electric capacity holes the filled conductive layer constitute the scheme of electric capacity; The present invention only needs an electric capacity hole; This makes etching technics carry out more easily, and has reduced the stress that etching technics causes Semiconductor substrate;
Further; In an embodiment of the present invention; The thickness range of the insulating barrier of said electric capacity can be 10～300 dusts; Thereby make that the distance of two battery lead plates of electric capacity is more approaching, under the situation of the area that takies identical Semiconductor substrate, the capacitance of the electric capacity that the embodiment of the invention forms is bigger;
Further, in an embodiment of the present invention, said interconnected pores and electric capacity hole can form in same etching technics, thereby only need when forming interconnected pores, form said electric capacity hole, do not increase the complexity of technology;
Further; Said first conductive layer forms through Semiconductor substrate being carried out ion implantation technology; Thereby can be through the degree of depth of adjusting ion injection and the degree of depth of said first conductive layer of dosage adjustments; Thereby can adjust flexibly electric capacity battery lead plate over against area, be more prone to adjust the capacitance of electric capacity accordingly, make technology flexible;
Further, said second conductive layer utilizes same electroplating technology to make with the interconnection connector, thereby forms said electric capacity when forming said interconnection connector, further simplifies technological process, reduces the cost of manufacture of electric capacity.
Description of drawings
Fig. 1 is the structural representation of the interconnection capacitance of prior art.
Fig. 2 is the manufacture method schematic flow sheet of the integrated passive devices of one embodiment of the invention.
Fig. 3～Fig. 9 is the cross-sectional view of formation method of the integrated passive devices of one embodiment of the invention.
Embodiment
Because existing interconnection capacitance is a parallel plate capacitor, said interconnection capacitance is included in the metal level-insulating barrier-metal level that is parallel to semiconductor substrate surface, thereby forms the interconnection capacitance of vertical conducting between the chip.
Please combine Fig. 1, when the capacitance of the electric capacity that need to form is big, need to increase between first battery lead plate and second battery lead plate over against area, but because the area of Semiconductor substrate is limited, being limited in scope of the capacitance of said electric capacity.And, because the thickness of said insulating barrier makes that usually greater than 500 dusts the capacitance of said electric capacity is bigger than normal.
In order to address the above problem, the embodiment of the invention proposes the manufacture method of integrated passive devices, please combine the manufacture method schematic flow sheet of the integrated passive devices of one embodiment of the invention shown in Figure 2, and said method comprises:
Step S1 provides Semiconductor substrate;
Step S2 forms first conductive layer in said Semiconductor substrate;
Step S3 forms interconnected pores and electric capacity hole in said Semiconductor substrate, said electric capacity hole and said first conductive layer are adjacent;
Step S4 forms the interconnection connector in said interconnected pores;
Step S5, insulating barrier is formed on the sidewall in said electric capacity hole and bottom;
Step S6 forms second conductive layer in said electric capacity hole, said second conductive layer, insulating barrier and said first conductive layer constitute electric capacity.
Below in conjunction with concrete embodiment technical scheme of the present invention is carried out detailed explanation.For technical scheme of the present invention is described better, please combine the cross-sectional view of manufacture method of integrated passive devices of the one embodiment of the invention of Fig. 3～shown in Figure 9.
At first, please refer to Fig. 3, Semiconductor substrate 100 is provided.The material of said Semiconductor substrate 100 can be silicon or germanium silicon, also can be silicon-on-insulator, perhaps can also comprise other material, for example GaAs etc.In the present embodiment, the material of said Semiconductor substrate 100 is a silicon, and the thickness range of said Semiconductor substrate 100 is 200～800 microns.Can form semiconductor device in the said Semiconductor substrate 100, said semiconductor device can be the circuit of formations such as diode, triode or some diodes, triode.
Then, please refer to Fig. 4, in said Semiconductor substrate 100, form first conductive layer 101.Said first conductive layer 101 is as a battery lead plate of electric capacity.In the present embodiment, the monocrystalline silicon of said first conductive layer 101 for mixing.As an embodiment, said first conductive layer 101 can inject formation through Semiconductor substrate being carried out local ion.Before carrying out said ion injection, need form mask layers on said Semiconductor substrate 100 surfaces, said mask layer will need not carry out the locality protection that ion injects, and said mask layer can be photoresist layer.In the present embodiment, the conduction type of the dopant ion that said ion injects can be N type or P type.In the present embodiment, the conduction type of the dopant ion that said ion injects is the P type, and energy range is 13～400KeV, and dosage range is 5E13～1E16/cm
2In other embodiment, the degree of depth and the width of the battery lead plate that forms as required can also be to the energy of said ion injection and the conduction types of dosage and dopant ion, to obtain first conductive layer of according with process requirements.
As another embodiment of the present invention, the material of said first conductive layer 101 can also be the polysilicon that mixes.The polysilicon of said doping can carry out etching technics through the corresponding region in Semiconductor substrate 100; In said Semiconductor substrate 100, form groove; Carry out chemical vapor deposition method then, in said groove, fill the polysilicon that mixes, form said first conductive layer 101.The conduction type of the impurity of the polysilicon of said doping can be N type or P type.
In other embodiment, the material of said first conductive layer 101 can also be monocrystalline germanium, polycrystalline germanium, germanium silicon or other semiconductor material.
Then, please refer to Fig. 5, as an embodiment, on said Semiconductor substrate 100, form interlayer dielectric layer 102, said interlayer dielectric layer 102 is as the hard mask layer in follow-up formation interconnected pores and electric capacity hole.Be formed with opening in the said interlayer dielectric layer 102, said opening has defined the position and the shape in follow-up interconnected pores that will form and electric capacity hole.
Then; Please continue with reference to figure 5; Opening along in the said interlayer dielectric layer 102 carries out etching technics, serves as a contrast at said interlayer dielectric layer 102 and semiconductor and forms interconnected pores and electric capacity hole in 100, and a side of a side in said electric capacity hole and said first conductive layer 101 is adjacent.Said electric capacity hole will form the insulating barrier of electric capacity and the another battery lead plate of electric capacity follow-up.
As one embodiment of the present of invention, said interconnected pores and electric capacity hole form in same etching technics.Said etching can adopt dry etching or wet-etching technology, to practice thrift processing step.As another embodiment of the present invention, said interconnected pores and electric capacity hole can also adopt etching technics to form respectively.
In the present embodiment, the thickness range of said Semiconductor substrate is 200～800 microns, and the depth bounds of said interconnected pores is 10～100 microns, and the depth bounds in said electric capacity hole is 10～100 microns.The degree of depth in said electric capacity hole can be identical with the degree of depth of said interconnected pores, also can be different.In the present embodiment, the degree of depth in said electric capacity hole is identical with the degree of depth of said interconnected pores.In other embodiment, the degree of depth in said electric capacity hole can also be bigger or little than the degree of depth of said interconnected pores.
Need to prove; As an embodiment, the present invention forms first conductive layer earlier, forms interconnected pores and electric capacity hole then; In other embodiment; The order of said interconnected pores, electric capacity hole and first conductive layer can exchange, and for example can at first form interconnected pores and electric capacity hole, and then forms said first conductive layer; Even, can utilize a plurality of steps in sequence to form said interconnected pores, first conductive layer and electric capacity hole or utilize a plurality of steps in sequence to form said electric capacity hole, first conductive layer and interconnected pores.
Then, form insulating barrier 103 at the sidewall of said electric capacity hole and interconnected pores and the surface of bottom and said interlayer dielectric layer 102, the material of said insulating barrier 103 is the electrical insulation material.
Said electrical insulation material can be silica, silicon nitride, carborundum, silicon oxynitride or high K medium.The thickness range of said insulating barrier 103 is 10～300 dusts.
As one embodiment of the present of invention; The material of said insulating barrier 103 is high K medium; Said high K medium can be hafnium oxide, hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium or aluminium oxide etc., and said high K medium can utilize chemical vapor deposition method to make.
As another embodiment of the present invention, said insulating barrier 103 only is formed on the sidewall and the bottom of said electric capacity hole and interconnected pores, and the material of said insulating barrier 103 is a silica, and said insulating barrier 103 can utilize oxidation technology to make.
Said insulating barrier 103 will be as the dielectric layer of electric capacity; Because the thickness of the said insulating barrier 103 that embodiments of the invention form is merely 10～300 dusts; With comparing of the thickness of existing insulating barrier greater than 500 dusts; The thickness of insulating barrier 103 of the present invention is less, thereby takies under the situation of area of identical Semiconductor substrate, and the capacitance of the electric capacity that the embodiment of the invention forms is bigger.
Then; Please refer to Fig. 7, form the electric capacity groove in the interlayer dielectric layer 102 on said first conductive layer 101, said electric capacity groove exposes said first conductive layer 101; Said electric capacity groove is used to fill the 3rd conductive layer, and said the 3rd conductive layer is connected the electric capacity of said follow-up formation with external electric.The method that forms said electric capacity groove is the method for etching, and said etching can adopt dry etching or wet etching, and said dry etching or wet etching are not done detailed explanation as those skilled in the art's known technology at this.
Then, please refer to Fig. 8, in said interconnected pores, form interconnection connector 104, in said electric capacity groove, form the 3rd conductive layer 106, in said electric capacity hole, form second conductive layer 105.
As one embodiment of the present of invention, the material of said interconnection connector 104, said the 3rd conductive layer 106, said second conductive layer 105 is identical.Said material can be metal, and said metal can be copper, aluminium, tungsten, titanium, cobalt.As an embodiment, said interconnection connector 104, said the 3rd conductive layer 106, said second conductive layer 105 can adopt same processing step to make, and said processing step can be physical gas-phase deposition, sputter or plating.In the present embodiment, the material of said interconnection connector 104, said the 3rd conductive layer 106, said second conductive layer 105 is a copper, and said interconnection connector 104, said the 3rd conductive layer 106, said second conductive layer 105 utilize electroplating technology to make.
In other embodiment; The material of said interconnection connector 104, said the 3rd conductive layer 106, said second conductive layer 105 is an aluminium, and said interconnection connector 104, said the 3rd conductive layer 106, said second conductive layer 105 utilize physical gas-phase deposition to make.Said second conductive layer 105, the insulating barrier 103 between said second conductive layer 105 and first conductive layer 101 and said first conductive layer 101 constitute electric capacity, and said electric capacity is as the interconnection capacitance of chip chamber vertical conducting.Said the 3rd conductive layer 106 is used for said electric capacity is connected in external electric.Said interconnection connector 104 is as the interconnection line of vertical conducting between the chip.Because the thickness of said second conductive layer 105 can be identical with the thickness of said Semiconductor substrate 100 with the maximum of the thickness of first conductive layer 101; Thereby increased substantially second conductive layer 105 and first conductive layer 101 over against area, thereby can improve the scope of capacitance of the electric capacity of formation.And; Form energy, the degree of depth and the dosage of the ion injection of said first conductive layer 101 through adjustment; Can adjust the degree of depth and the width of first conductive layer 105, thus can adjust said first conductive layer 101 and second conductive layer 105 over against area, help adjusting the capacitance of electric capacity.And because the thinner thickness of the insulating barrier 103 between said first conductive layer 101 and second conductive layer 105, thereby can form electric capacity with big capacitance, and help practicing thrift area of chip.
Then, please refer to Fig. 9, attenuate is carried out on the surface away from a side of said interconnection connector 104 and electric capacity of said Semiconductor substrate 100, until bottom-exposed with said interconnection connector 104.As an embodiment, the thickness of the Semiconductor substrate 100 behind the attenuate should equal the thickness of said interconnected pores, and the thickness range of the Semiconductor substrate 100 behind the attenuate is 10～100 microns.
Correspondingly, the embodiment of the invention also provides a kind of integrated passive devices, comprising:
Interconnected pores is positioned at said Semiconductor substrate 100 and interlayer dielectric layer 102, is filled with interconnection connector 104 in the said interconnected pores;
The electric capacity hole is positioned at said interlayer dielectric layer 102;
Insulating barrier 103 covers the surface of sidewall, bottom and the interlayer dielectric layer 102 in said interconnected pores and electric capacity hole;
Second conductive layer 105; Be positioned at said electric capacity hole and interlayer dielectric layer 102; Said second conductive layer 105 is positioned on the said insulating barrier 103, and said second conductive layer 105 is full with the filling of said electric capacity hole, and said second conductive layer 105 is as a battery lead plate of electric capacity;
First conductive layer 101; Adjacent with said electric capacity hole; Be positioned at said Semiconductor substrate 100; Said first conductive layer 101 is as the battery lead plate that has of electric capacity, thereby said first conductive layer 101, the insulating barrier between said second conductive layer 105 and first conductive layer 101 103, second conductive layer 105 form electric capacity;
The electric capacity groove is positioned at the interlayer dielectric layer 102 of said first conductive layer 101 tops, is filled with the 3rd conductive layer 106 in the said interconnection groove, and said the 3rd conductive layer 106 is used for said electric capacity is connected with external electric.
As an embodiment, the semiconductor material of said first conductive layer 101 for mixing.For example said first conductive layer 101 can be monocrystalline silicon or the polysilicon that mixes.The conduction type of the impurity of said first conductive layer 101 can be N type or P type.
Said Semiconductor substrate 100 away from the surface of said interconnection connector 104 and electric capacity one side bottom-exposed with said interconnection connector 104 and electric capacity.The thickness range of said Semiconductor substrate 100 is 10～100 microns.
To sum up; The embodiment of the invention forms insulating barrier and becomes second conductive layer in the electric capacity hole; Be positioned at first conductive layer and said second conductive layer and the insulating barrier formation electric capacity of said electric capacity hole one side; Compare for the parallel plate capacitor of arranging successively with the interconnection capacitance of vertical conducting between the chip of prior art along semiconductor substrate surface; The depth bounds maximum in electric capacity of the present invention hole can reach the degree of depth identical with said Semiconductor substrate, thereby the area that can realize two battery lead plates that are oppositely arranged of electric capacity is improved on a large scale, thereby improves the capacitance of said electric capacity; With respect in Semiconductor substrate, forming two adjacent electric capacity holes; And utilize oxidation technology in two electric capacity holes, form insulating barrier, last in said two electric capacity holes the filled conductive layer constitute the scheme of electric capacity; The present invention only needs an electric capacity hole; This makes etching technics carry out more easily, and has reduced the stress that etching technics causes Semiconductor substrate;
Further; In an embodiment of the present invention; The thickness range of the insulating barrier of said electric capacity can be 10～300 dusts; Thereby make that the distance of two battery lead plates of electric capacity is more approaching, under the situation of the area that takies identical Semiconductor substrate, the capacitance of the electric capacity that the embodiment of the invention forms is bigger;
Further, in an embodiment of the present invention, said interconnected pores and electric capacity hole can form in same etching technics, thereby only need when forming interconnected pores, form said electric capacity hole, do not increase the complexity of technology;
Further; Said first conductive layer forms through Semiconductor substrate being carried out ion implantation technology; Thereby can be through the degree of depth of adjusting ion injection and the degree of depth of said first conductive layer of dosage adjustments; Thereby can adjust flexibly electric capacity battery lead plate over against area, be more prone to adjust the capacitance of electric capacity accordingly, make technology flexible;
Further, said second conductive layer utilizes same electroplating technology to make with the interconnection connector, thereby forms said electric capacity when forming said interconnection connector, further simplifies technological process, reduces the cost of manufacture of electric capacity.
Though the present invention with preferred embodiment openly as above; But it is not to be used for limiting the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention; Can utilize the method and the technology contents of above-mentioned announcement that technical scheme of the present invention is made possible change and modification, therefore, every content that does not break away from technical scheme of the present invention; To any simple modification, equivalent variations and modification that above embodiment did, all belong to the protection range of technical scheme of the present invention according to technical spirit of the present invention.
Claims (15)
1. the manufacture method of an integrated passive devices is characterized in that, comprising:
Semiconductor substrate is provided;
In said Semiconductor substrate, form first conductive layer;
In said Semiconductor substrate, form interconnected pores and electric capacity hole, said electric capacity hole and said first conductive layer are adjacent;
In said interconnected pores, form the interconnection connector;
Insulating barrier is formed on sidewall and bottom in said electric capacity hole;
In said electric capacity hole, form second conductive layer, said second conductive layer, insulating barrier and said first conductive layer constitute electric capacity.
2. the manufacture method of integrated passive devices as claimed in claim 1 is characterized in that, the thickness range of said insulating barrier is 10～300 dusts.
3. the manufacture method of integrated passive devices as claimed in claim 1 is characterized in that, the material of said insulating barrier is: silica, silicon nitride, carborundum, silicon oxynitride or high K medium.
4. the manufacture method of integrated passive devices as claimed in claim 1 is characterized in that, said interconnected pores and electric capacity hole form in same etching technics.
5. the manufacture method of integrated passive devices as claimed in claim 1 is characterized in that, the depth bounds of said interconnected pores is 10 microns～100 microns.
6. the manufacture method of integrated passive devices as claimed in claim 1 is characterized in that, the thickness range of said Semiconductor substrate is 200 microns～800 microns.
7. the manufacture method of integrated passive devices as claimed in claim 1 is characterized in that, the depth bounds in said electric capacity hole is 10 microns～100 microns.
8. want the manufacture method of 7 described integrated passive devices like right, it is characterized in that, said first conductive layer forms through Semiconductor substrate being carried out ion implantation technology, and the conduction type of the dopant ion of said ion implantation technology is N type or P type.
9. the manufacture method of integrated passive devices as claimed in claim 8 is characterized in that, the depth bounds that said ion injects is 0.1～1 micron, and energy range is 13～400KeV, and dosage range is 5E13～1E16/cm
2
10. the manufacture method of integrated passive devices as claimed in claim 1 is characterized in that, said second conductive layer is identical with the material of interconnection connector, and said second conductive layer is a metal with the material of interconnection connector.
11. the manufacture method of integrated passive devices as claimed in claim 1 is characterized in that, said second conductive layer is copper or tungsten with the material of interconnection connector, and said second conductive layer utilizes same processing step to make with the interconnection connector.
12. the manufacture method of integrated passive devices as claimed in claim 1; It is characterized in that; After forming said interconnection connector and electric capacity; Also comprise: attenuate is carried out on the surface away from a side of said interconnection connector and electric capacity to said Semiconductor substrate, and until the bottom-exposed with said interconnection connector, the thickness range of the Semiconductor substrate behind the attenuate is 10～100 microns.
13. an integrated passive devices is characterized in that, comprising:
Semiconductor substrate;
Interconnected pores is positioned at said Semiconductor substrate, is filled with the interconnection connector in the said interconnected pores;
The electric capacity hole is positioned at said Semiconductor substrate, and the sidewall and the bottom in said electric capacity hole are formed with insulating barrier,
Said electric capacity is filled with second conductive layer in the hole;
First conductive layer, adjacent with said electric capacity hole, said first conductive layer, insulating barrier, second conductive layer form electric capacity.
14. integrated passive devices as claimed in claim 13 is characterized in that, monocrystalline silicon or the polysilicon of said first conductive layer for mixing.
15. integrated passive devices as claimed in claim 13 is characterized in that, the thickness range of said Semiconductor substrate is 10～100 microns.
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|---|---|
| CN102751172B (en) | 2014-12-24 |
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