CN102738173A - Strained SiGe return-type channel SOI (silicon on insulator) BiCMOS (bipolar complementary metal oxide semiconductor) integrated device and preparation method - Google Patents

Strained SiGe return-type channel SOI (silicon on insulator) BiCMOS (bipolar complementary metal oxide semiconductor) integrated device and preparation method Download PDF

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CN102738173A
CN102738173A CN2012102436001A CN201210243600A CN102738173A CN 102738173 A CN102738173 A CN 102738173A CN 2012102436001 A CN2012102436001 A CN 2012102436001A CN 201210243600 A CN201210243600 A CN 201210243600A CN 102738173 A CN102738173 A CN 102738173A
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CN102738173B (en
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宋建军
胡辉勇
周春宇
吕懿
张鹤鸣
宣荣喜
舒斌
郝跃
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Xidian University
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Abstract

The invention discloses a strained SiGe return-type channel SOI BiCMOS integrated device and a preparation method. The preparation method comprises growing N-Si on an SOI substrate as the collector region of the bipolar device, etching a base region by lithography, growing P-SiGe, i-Si and i-Poly-Si on the base region, preparing deep trench isolation, and preparing an emitter, a base and a collector to obtain a SiGe HBT (heterojunction bipolar transistor); etching the active region of an NMOS (n-type metal oxide semiconductor) device by lithography, and epitaxially growing five material layers in the active region to obtain the active region of the NMOS device; etching the active region of a PMOS (p-type metal oxide semiconductor) device by lithography, epitaxially growing three material layers on the active region to obtain the active region of the PMOS device, preparing the NMOS device, forming a virtual gate of the PMOS device, and implanting to form the source and drain of the PMOS device by self-alignment process; and etching the virtual gate to complete the preparation of the PMOS device, and preparing the strained SiGe return-type channel SOI BiCMOS integrated device and circuit with a conductive channel of 22 to 45nm of the MOS device. The preparation method provided by the invention adopts the self-alignment process and fully utilizes the characteristics of carrier mobility anisotropy of the strained SiGe material to prepare the performance-enhanced strained SiGe return-type channel SOI BiCMOS integrated circuit.

Description

A kind of strain SiGe returns type channel SOI BiCMOS integrated device and preparation method
Technical field
The invention belongs to the semiconductor integrated circuit technical field, relate in particular to a kind of strain SiGe and return type channel SOI BiCMOS integrated device and preparation method.
Background technology
Semiconductor integrated circuit is the basis of electronics industry, and people impel the development in this field very rapid to the great demand of electronics industry.In decades in the past, the fast development of electronics industry has produced tremendous influence to social development and national economy.At present, electronics industry has become worldwide largest industry, and in occupation of very big share, the output value has surpassed 10,000 hundred million dollars in the world market.
Si CMOS integrated circuit has advantages such as low-power consumption, high integration, low noise and high reliability, in the semiconductor integrated circuit industry, has occupied ascendancy.Yet increase along with the reducing of the further increase of integrated circuit scale, device feature size, integrated level and complexity; Especially device feature size gets into after the nanoscale; The material of Si cmos device, the limitation of physical features have progressively manifested to come out, and have limited further developing of Si integrated circuit and manufacturing process thereof.Although microelectronics has obtained remarkable progress in research aspect compound semiconductor and other new material and the application in some field, far do not possess the condition that substitutes silica-based technology.And according to the science and technology development rule, a kind of new technology main force's technology from be born to becoming generally needs the time in twenty or thirty year.So in order to satisfy the needs that traditional performance improves, the performance that strengthens Si CMOS is considered to the developing direction of microelectronics industry.
Adopting strain Si, SiGe technology is to improve mobility through in traditional body Si device, introducing stress, improves device performance.The properties of product that silicon chip is produced improve 30%～60%, and process complexity and cost only increase by 1%～3%.As far as existing many integrated circuit production lines; If adopt the strain SiGe material that the Si CMOS ic core piece performance of producing is obviously improved, but also can prolong service life of the integrated circuit production line that the cost huge investment builds up greatly.
Summary of the invention
The object of the present invention is to provide a kind of strain SiGe to return type channel SOI BiCMOS integrated device and preparation method; To realize the utilizing anisotropic characteristics of strain SiGe material carrier mobility, prepare strain SiGe and return type raceway groove BiCMOS integrated device and circuit.
The object of the present invention is to provide a kind of strain SiGe to return type channel SOI BiCMOS integrated device, said BiCMOS device adopts SOI two polycrystal SiGe HBT device, strain SiGe vertical-channel nmos device and strain SiGe planar channeling PMOS devices.
Further, the nmos device conducting channel is the strain SiGe material, is tensile strain along channel direction.
Further, PMOS device conducting channel is the strain SiGe material, is compressive strain along channel direction.
Further, the emitter of said SiGe HBT device adopts polysilicon to contact with base stage.
Further, the base of said SiGe HBT device is the strain SiGe material.
Further, SiGe HBT device adopts the SOI substrate preparation.
Another object of the present invention is to provide a kind of strain SiGe to return the preparation method of type channel SOI BiCMOS integrated device, this preparation method comprises the steps:
The first step, to choose oxidated layer thickness be 300～400nm, and upper strata Si thickness is 100～150nm, and N type doping content is 1 * 10 16～1 * 10 17Cm -3The SOI substrate slice;
Second goes on foot, utilizes the method for chemical vapor deposition (CVD), at 600～750 ℃, and growth Si epitaxial loayer on substrate, thickness is 250～300nm, and the N type mixes, and doping content is 1 * 10 16～1 * 10 17Cm -3, as collector region;
The 3rd goes on foot, utilizes the method for chemical vapor deposition (CVD), at 600～800 ℃, is the SiO of 200 ~ 300nm at substrate surface deposit one layer thickness 2A layer and a layer thickness are the SiN layer of 100 ~ 200nm; The photoetching base utilizes dry etching, etches the degree of depth and be the zone, base of 200nm, and at substrate surface growth trilaminate material: ground floor is the SiGe layer, and the Ge component is 15 ~ 25%, and thickness is 20 ~ 60nm, and the P type mixes, and doping content is 5 * 10 18~ 5 * 10 19Cm -3, as the base; The second layer is unadulterated intrinsic Si layer, and thickness is 10 ~ 20nm; The 3rd layer is unadulterated intrinsic Poly-Si layer, and thickness is 200～300nm, as base stage and emitter region;
The 4th goes on foot, utilizes the method for chemical vapor deposition (CVD), at 600～800 ℃, is the SiO of 200 ~ 300nm at substrate surface deposit one layer thickness 2A layer and a layer thickness are the SiN layer of 100 ~ 200nm; Deep trench isolation zone between lithographic device, dry etching goes out the deep trouth that the degree of depth is 5 μ m in the deep trench isolation zone, utilizes chemical vapor deposition (CVD) method, at 600～800 ℃, in deep trouth, fills SiO 2
The 5th goes on foot, falls with wet etching the SiO on surface 2With the SiN layer, utilize the method for chemical vapor deposition (CVD) again, at 600～800 ℃, be the SiO of 200 ~ 300nm at substrate surface deposit one layer thickness 2A layer and a layer thickness are the SiN layer of 100 ~ 200nm; Photoetching collector region shallow trench isolation areas goes out the shallow slot that the degree of depth is 180 ~ 300nm at the shallow trench isolation areas dry etching, utilizes chemical vapor deposition (CVD) method, at 600～800 ℃, in shallow slot, fills SiO 2
The 6th goes on foot, falls with wet etching the SiO on surface 2With the SiN layer, utilize the method for chemical vapor deposition (CVD), at 600～800 ℃, be the SiO of 300 ~ 500nm at substrate surface deposit one layer thickness 2Layer; The photoetching base region carries out p type impurity to this zone and injects, and making base stage contact zone doping content is 1 * 10 19～1 * 10 20Cm -3, form the base stage contact area;
The 7th step, photoetching emitting area carry out N type impurity to this zone and inject, and making doping content is 1 * 10 17～5 * 10 17Cm -3, form the emitter region;
The 8th step, photoetching collector region, and utilize the method for chemico-mechanical polishing (CMP), remove intrinsic Si layer and the intrinsic Poly-Si layer of collector region, the injection of N type impurity is carried out in this zone, making collector electrode contact zone doping content is 1 * 10 19～1 * 10 20Cm -3, form collector contact area; And to substrate under 950～1100 ℃ of temperature, annealing 15～120s carries out impurity activation, forms SiGe HBT device;
The 9th step, photoetching nmos device active area; Utilize dry etch process, etch the deep trouth that the degree of depth is 2～3 μ m, oxide layer is carved pass through at the nmos device active area; Utilize the method for chemical vapor deposition (CVD); At 600～750 ℃, five layer materials of in deep trouth, growing continuously: ground floor is that thickness is the N type Si epitaxial loayer of 1.8～2.6 μ m, and doping content is 5 * 10 19～1 * 10 20Cm -3, as the nmos device drain region; The second layer is that thickness is the N type strain SiGe layer of 3～5nm, and doping content is 1～5 * 10 18Cm -3, the Ge component is 10%, as a N type lightly-doped source drain structure (N-LDD) layer of nmos device; The 3rd layer is that thickness is the P type strain SiGe layer of 22～45nm, and doping content is 5 * 10 16～5 * 10 17Cm -3, the Ge component is a Gradient distribution, and lower floor is 10%, and the upper strata is 20～30% Gradient distribution, as the nmos device channel region; The 4th layer is that thickness is the N type strain SiGe layer of 3～5nm, and doping content is 1～5 * 10 18Cm -3, the Ge component is for being 20～30%, as the 2nd N type lightly-doped source drain structure (N-LDD) layer of nmos device; Layer 5 is that thickness is the N type Si layer of 200～400nm, and doping content is 5 * 10 19～1 * 10 20Cm -3, as the nmos device source region;
The tenth goes on foot, utilizes the method for chemical vapor deposition (CVD), at 600～780 ℃, at substrate surface deposit one deck SiO 2, photoetching PMOS device active region etches the shallow slot that the degree of depth is 100nm at the PMOS device active region, utilizes the method for chemical vapor deposition (CVD), at 600～750 ℃, mixes in PMOS device area growth one deck N type, and doping content is 5 * 10 16～5 * 10 17Cm -3, thickness is the Si epitaxial loayer of 80nm, regrowth one N type strain SiGe layer, and the Ge component is 10～30%, thickness is 10～20nm, the intrinsic relaxation Si cap layer of growing at last, thickness is 3～5nm, forms the PMOS device active region;
The 11 the step, utilize chemical vapor deposition (CVD) method, at 600～780 ℃, at substrate surface deposit one deck SiO 2And layer of sin, form the barrier layer; The photoetching nmos device leaks groove, utilizes dry etch process, and etching the degree of depth is the leakage groove of 0.4～0.6 μ m; Utilize chemical vapor deposition (CVD) method, at 600～780 ℃, at substrate surface deposit one deck SiO 2, forming nmos device and leak the trenched side-wall isolation, dry etching falls the SiO on surface 2, keep the SiO that leaks trenched side-wall 2, utilize chemical vapor deposition (CVD) method, at 600～780 ℃, the deposit doping content is 1～5 * 10 20Cm -3N type Ploy-Si, groove is filled up, chemico-mechanical polishing (CMP) method is removed the unnecessary Ploy-Si of substrate surface, forms nmos device and leaks the bonding pad; Utilize wet etching, etch away the layer SiO on surface 2And SiN;
The 12 the step, utilize chemical vapor deposition (CVD) method, at 600～780 ℃, at substrate surface deposit one deck SiO 2And layer of sin, form the barrier layer once more; Photoetching nmos device grid window utilizes dry etch process, etches the gate groove that the degree of depth is 0.4～0.6 μ m; Utilizing atomic layer chemical vapour deposition (ALCVD) method, at 300～400 ℃, is the HfO of 5～8nm at substrate surface deposit one layer thickness 2, form the nmos device gate dielectric layer, utilize chemical vapor deposition (CVD) method then, at 600～780 ℃, be 1～5 * 10 in substrate surface deposit doping content 20Cm -3N type Poly-Si, the nmos device gate groove is filled up, get rid of the nmos device gate groove again with outer surface part Poly-Si and HfO 2, form nmos device grid, source region, finally form nmos device; Utilize wet etching, etch away the layer SiO on surface 2And SiN;
The 13 the step, utilize chemical vapor deposition (CVD) method, at 600～780 ℃, at substrate surface deposit one deck SiO 2, photoetching PMOS device active region utilizes chemical vapor deposition (CVD) method, at 600～780 ℃, is the SiO of 10～15nm at substrate surface deposit one layer thickness 2With a layer thickness be the Poly-Si of 200～300nm, photoetching Poly-Si and SiO 2, form the empty grid of PMOS device; The PMOS device is carried out P type ion inject, forming doping content is 1～5 * 10 18Cm -3P type lightly-doped source drain structure (P-LDD);
The 14 the step, utilize chemical vapor deposition (CVD) method, at 600～780 ℃, deposit one layer thickness is the SiO of 3～5nm on substrate surface 2, dry etching falls the SiO on the substrate surface 2, the SiO of reservation Ploy-Si sidewall 2, form PMOS device gate electrode side wall; Again the PMOS device active region is carried out P type ion and inject, autoregistration generates the source region and the drain region of PMOS device, makes the source-drain area doping content reach 5 * 10 19～1 * 10 20Cm -3
The 15 the step, utilize chemical vapor deposition (CVD) method, at 600～780 ℃, at substrate surface deposit SiO 2Layer with chemico-mechanical polishing (CMP) method flat surface, is used dry etch process etching surface SiO again 2To empty grid upper surface, expose empty grid; The empty grid of wet etching form a groove at the gate electrode place; Utilize chemical vapor deposition (CVD) method, at 600～780 ℃, at substrate surface deposit one deck SiON, thickness is 1.5～5nm; With physical vapor deposition (PVD) deposit W-TiN composite grid, (CMP) removes surface metal with chemico-mechanical polishing, with the stop layer of W-TiN composite grid as chemico-mechanical polishing (CMP), thereby forms grid, finally forms the PMOS device;
The 16 the step, utilize chemical vapor deposition (CVD) method, at 600～780 ℃, at substrate surface deposit SiO 2Layer, lithography fair lead, metallization, splash-proofing sputtering metal, photoetching lead-in wire, formation MOS device conducting channel are that the strain SiGe of 22～45nm returns type channel SOI BiCMOS integrated device.
Further, the nmos device channel length confirms according to the P type strain SiGe layer thickness of the 9th step deposit, gets 22～45nm; The PMOS device channel length is controlled by photoetching process.
Further, SiGe HBT device base thickness according to the 3rd the step SiGe epitaxy layer thickness decide, get 20～60nm.
Another object of the present invention is to provide a kind of strain SiGe to return the preparation method of type channel SOI BiCMOS integrated circuit, this preparation method comprises the steps:
Step 1, the implementation method of epitaxial material preparation is:
(1a) choose the SOI substrate slice, this substrate lower layer support material is Si, and the intermediate layer is SiO 2, thickness is 400nm, upper layer of material is that doping content is 1 * 10 17Cm -3N type Si, thickness is 150nm;
(1b) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the N type epitaxy Si layer of 300nm on the Si material of upper strata, and as collector region, this layer doping content is 1 * 10 17Cm -3
(1c) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer;
(1d) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiN layer of 200nm at substrate surface deposit one layer thickness;
(1e) the photoetching base utilizes dry etching, and etching the degree of depth is the zone, base of 200nm;
(1f) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the SiGe layer of 60nm on substrate, and as the base, this layer Ge component is 25%, and doping content is 5 * 10 19Cm -3
(1g) utilize the method for chemical vapor deposition (CVD), at 750 ℃, the unadulterated intrinsic Si layer of growth one layer thickness 20nm on substrate;
(1h) utilize the method for chemical vapor deposition (CVD), at 750 ℃, the unadulterated intrinsic Poly-Si layer of growth one layer thickness 300nm on substrate;
Step 2, the implementation method of device deep trench isolation preparation is:
(2a) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer;
(2b) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiN layer of 200nm at substrate surface deposit one layer thickness;
(2c) deep trench isolation zone between the lithographic device, dry etching goes out the deep trouth that the degree of depth is 5 μ m in the deep trench isolation zone;
(2d) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 800 ℃ 2, form the device deep trench isolation;
Step 3, the implementation method of collector electrode shallow-trench isolation preparation is:
(3a) fall surperficial SiO with wet etching 2With the SiN layer;
(3b) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer;
(3c) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiN layer of 200nm at substrate surface deposit one layer thickness;
(3d) photoetching collector electrode shallow trench isolation areas goes out the shallow slot that the degree of depth is 300nm at the shallow trench isolation areas dry etching;
(3e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 800 ℃ 2, form the collector electrode shallow-trench isolation;
Step 4, the implementation method of base stage shallow-trench isolation preparation is:
(4a) fall surperficial SiO with wet etching 2With the SiN layer;
(4b) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer;
(4c) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiN layer of 200nm at substrate surface deposit one layer thickness;
(4d) photoetching base stage shallow trench isolation areas goes out the shallow slot that the degree of depth is 325nm at the shallow trench isolation areas dry etching;
(4e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 800 ℃ 2, form the base stage shallow-trench isolation;
Step 5, the implementation method that SiGe HBT forms is:
(5a) fall surperficial SiO with wet etching 2With the SiN layer;
(5b) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiO of 500nm at substrate surface deposit one layer thickness 2Layer;
(5c) photoetching base region carries out p type impurity to this zone and injects, and making the contact zone doping content is 1 * 10 20Cm -3, form base stage;
(5d) photoetching emitter region is carried out N type impurity to this zone and is injected, and making doping content is 5 * 10 17Cm -3, form the emitter region;
(5e) photoetching collector region, and utilize the method for chemico-mechanical polishing (CMP), remove intrinsic Si layer and the intrinsic Poly-Si layer of collector region, the injection of N type impurity is carried out in this zone, making collector electrode contact zone doping content is 1 * 10 20Cm -3, form collector electrode;
(5f) to substrate under 1100 ℃ of temperature, annealing 15s carries out impurity activation, forms SiGe HBT;
Step 6, the implementation method of MOS epitaxial material preparation is:
(6a) photoetching nmos device active area utilizes dry etch process, etches the deep trouth that the degree of depth is 3 μ m at the nmos device active area;
(6b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the N type Si epitaxial loayer of 2.6 μ m at nmos device active area selective growth thickness, and doping content is 5 * 10 19Cm -3, as the nmos device drain region;
(6c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the N type strain SiGe layer of 5nm at nmos device active area selective growth thickness, and doping content is 5 * 10 17Cm -3, the Ge component is 10%, as a N type lightly-doped source drain structure (N-LDD) layer of nmos device;
(6d) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the P type strain SiGe layer of 45nm at nmos device active area selective growth thickness, and doping content is 5 * 10 16Cm -3, the Ge component is a Gradient distribution, and lower floor is 10%, and the upper strata is 30%, as the nmos device channel region;
(6e) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the N type strain SiGe layer of 5nm at nmos device active area selective growth thickness, and doping content is 5 * 10 17Cm -3, the Ge component is 30%, as the 2nd N type lightly-doped source drain structure (N-LDD) layer of nmos device;
(6f) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the N type Si layer of 400nm at nmos device active area selective growth thickness, and doping content is 5 * 10 19Cm -3, as the nmos device source region;
(6g) utilize the method for chemical vapor deposition (CVD), at 600 ℃, at substrate surface deposit one deck SiO 2
(6h) photoetching PMOS device active region etches the shallow slot that the degree of depth is 100nm at the PMOS device active region;
(6i) utilize the method for chemical vapor deposition (CVD), at 600 ℃, mix in PMOS device area growth one deck N type, doping content is 5 * 10 16Cm -3, thickness is the Si epitaxial loayer of 80nm, regrowth one N type strain SiGe layer, and doping content is 5 * 10 16Cm -3, the Ge component is 10%, thickness is 20nm;
(6j) utilize the method for chemical vapor deposition (CVD), at 600 ℃, at PMOS device active region selective growth one intrinsic relaxation Si cap layer, thickness is 5nm, forms the PMOS device active region;
Step 7, nmos device are leaked the implementation method that connects preparation and are:
(7a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at nmos device surfaces of active regions deposit one deck SiO 2And layer of sin, form the barrier layer;
(7b) the photoetching nmos device leaks groove, utilizes dry etch process, and etching the degree of depth is the leakage groove of 0.6 μ m;
(7c) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one deck SiO 2, forming nmos device and leak the trenched side-wall isolation, dry etching falls the SiO on surface 2, keep the SiO that leaks trenched side-wall 2
(7d) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is 1 * 10 in substrate surface deposit doping content 20Cm -3N type Ploy-Si, nmos device is leaked groove fills up;
(7e) utilize chemico-mechanical polishing (CMP) method, remove the unnecessary Ploy-Si of substrate surface, form nmos device and leak the bonding pad;
(7f) utilize wet etching, etch away the layer SiO on surface 2And SiN;
Step 8, the implementation method that nmos device forms is:
(8a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at nmos device surfaces of active regions deposit one deck SiO 2And layer of sin, form the barrier layer once more;
(8b) photoetching nmos device grid window utilizes dry etch process, etches the gate groove that the degree of depth is 0.6 μ m;
(8c) utilizing atomic layer chemical vapour deposition (ALCVD) method, at 300 ℃, is the HfO of 5nm at substrate surface deposit one layer thickness 2, form the nmos device gate dielectric layer;
(8d) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is 1 * 10 in substrate surface deposit doping content 20Cm -3N type Poly-Si, the nmos device gate groove is filled up;
(8e) get rid of nmos device gate groove surperficial part Poly-Si and HfO again 2Layer forms nmos device grid, source region, finally forms nmos device;
(8f) utilize wet etching, etch away the SiO on surface 2With the SiN layer;
Step 9, the implementation method that preparation is leaked in empty grid of PMOS device and source is:
(9a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at nmos device surfaces of active regions deposit one deck SiO 2
(9b) photoetching PMOS device active region utilizes chemical vapor deposition (CVD) method, at 600 ℃, is the SiO of 10nm at substrate surface deposit one layer thickness 2
(9c) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is the Poly-Si of 200nm at substrate surface deposit one layer thickness;
(9d) photoetching Poly-Si and SiO 2, form the empty grid of PMOS device;
(9e) the PMOS device is carried out P type ion and inject, forming doping content is 1 * 10 18Cm -3P type lightly-doped source drain structure (P-LDD);
(9f) utilize chemical vapor deposition (CVD) method, at 600 ℃, deposit one layer thickness is the SiO of 3nm on substrate surface 2, dry etching falls the SiO on the substrate surface 2, the SiO of reservation Ploy-Si sidewall 2, form PMOS device gate electrode side wall;
(9g) the PMOS device active region is carried out P type ion and inject, autoregistration generates the source region and the drain region of PMOS device, makes the source-drain area doping content reach 5 * 10 19Cm -3
Step 10, the implementation method that the PMOS device forms is:
(10a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit SiO 2Layer with chemico-mechanical polishing (CMP) method flat surface, is used dry etch process etching surface SiO again 2To empty grid upper surface, expose empty grid;
(10b) the empty grid of wet etching form a groove at the gate electrode place;
(10c) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one deck SiON, thickness is 5nm;
(10d) with physical vapor deposition (PVD) deposit W-TiN composite grid, (CMP) removes surface metal with chemico-mechanical polishing;
(10e) with the stop layer of W-TiN composite grid, thereby form grid, finally form the PMOS device as chemico-mechanical polishing (CMP);
Step 11, the implementation method that constitutes the BiCMOS integrated circuit is:
(11a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit SiO 2Layer;
(11b) lithography fair lead;
(11c) metallization;
(11d) splash-proofing sputtering metal, photoetching lead-in wire, formation MOS device conducting channel are that the strain SiGe of 45nm returns type channel SOI BiCMOS integrated device and circuit.
The present invention has following advantage:
1. the strain SiGe of the present invention's preparation returns in the type channel SOI BiCMOS integrated device, has made full use of the characteristic of each diversity of strain SiGe material stress, introduces compressive strain in the horizontal direction, has improved PMOS device hole mobility; Introduce tensile strain in vertical direction, improved the nmos device electron mobility, therefore, performances such as this device frequency and current driving ability are higher than unidimensional relaxation Si cmos device;
2. the present invention returns in the type channel SOI BiCMOS integrated device process at the preparation strain SiGe; Employing selective epitaxial technology; Respectively at nmos device and PMOS device active region selective growth strain SiGe material; Improve the flexibility of designs, strengthened cmos device and integrated circuit electric property;
3. the strain SiGe of the present invention's preparation returns in the type channel SOI BiCMOS integrated device structure; The channel direction of nmos device is a vertical direction, and raceway groove is the strain SiGe layer of chemical vapor deposition (CVD) method preparation, and the thickness of SiGe layer is the channel length of nmos device; Therefore; In the preparation of nmos device, avoid the photoetching of small size grid, reduced process complexity, reduced cost;
4. the strain SiGe of the present invention preparation raceway groove that returns nmos device in the type channel SOI BiCMOS integrated device structure is back type; Promptly grid can be controlled raceway groove on four sides in groove; Therefore, this device has increased the width of raceway groove in limited zone, thereby has improved the current driving ability of device; Increase the integrated level of integrated circuit, reduced the manufacturing cost of lsi unit area;
5. the strain SiGe of the present invention preparation returns that nmos device raceway groove Ge component changes in gradient in the type channel SOI BiCMOS integrated device structure; Therefore can produce the built-in field that an accelerated electron transports at channel direction; Strengthen the carrier transport ability of raceway groove, thereby improved the frequency characteristic and the current driving ability of strain SiGe nmos device;
6. the strain SiGe of the present invention preparation returns the HfO that nmos device in the type channel SOI BiCMOS integrated device structure has adopted high K value 2As gate medium, improved the grid-control ability of nmos device, strengthened the electric property of nmos device;
7. the strain SiGe of the present invention preparation returns that the PMOS device is a quantum well devices in the type channel SOI BiCMOS integrated device structure; Be that the strain SiGe channel layer is between Si cap layer and the body Si layer; Compare with the surface channel device; This device can reduce the channel interface scattering effectively, has improved the device electrology characteristic; Simultaneously, SQW can make the problem in the hot electron injection grid medium improve, and has increased the reliability of device and circuit;
8. the strain SiGe of the present invention's preparation returns in the type channel SOI BiCMOS integrated device structure, and the PMOS device adopts SiON to replace traditional pure SiO 2Do gate medium, not only strengthened the reliability of device, and utilize the variation of gate medium dielectric constant, improved the grid-control ability of device;
9. to return the maximum temperature that relates in the type channel SOI BiCMOS integrated device process be 800 ℃ at the preparation strain SiGe in the present invention; Be lower than the technological temperature that causes strain SiGe channel stress relaxation; Therefore this preparation method can keep strain SiGe channel stress effectively, improves the performance of integrated circuit;
10. the present invention prepares strain SiGe and returns in the type channel SOI BiCMOS integrated device process; The PMOS device has adopted metal gate mosaic technology (damascene process) preparation gate electrode; This gate electrode is a metal W-TiN composite construction, because the TiN of lower floor and strain Si and strain SiGe material work function difference are less, has improved electric properties of devices; The W on upper strata then can reduce the resistance of gate electrode, has realized the optimization of gate electrode;
11. the strain SiGe of the present invention's preparation returns emitter, the base stage of SiGe HBT device in the type channel SOI BiCMOS integrated device and adopts polycrystalline; Polycrystalline can partly be produced on above the oxide layer; Reduce the area of device active region, thereby reduced device size, improved the integrated level of circuit.
Description of drawings
Fig. 1 is the realization flow figure that strain SiGe provided by the invention returns type channel SOI BiCMOS integrated device and circuit preparation method.
Embodiment
In order to make the object of the invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with accompanying drawing and embodiment.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
The embodiment of the invention provides a kind of strain SiGe to return type channel SOI BiCMOS integrated device, and said BiCMOS device adopts SOI two polycrystal SiGe HBT device, strain SiGe vertical-channel nmos device and strain SiGe planar channeling PMOS devices.
As a prioritization scheme of the embodiment of the invention, the nmos device conducting channel is the strain SiGe material, is tensile strain along channel direction.
As a prioritization scheme of the embodiment of the invention, PMOS device conducting channel is the strain SiGe material, is compressive strain along channel direction.
As a prioritization scheme of the embodiment of the invention, the emitter of said SiGe HBT device adopts polysilicon to contact with base stage.
As a prioritization scheme of the embodiment of the invention, the base of SiGe HBT device is the strain SiGe material.
As a prioritization scheme of the embodiment of the invention, SiGe HBT device adopts the SOI substrate preparation.
Following with reference to accompanying drawing 1, strain SiGe of the present invention is returned type channel SOI BiCMOS integrated device and circuit preparation method technological process describes in further detail.
Embodiment 1: the preparation conducting channel is that the strain SiGe of 45nm returns type channel SOI BiCMOS integrated device and circuit, and concrete steps are following:
Step 1, the epitaxial material preparation.
(1a) choose the SOI substrate slice, this substrate lower layer support material is Si, and the intermediate layer is SiO 2, thickness is 400nm, upper layer of material is that doping content is 1 * 10 17Cm -3N type Si, thickness is 150nm;
(1b) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the N type epitaxy Si layer of 300nm on the Si material of upper strata, and as collector region, this layer doping content is 1 * 10 17Cm -3
(1c) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer;
(1d) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiN layer of 200nm at substrate surface deposit one layer thickness;
(1e) the photoetching base utilizes dry etching, and etching the degree of depth is the zone, base of 200nm;
(1f) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the SiGe layer of 60nm on substrate, and as the base, this layer Ge component is 25%, and doping content is 5 * 10 19Cm -3
(1g) utilize the method for chemical vapor deposition (CVD), at 750 ℃, the unadulterated intrinsic Si layer of growth one layer thickness 20nm on substrate;
(1h) utilize the method for chemical vapor deposition (CVD), at 750 ℃, the unadulterated intrinsic Poly-Si layer of growth one layer thickness 300nm on substrate.
Step 2, the preparation of device deep trench isolation.
(2a) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer;
(2b) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiN layer of 200nm at substrate surface deposit one layer thickness;
(2c) deep trench isolation zone between the lithographic device, dry etching goes out the deep trouth that the degree of depth is 5 μ m in the deep trench isolation zone;
(2d) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 800 ℃ 2, form the device deep trench isolation.
Step 3, the preparation of collector electrode shallow-trench isolation.
(3a) fall surperficial SiO with wet etching 2With the SiN layer;
(3b) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer;
(3c) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiN layer of 200nm at substrate surface deposit one layer thickness;
(3d) photoetching collector electrode shallow trench isolation areas goes out the shallow slot that the degree of depth is 300nm at the shallow trench isolation areas dry etching;
(3e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 800 ℃ 2, form the collector electrode shallow-trench isolation.
Step 4, the preparation of base stage shallow-trench isolation.
(4a) fall surperficial SiO with wet etching 2With the SiN layer;
(4b) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer;
(4c) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiN layer of 200nm at substrate surface deposit one layer thickness;
(4d) photoetching base stage shallow trench isolation areas goes out the shallow slot that the degree of depth is 325nm at the shallow trench isolation areas dry etching;
(4e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 800 ℃ 2, form the base stage shallow-trench isolation.
Step 5, SiGe HBT forms.
(5a) fall surperficial SiO with wet etching 2With the SiN layer;
(5b) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiO of 500nm at substrate surface deposit one layer thickness 2Layer;
(5c) photoetching base region carries out p type impurity to this zone and injects, and making the contact zone doping content is 1 * 10 20Cm -3, form base stage;
(5d) photoetching emitter region is carried out N type impurity to this zone and is injected, and making doping content is 5 * 10 17Cm -3, form the emitter region;
(5e) photoetching collector region, and utilize the method for chemico-mechanical polishing (CMP), remove intrinsic Si layer and the intrinsic Poly-Si layer of collector region, the injection of N type impurity is carried out in this zone, making collector electrode contact zone doping content is 1 * 10 20Cm -3, form collector electrode;
(5f) to substrate under 1100 ℃ of temperature, annealing 15s carries out impurity activation, forms SiGe HBT.
Step 6, the preparation of MOS epitaxial material.
(6a) photoetching nmos device active area utilizes dry etch process, etches the deep trouth that the degree of depth is 3 μ m at the nmos device active area;
(6b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the N type Si epitaxial loayer of 2.6 μ m at nmos device active area selective growth thickness, and doping content is 5 * 10 19Cm -3, as the nmos device drain region;
(6c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the N type strain SiGe layer of 5nm at nmos device active area selective growth thickness, and doping content is 5 * 10 17Cm -3, the Ge component is 10%, as a N type lightly-doped source drain structure (N-LDD) layer of nmos device;
(6d) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the P type strain SiGe layer of 45nm at nmos device active area selective growth thickness, and doping content is 5 * 10 16Cm -3, the Ge component is a Gradient distribution, and lower floor is 10%, and the upper strata is 30%, as the nmos device channel region;
(6e) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the N type strain SiGe layer of 5nm at nmos device active area selective growth thickness, and doping content is 5 * 10 17Cm -3, the Ge component is 30%, as the 2nd N type lightly-doped source drain structure (N-LDD) layer of nmos device;
(6f) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the N type Si layer of 400nm at nmos device active area selective growth thickness, and doping content is 5 * 10 19Cm -3, as the nmos device source region;
(6g) utilize the method for chemical vapor deposition (CVD), at 600 ℃, at substrate surface deposit one deck SiO 2
(6h) photoetching PMOS device active region etches the shallow slot that the degree of depth is 100nm at the PMOS device active region;
(6i) utilize the method for chemical vapor deposition (CVD), at 600 ℃, mix in PMOS device area growth one deck N type, doping content is 5 * 10 16Cm -3, thickness is the Si epitaxial loayer of 80nm, regrowth one N type strain SiGe layer, and doping content is 5 * 10 16Cm -3, the Ge component is 10%, thickness is 20nm;
(6j) utilize the method for chemical vapor deposition (CVD), at 600 ℃, at PMOS device active region selective growth one intrinsic relaxation Si cap layer, thickness is 5nm, forms the PMOS device active region.
Step 7, nmos device are leaked and are connected preparation.
(7a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at nmos device surfaces of active regions deposit one deck SiO 2And layer of sin, form the barrier layer;
(7b) the photoetching nmos device leaks groove, utilizes dry etch process, and etching the degree of depth is the leakage groove of 0.6 μ m;
(7c) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one deck SiO 2, forming nmos device and leak the trenched side-wall isolation, dry etching falls the SiO on surface 2, keep the SiO that leaks trenched side-wall 2
(7d) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is 1 * 10 in substrate surface deposit doping content 20Cm -3N type Ploy-Si, nmos device is leaked groove fills up;
(7e) utilize chemico-mechanical polishing (CMP) method, remove the unnecessary Ploy-Si of substrate surface, form nmos device and leak the bonding pad;
(7f) utilize wet etching, etch away the layer SiO on surface 2And SiN.
Step 8, nmos device forms.
(8a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at nmos device surfaces of active regions deposit one deck SiO 2And layer of sin, form the barrier layer once more;
(8b) photoetching nmos device grid window utilizes dry etch process, etches the gate groove that the degree of depth is 0.6 μ m;
(8c) utilizing atomic layer chemical vapour deposition (ALCVD) method, at 300 ℃, is the HfO of 5nm at substrate surface deposit one layer thickness 2, form the nmos device gate dielectric layer;
(8d) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is 1 * 10 in substrate surface deposit doping content 20Cm -3N type Poly-Si, the nmos device gate groove is filled up;
(8e) get rid of nmos device gate groove surperficial part Poly-Si and HfO again 2Layer forms nmos device grid, source region, finally forms nmos device;
(8f) utilize wet etching, etch away the SiO on surface 2With the SiN layer.
Step 9, preparation is leaked in empty grid of PMOS device and source.
(9a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at nmos device surfaces of active regions deposit one deck SiO 2
(9b) photoetching PMOS device active region utilizes chemical vapor deposition (CVD) method, at 600 ℃, is the SiO of 10nm at substrate surface deposit one layer thickness 2
(9c) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is the Poly-Si of 200nm at substrate surface deposit one layer thickness;
(9d) photoetching Poly-Si and SiO 2, form the empty grid of PMOS device;
(9e) the PMOS device is carried out P type ion and inject, forming doping content is 1 * 10 18Cm -3P type lightly-doped source drain structure (P-LDD);
(9f) utilize chemical vapor deposition (CVD) method, at 600 ℃, deposit one layer thickness is the SiO of 3nm on substrate surface 2, dry etching falls the SiO on the substrate surface 2, the SiO of reservation Ploy-Si sidewall 2, form PMOS device gate electrode side wall;
(9g) the PMOS device active region is carried out P type ion and inject, autoregistration generates the source region and the drain region of PMOS device, makes the source-drain area doping content reach 5 * 10 19Cm -3
Step 10, the PMOS device forms.
(10a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit SiO 2Layer with chemico-mechanical polishing (CMP) method flat surface, is used dry etch process etching surface SiO again 2To empty grid upper surface, expose empty grid;
(10b) the empty grid of wet etching form a groove at the gate electrode place;
(10c) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one deck SiON, thickness is 5nm;
(10d) with physical vapor deposition (PVD) deposit W-TiN composite grid, (CMP) removes surface metal with chemico-mechanical polishing;
(10e) with the stop layer of W-TiN composite grid, thereby form grid, finally form the PMOS device as chemico-mechanical polishing (CMP).
Step 11 constitutes the BiCMOS integrated circuit.
(11a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit SiO 2Layer;
(11b) lithography fair lead;
(11c) metallization;
(11d) splash-proofing sputtering metal, photoetching lead-in wire, formation MOS device conducting channel are that the strain SiGe of 45nm returns type channel SOI BiCMOS integrated device and circuit.
Embodiment 2: the preparation conducting channel is that the strain SiGe of 30nm returns type channel SOI BiCMOS integrated device and circuit, and concrete steps are following:
Step 1, the epitaxial material preparation.
(1a) choose the SOI substrate slice, this substrate lower layer support material is Si, and the intermediate layer is SiO 2, thickness is 350nm, upper layer of material is that doping content is 5 * 10 16Cm -3N type Si, thickness is 120nm;
(1b) utilize the method for chemical vapor deposition (CVD), at 700 ℃, growth one layer thickness is the N type epitaxy Si layer of 250nm on the Si material of upper strata, and as collector region, this layer doping content is 5 * 10 16Cm -3
(1c) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the SiO of 240nm at substrate surface deposit one layer thickness 2Layer;
(1d) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the SiN layer of 150nm at substrate surface deposit one layer thickness;
(1e) the photoetching base utilizes dry etching, and etching the degree of depth is the zone, base of 200nm;
(1f) utilize the method for chemical vapor deposition (CVD), at 700 ℃, growth one layer thickness is the SiGe layer of 40nm on substrate, and as the base, this layer Ge component is 20%, and doping content is 1 * 10 19Cm -3
(1g) utilize the method for chemical vapor deposition (CVD), at 700 ℃, the unadulterated intrinsic Si layer of growth one layer thickness 15nm on substrate;
(1h) utilize the method for chemical vapor deposition (CVD), at 700 ℃, the unadulterated intrinsic Poly-Si layer of growth one layer thickness 240nm on substrate.
Step 2, the preparation of device deep trench isolation.
(2a) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the SiO of 240nm at substrate surface deposit one layer thickness 2Layer;
(2b) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the SiN layer of 150nm at substrate surface deposit one layer thickness;
(2c) deep trench isolation zone between the lithographic device, dry etching goes out the deep trouth that the degree of depth is 5 μ m in the deep trench isolation zone;
(2d) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 700 ℃ 2, form the device deep trench isolation.
Step 3, the preparation of collector electrode shallow-trench isolation.
(3a) fall surperficial SiO with wet etching 2With the SiN layer;
(3b) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the SiO of 240nm at substrate surface deposit one layer thickness 2Layer;
(3c) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the SiN layer of 150nm at substrate surface deposit one layer thickness;
(3d) photoetching collector electrode shallow trench isolation areas goes out the shallow slot that the degree of depth is 240nm at the shallow trench isolation areas dry etching;
(3e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 700 ℃ 2, form the collector electrode shallow-trench isolation.
Step 4, the preparation of base stage shallow-trench isolation.
(4a) fall surperficial SiO with wet etching 2With the SiN layer;
(4b) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the SiO of 240nm at substrate surface deposit one layer thickness 2Layer;
(4c) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the SiN layer of 150nm at substrate surface deposit one layer thickness;
(4d) photoetching base stage shallow trench isolation areas goes out the shallow slot that the degree of depth is 260nm at the shallow trench isolation areas dry etching;
(4e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 700 ℃ 2, form the base stage shallow-trench isolation.
Step 5, SiGe HBT forms.
(5a) fall surperficial SiO with wet etching 2With the SiN layer;
(5b) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the SiO of 400nm at substrate surface deposit one layer thickness 2Layer;
(5c) photoetching base region carries out p type impurity to this zone and injects, and making the contact zone doping content is 5 * 10 19Cm -3, form base stage;
(5d) photoetching emitter region is carried out N type impurity to this zone and is injected, and making doping content is 3 * 10 17Cm -3, form the emitter region;
(5e) photoetching collector region, and utilize the method for chemico-mechanical polishing (CMP), remove intrinsic Si layer and the intrinsic Poly-Si layer of collector region, the injection of N type impurity is carried out in this zone, making collector electrode contact zone doping content is 5 * 10 19Cm -3, form collector electrode;
(5f) to substrate under 1000 ℃ of temperature, annealing 60s carries out impurity activation, forms SiGe HBT.
Step 6, the preparation of MOS epitaxial material.
(6a) photoetching nmos device active area utilizes dry etch process, etches the deep trouth that the degree of depth is 2.4 μ m at the nmos device active area;
(6b) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the N type Si epitaxial loayer of 2.1 μ m at nmos device active area selective growth thickness, and doping content is 8 * 10 19Cm -3, as the nmos device drain region;
(6c) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the N type strain SiGe layer of 4nm at nmos device active area selective growth thickness, and doping content is 3 * 10 18Cm -3, the Ge component is 10%, as a N type lightly-doped source drain structure (N-LDD) layer of nmos device;
(6d) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the P type strain SiGe layer of 30nm at nmos device active area selective growth thickness, and doping content is 1 * 10 17Cm -3, the Ge component is a Gradient distribution, and lower floor is 10%, and the upper strata is 20%, as the nmos device channel region;
(6e) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the N type strain SiGe layer of 4nm at nmos device active area selective growth thickness, and doping content is 3 * 10 18Cm -3, the Ge component is 20%, as the 2nd N type lightly-doped source drain structure (N-LDD) layer of nmos device;
(6f) utilizing the method for chemical vapor deposition (CVD), at 700 ℃, is the N type Si layer of 300nm at nmos device active area selective growth thickness, and doping content is 8 * 10 19Cm -3, as the nmos device source region;
(6g) utilize the method for chemical vapor deposition (CVD), at 700 ℃, at substrate surface deposit one deck SiO 2
(6h) photoetching PMOS device active region etches the shallow slot that the degree of depth is 100nm at the PMOS device active region;
(6i) utilize the method for chemical vapor deposition (CVD), at 700 ℃, mix in PMOS device area growth one deck N type, doping content is 1 * 10 17Cm -3, thickness is the Si epitaxial loayer of 80nm, regrowth one N type strain SiGe layer, and doping content is 1 * 10 17Cm -3, the Ge component is 20%, thickness is 15nm;
(6j) utilize the method for chemical vapor deposition (CVD), at 700 ℃, at PMOS device active region selective growth one intrinsic relaxation Si cap layer, thickness is 4nm, forms the PMOS device active region.
Step 7, nmos device are leaked and are connected preparation.
(7a) utilize chemical vapor deposition (CVD) method, at 700 ℃, at nmos device surfaces of active regions deposit one deck SiO 2And layer of sin, form the barrier layer;
(7b) the photoetching nmos device leaks groove, utilizes dry etch process, and etching the degree of depth is the leakage groove of 0.5 μ m;
(7c) utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface deposit one deck SiO 2, forming nmos device and leak the trenched side-wall isolation, dry etching falls the SiO on surface 2, keep the SiO that leaks trenched side-wall 2
(7d) utilizing chemical vapor deposition (CVD) method, at 700 ℃, is 3 * 10 in substrate surface deposit doping content 20Cm -3N type Ploy-Si, nmos device is leaked groove fills up;
(7e) utilize chemico-mechanical polishing (CMP) method, remove the unnecessary Ploy-Si of substrate surface, form nmos device and leak the bonding pad;
(7f) utilize wet etching, etch away the layer SiO on surface 2And SiN.
Step 8, nmos device forms.
(8a) utilize chemical vapor deposition (CVD) method, at 700 ℃, at nmos device surfaces of active regions deposit one deck SiO 2And layer of sin, form the barrier layer once more;
(8b) photoetching nmos device grid window utilizes dry etch process, etches the gate groove that the degree of depth is 0.5 μ m;
(8c) utilizing atomic layer chemical vapour deposition (ALCVD) method, at 350 ℃, is the HfO of 6nm at substrate surface deposit one layer thickness 2, form the nmos device gate dielectric layer;
(8d) utilizing chemical vapor deposition (CVD) method, at 700 ℃, is 3 * 10 in substrate surface deposit doping content 20Cm -3N type Poly-Si, the nmos device gate groove is filled up;
(8e) get rid of nmos device gate groove surperficial part Poly-Si and HfO again 2Layer forms nmos device grid, source region, finally forms nmos device;
(8f) utilize wet etching, etch away the SiO on surface 2With the SiN layer.
Step 9, preparation is leaked in empty grid of PMOS device and source.
(9a) utilize chemical vapor deposition (CVD) method, at 700 ℃, at nmos device surfaces of active regions deposit one deck SiO 2
(9b) photoetching PMOS device active region utilizes chemical vapor deposition (CVD) method, at 700 ℃, is the SiO of 12nm at substrate surface deposit one layer thickness 2
(9c) utilizing chemical vapor deposition (CVD) method, at 700 ℃, is the Poly-Si of 240nm at substrate surface deposit one layer thickness;
(9d) photoetching Poly-Si and SiO 2, form the empty grid of PMOS device;
(9e) the PMOS device is carried out P type ion and inject, forming doping content is 3 * 10 18Cm -3P type lightly-doped source drain structure (P-LDD);
(9f) utilize chemical vapor deposition (CVD) method, at 700 ℃, deposit one layer thickness is the SiO of 4nm on substrate surface 2, dry etching falls the SiO on the substrate surface 2, the SiO of reservation Ploy-Si sidewall 2, form PMOS device gate electrode side wall;
(9g) the PMOS device active region is carried out P type ion and inject, autoregistration generates the source region and the drain region of PMOS device, makes the source-drain area doping content reach 8 * 10 19Cm -3
Step 10, the PMOS device forms.
(10a) utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface deposit SiO 2Layer with chemico-mechanical polishing (CMP) method flat surface, is used dry etch process etching surface SiO again 2To empty grid upper surface, expose empty grid;
(10b) the empty grid of wet etching form a groove at the gate electrode place;
(10c) utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface deposit one deck SiON, thickness is 3nm;
(10d) with physical vapor deposition (PVD) deposit W-TiN composite grid, (CMP) removes surface metal with chemico-mechanical polishing;
(10e) with the stop layer of W-TiN composite grid, thereby form grid, finally form the PMOS device as chemico-mechanical polishing (CMP).
Step 11 constitutes the BiCMOS integrated circuit.
(11a) utilize chemical vapor deposition (CVD) method, at 700 ℃, at substrate surface deposit SiO 2Layer;
(11b) lithography fair lead;
(11c) metallization;
(11d) splash-proofing sputtering metal, photoetching lead-in wire, formation MOS device conducting channel are that the strain SiGe of 30nm returns type channel SOI BiCMOS integrated device and circuit.
Embodiment 3: the preparation conducting channel is that the strain SiGe of 22nm returns type channel SOI BiCMOS integrated device and circuit, and concrete steps are following:
Step 1, the epitaxial material preparation.
(1a) choose the SOI substrate slice, this substrate lower layer support material is Si, and the intermediate layer is SiO 2, thickness is 300nm, upper layer of material is that doping content is 1 * 10 16Cm -3N type Si, thickness is 100nm;
(1b) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the N type epitaxy Si layer of 250nm on the Si material of upper strata, and as collector region, this layer doping content is 1 * 10 16Cm -3
(1c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 200nm at substrate surface deposit one layer thickness 2Layer;
(1d) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiN layer of 100nm at substrate surface deposit one layer thickness;
(1e) the photoetching base utilizes dry etching, and etching the degree of depth is the zone, base of 200nm;
(1f) utilize the method for chemical vapor deposition (CVD), at 600 ℃, growth one layer thickness is the SiGe layer of 20nm on substrate, and as the base, this layer Ge component is 15%, and doping content is 5 * 10 18Cm -3
(1g) utilize the method for chemical vapor deposition (CVD), at 600 ℃, the unadulterated intrinsic Si layer of growth one layer thickness 10nm on substrate;
(1h) utilize the method for chemical vapor deposition (CVD), at 600 ℃, the unadulterated intrinsic Poly-Si layer of growth one layer thickness 200nm on substrate.
Step 2, the preparation of device deep trench isolation.
(2a) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 200nm at substrate surface deposit one layer thickness 2Layer;
(2b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiN layer of 100nm at substrate surface deposit one layer thickness;
(2c) deep trench isolation zone between the lithographic device, dry etching goes out the deep trouth that the degree of depth is 5 μ m in the deep trench isolation zone;
(2d) utilize chemical vapor deposition (CVD) method,, in deep trouth, fill SiO at 600 ℃ 2, form the device deep trench isolation.
Step 3, the preparation of collector electrode shallow-trench isolation.
(3a) fall surperficial SiO with wet etching 2With the SiN layer;
(3b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 200nm at substrate surface deposit one layer thickness 2Layer;
(3c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiN layer of 100nm at substrate surface deposit one layer thickness;
(3d) photoetching collector electrode shallow trench isolation areas goes out the shallow slot that the degree of depth is 180nm at the shallow trench isolation areas dry etching;
(3e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 600 ℃ 2, form the collector electrode shallow-trench isolation.
Step 4, the preparation of base stage shallow-trench isolation.
(4a) fall surperficial SiO with wet etching 2With the SiN layer;
(4b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 200nm at substrate surface deposit one layer thickness 2Layer;
(4c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiN layer of 100nm at substrate surface deposit one layer thickness;
(4d) photoetching collector region shallow trench isolation areas goes out the shallow slot that the degree of depth is 215nm at the shallow trench isolation areas dry etching;
(4e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 600 ℃ 2, form the base stage shallow-trench isolation.
Step 5, SiGe HBT forms.
(5a) fall surperficial SiO with wet etching 2With the SiN layer;
(5b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer;
(5c) photoetching base region carries out p type impurity to this zone and injects, and making the contact zone doping content is 1 * 10 19Cm -3, form base stage;
(5d) photoetching emitter region is carried out N type impurity to this zone and is injected, and making doping content is 1 * 10 17Cm -3, form the emitter region;
(5e) photoetching collector region, and utilize the method for chemico-mechanical polishing (CMP), remove intrinsic Si layer and the intrinsic Poly-Si layer of collector region, the injection of N type impurity is carried out in this zone, making collector electrode contact zone doping content is 1 * 10 19Cm -3, form collector electrode;
(5f) to substrate under 950 ℃ of temperature, annealing 120s carries out impurity activation, forms SiGe HBT.
Step 6, the preparation of MOS epitaxial material.
(6a) photoetching nmos device active area utilizes dry etch process, etches the deep trouth that the degree of depth is 2 μ m at the nmos device active area;
(6b) utilizing the method for chemical vapor deposition (CVD), at 750 ℃, is the N type Si epitaxial loayer of 1.8 μ m at nmos device active area selective growth thickness, and doping content is 1 * 10 20Cm -3, as the nmos device drain region;
(6c) utilizing the method for chemical vapor deposition (CVD), at 750 ℃, is the N type strain SiGe layer of 3nm at nmos device active area selective growth thickness, and doping content is 1 * 10 18Cm -3, the Ge component is 10%, as a N type lightly-doped source drain structure (N-LDD) layer of nmos device;
(6d) utilizing the method for chemical vapor deposition (CVD), at 750 ℃, is the P type strain SiGe layer of 22nm at nmos device active area selective growth thickness, and doping content is 5 * 10 17Cm -3, the Ge component is a Gradient distribution, and lower floor is 10%, and the upper strata is 25%, as the nmos device channel region;
(6e) utilizing the method for chemical vapor deposition (CVD), at 750 ℃, is the N type strain SiGe layer of 3nm at nmos device active area selective growth thickness, and doping content is 1 * 10 18Cm -3, the Ge component is 25%, as the 2nd N type lightly-doped source drain structure (N-LDD) layer of nmos device;
(6f) utilizing the method for chemical vapor deposition (CVD), at 750 ℃, is the N type Si layer of 200nm at nmos device active area selective growth thickness, and doping content is 1 * 10 20Cm -3, as the nmos device source region;
(6g) utilize the method for chemical vapor deposition (CVD), at 780 ℃, at substrate surface deposit one deck SiO 2
(6h) photoetching PMOS device active region etches the shallow slot that the degree of depth is 100nm at the PMOS device active region;
(6i) utilize the method for chemical vapor deposition (CVD), at 750 ℃, mix in PMOS device area growth one deck N type, doping content is 5 * 10 17Cm -3, thickness is the Si epitaxial loayer of 80nm, regenerative growth one N type strain SiGe layer, and doping content is 5 * 10 17Cm -3, the Ge component is 30%, thickness is 10nm;
(6j) utilize the method for chemical vapor deposition (CVD), at 750 ℃, at PMOS device active region selective growth one intrinsic relaxation Si cap layer, thickness is 3nm, forms the PMOS device active region.
Step 7, nmos device are leaked and are connected preparation.
(7a) utilize chemical vapor deposition (CVD) method, at 780 ℃, at nmos device surfaces of active regions deposit one deck SiO 2And layer of sin, form the barrier layer;
(7b) the photoetching nmos device leaks groove, utilizes dry etch process, and etching the degree of depth is the leakage groove of 0.4 μ m;
(7c) utilize chemical vapor deposition (CVD) method, at 780 ℃, at substrate surface deposit one deck SiO 2, forming nmos device and leak the trenched side-wall isolation, dry etching falls the SiO on surface 2, keep the SiO that leaks trenched side-wall 2
(7d) utilizing chemical vapor deposition (CVD) method, at 780 ℃, is 5 * 10 in substrate surface deposit doping content 20Cm -3N type Ploy-Si, nmos device is leaked groove fills up;
(7e) utilize chemico-mechanical polishing (CMP) method, remove the unnecessary Ploy-Si of substrate surface, form nmos device and leak the bonding pad;
(7f) utilize wet etching, etch away the layer SiO on surface 2And SiN.
Step 8, nmos device forms.
(8a) utilize chemical vapor deposition (CVD) method, at 780 ℃, at nmos device surfaces of active regions deposit one deck SiO 2And layer of sin, form the barrier layer once more;
(8b) photoetching nmos device grid window utilizes dry etch process, etches the gate groove that the degree of depth is 0.4 μ m;
(8c) utilizing atomic layer chemical vapour deposition (ALCVD) method, at 400 ℃, is the HfO of 8nm at substrate surface deposit one layer thickness 2, form the nmos device gate dielectric layer;
(8d) utilizing chemical vapor deposition (CVD) method, at 780 ℃, is 5 * 10 in substrate surface deposit doping content 20Cm -3N type Poly-Si, the nmos device gate groove is filled up;
(8e) get rid of nmos device gate groove surperficial part Poly-Si and HfO again 2Layer forms nmos device grid, source region, finally forms nmos device;
(8f) utilize wet etching, etch away the SiO on surface 2With the SiN layer.
Step 9, preparation is leaked in empty grid of PMOS device and source.
(9a) utilize chemical vapor deposition (CVD) method, at 780 ℃, at nmos device surfaces of active regions deposit one deck SiO 2
(9b) photoetching PMOS device active region utilizes chemical vapor deposition (CVD) method, at 780 ℃, is the SiO of 15nm at substrate surface deposit one layer thickness 2
(9c) utilizing chemical vapor deposition (CVD) method, at 780 ℃, is the Poly-Si of 300nm at substrate surface deposit one layer thickness;
(9d) photoetching Poly-Si and SiO 2, form the empty grid of PMOS device;
(9e) the PMOS device is carried out P type ion and inject, forming doping content is 5 * 10 18Cm -3P type lightly-doped source drain structure (P-LDD);
(9f) utilize chemical vapor deposition (CVD) method, at 780 ℃, deposit one layer thickness is the SiO of 3nm on substrate surface 2, dry etching falls the SiO on the substrate surface 2, the SiO of reservation Ploy-Si sidewall 2, form PMOS device gate electrode side wall;
(9g) the PMOS device active region is carried out P type ion and inject, autoregistration generates the source region and the drain region of PMOS device, makes the source-drain area doping content reach 1 * 10 20Cm -3
Step 10, the PMOS device forms.
(10a) utilize chemical vapor deposition (CVD) method, at 780 ℃, at substrate surface deposit SiO 2Layer with chemico-mechanical polishing (CMP) method flat surface, is used dry etch process etching surface SiO again 2To empty grid upper surface, expose empty grid;
(10b) the empty grid of wet etching form a groove at the gate electrode place;
(10c) utilize chemical vapor deposition (CVD) method, at 780 ℃, at substrate surface deposit one deck SiON, thickness is 1.5nm;
(10d) with physical vapor deposition (PVD) deposit W-TiN composite grid, (CMP) removes surface metal with chemico-mechanical polishing;
(10e) with the stop layer of W-TiN composite grid, thereby form grid, finally form the PMOS device as chemico-mechanical polishing (CMP).
Step 11 constitutes the BiCMOS integrated circuit.
(11a) utilize chemical vapor deposition (CVD) method, at 780 ℃, at substrate surface deposit SiO 2Layer;
(11b) lithography fair lead;
(11c) metallization;
(11d) splash-proofing sputtering metal, photoetching lead-in wire, formation MOS device conducting channel are that the strain SiGe of 22nm returns type channel SOI BiCMOS integrated device and circuit.
Strain Si BiCMOS integrated device and preparation method based on self-registered technology that the embodiment of the invention provides have following advantage:
1. the strain SiGe of the present invention's preparation returns in the type channel SOI BiCMOS integrated device, has made full use of the characteristic of each diversity of strain SiGe material stress, introduces compressive strain in the horizontal direction, has improved PMOS device hole mobility; Introduce tensile strain in vertical direction, improved the nmos device electron mobility, therefore, performances such as this device frequency and current driving ability are higher than unidimensional relaxation Si cmos device;
2. the present invention returns in the type channel SOI BiCMOS integrated device process at the preparation strain SiGe; Employing selective epitaxial technology; Respectively at nmos device and PMOS device active region selective growth strain SiGe material; Improve the flexibility of designs, strengthened cmos device and integrated circuit electric property;
3. the strain SiGe of the present invention's preparation returns in the type channel SOI BiCMOS integrated device structure; The channel direction of nmos device is a vertical direction, and raceway groove is the strain SiGe layer of chemical vapor deposition (CVD) method preparation, and the thickness of SiGe layer is the channel length of nmos device; Therefore; In the preparation of nmos device, avoid the photoetching of small size grid, reduced process complexity, reduced cost;
4. the strain SiGe of the present invention preparation raceway groove that returns nmos device in the type channel SOI BiCMOS integrated device structure is back type; Promptly grid can be controlled raceway groove on four sides in groove; Therefore, this device has increased the width of raceway groove in limited zone, thereby has improved the current driving ability of device; Increase the integrated level of integrated circuit, reduced the manufacturing cost of lsi unit area;
5. the strain SiGe of the present invention preparation returns that nmos device raceway groove Ge component changes in gradient in the type channel SOI BiCMOS integrated device structure; Therefore can produce the built-in field that an accelerated electron transports at channel direction; Strengthen the carrier transport ability of raceway groove, thereby improved the frequency characteristic and the current driving ability of strain SiGe nmos device;
6. the strain SiGe of the present invention preparation returns the HfO that nmos device in the type channel SOI BiCMOS integrated device structure has adopted high K value 2As gate medium, improved the grid-control ability of nmos device, strengthened the electric property of nmos device;
7. the strain SiGe of the present invention preparation returns that the PMOS device is a quantum well devices in the type channel SOI BiCMOS integrated device structure; Be that the strain SiGe channel layer is between Si cap layer and the body Si layer; Compare with the surface channel device; This device can reduce the channel interface scattering effectively, has improved the device electrology characteristic; Simultaneously, SQW can make the problem in the hot electron injection grid medium improve, and has increased the reliability of device and circuit;
8. the strain SiGe of the present invention's preparation returns in the type channel SOI BiCMOS integrated device structure, and the PMOS device adopts SiON to replace traditional pure SiO 2Do gate medium, not only strengthened the reliability of device, and utilize the variation of gate medium dielectric constant, improved the grid-control ability of device;
9. to return the maximum temperature that relates in the type channel SOI BiCMOS integrated device process be 800 ℃ at the preparation strain SiGe in the present invention; Be lower than the technological temperature that causes strain SiGe channel stress relaxation; Therefore this preparation method can keep strain SiGe channel stress effectively, improves the performance of integrated circuit;
10. the present invention prepares strain SiGe and returns in the type channel SOI BiCMOS integrated device process; The PMOS device has adopted metal gate mosaic technology (damascene process) preparation gate electrode; This gate electrode is a metal W-TiN composite construction, because the TiN of lower floor and strain Si and strain SiGe material work function difference are less, has improved electric properties of devices; The W on upper strata then can reduce the resistance of gate electrode, has realized the optimization of gate electrode;
11. the strain SiGe of the present invention's preparation returns emitter, the base stage of SiGe HBT device in the type channel SOI BiCMOS integrated device and adopts polycrystalline; Polycrystalline can partly be produced on above the oxide layer; Reduce the area of device active region, thereby reduced device size, improved the integrated level of circuit.
The above is merely preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of within spirit of the present invention and principle, being done, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.

Claims (10)

1. a strain SiGe returns type channel SOI BiCMOS integrated device, it is characterized in that, said BiCMOS device adopts SOI two polycrystal SiGe HBT device, strain SiGe vertical-channel nmos device and strain SiGe planar channeling PMOS devices.
2. strain SiGe according to claim 1 returns type channel SOI BiCMOS integrated device, it is characterized in that, the nmos device conducting channel is the strain SiGe material, is tensile strain along channel direction.
3. strain SiGe according to claim 1 returns type channel SOI BiCMOS integrated device, it is characterized in that, PMOS device conducting channel is the strain SiGe material, is compressive strain along channel direction.
4. strain SiGe according to claim 1 returns type channel SOI BiCMOS integrated device, it is characterized in that, the emitter of said SiGe HBT device adopts polysilicon to contact with base stage.
5. strain SiGe according to claim 1 returns type channel SOI BiCMOS integrated device, it is characterized in that, the base of said SiGe HBT device is the strain SiGe material.
6. strain SiGe according to claim 1 returns type channel SOI BiCMOS integrated device, it is characterized in that, SiGe HBT device adopts the SOI substrate preparation.
7. a strain SiGe returns the preparation method of type channel SOI BiCMOS integrated device, it is characterized in that this preparation method comprises the steps:
The first step, to choose oxidated layer thickness be 300～400nm, and upper strata Si thickness is 100～150nm, and N type doping content is 1 * 10 16～1 * 10 17Cm -3The SOI substrate slice;
Second goes on foot, utilizes the method for chemical vapor deposition (CVD), at 600～750 ℃, and growth Si epitaxial loayer on substrate, thickness is 250～300nm, and the N type mixes, and doping content is 1 * 10 16～1 * 10 17Cm -3, as collector region;
The 3rd goes on foot, utilizes the method for chemical vapor deposition (CVD), at 600～800 ℃, is the SiO of 200 ~ 300nm at substrate surface deposit one layer thickness 2A layer and a layer thickness are the SiN layer of 100 ~ 200nm; The photoetching base utilizes dry etching, etches the degree of depth and be the zone, base of 200nm, and at substrate surface growth trilaminate material: ground floor is the SiGe layer, and the Ge component is 15 ~ 25%, and thickness is 20 ~ 60nm, and the P type mixes, and doping content is 5 * 10 18~ 5 * 10 19Cm -3, as the base; The second layer is unadulterated intrinsic Si layer, and thickness is 10 ~ 20nm; The 3rd layer is unadulterated intrinsic Poly-Si layer, and thickness is 200～300nm, as base stage and emitter region;
The 4th goes on foot, utilizes the method for chemical vapor deposition (CVD), at 600～800 ℃, is the SiO of 200 ~ 300nm at substrate surface deposit one layer thickness 2A layer and a layer thickness are the SiN layer of 100 ~ 200nm; Deep trench isolation zone between lithographic device, dry etching goes out the deep trouth that the degree of depth is 5 μ m in the deep trench isolation zone, utilizes chemical vapor deposition (CVD) method, at 600～800 ℃, in deep trouth, fills SiO 2
The 5th goes on foot, falls with wet etching the SiO on surface 2With the SiN layer, utilize the method for chemical vapor deposition (CVD) again, at 600～800 ℃, be the SiO of 200 ~ 300nm at substrate surface deposit one layer thickness 2A layer and a layer thickness are the SiN layer of 100 ~ 200nm; Photoetching collector region shallow trench isolation areas goes out the shallow slot that the degree of depth is 180 ~ 300nm at the shallow trench isolation areas dry etching, utilizes chemical vapor deposition (CVD) method, at 600～800 ℃, in shallow slot, fills SiO 2
The 6th goes on foot, falls with wet etching the SiO on surface 2With the SiN layer, utilize the method for chemical vapor deposition (CVD), at 600～800 ℃, be the SiO of 300 ~ 500nm at substrate surface deposit one layer thickness 2Layer; The photoetching base region carries out p type impurity to this zone and injects, and making base stage contact zone doping content is 1 * 10 19～1 * 10 20Cm -3, form the base stage contact area;
The 7th step, photoetching emitting area carry out N type impurity to this zone and inject, and making doping content is 1 * 10 17～5 * 10 17Cm -3, form the emitter region;
The 8th step, photoetching collector region, and utilize the method for chemico-mechanical polishing (CMP), remove intrinsic Si layer and the intrinsic Poly-Si layer of collector region, the injection of N type impurity is carried out in this zone, making collector electrode contact zone doping content is 1 * 10 19～1 * 10 20Cm -3, form collector contact area; And to substrate under 950～1100 ℃ of temperature, annealing 15～120s carries out impurity activation, forms SiGe HBT device;
The 9th step, photoetching nmos device active area; Utilize dry etch process, etch the deep trouth that the degree of depth is 2～3 μ m, oxide layer is carved pass through at the nmos device active area; Utilize the method for chemical vapor deposition (CVD); At 600～750 ℃, five layer materials of in deep trouth, growing continuously: ground floor is that thickness is the N type Si epitaxial loayer of 1.8～2.6 μ m, and doping content is 5 * 10 19～1 * 10 20Cm -3, as the nmos device drain region; The second layer is that thickness is the N type strain SiGe layer of 3～5nm, and doping content is 1～5 * 10 18Cm -3, the Ge component is 10%, as a N type lightly-doped source drain structure (N-LDD) layer of nmos device; The 3rd layer is that thickness is the P type strain SiGe layer of 22～45nm, and doping content is 5 * 10 16～5 * 10 17Cm -3, the Ge component is a Gradient distribution, and lower floor is 10%, and the upper strata is 20～30% Gradient distribution, as the nmos device channel region; The 4th layer is that thickness is the N type strain SiGe layer of 3～5nm, and doping content is 1～5 * 10 18Cm -3, the Ge component is for being 20～30%, as the 2nd N type lightly-doped source drain structure (N-LDD) layer of nmos device; Layer 5 is that thickness is the N type Si layer of 200～400nm, and doping content is 5 * 10 19～1 * 10 20Cm -3, as the nmos device source region;
The tenth goes on foot, utilizes the method for chemical vapor deposition (CVD), at 600～780 ℃, at substrate surface deposit one deck SiO 2, photoetching PMOS device active region etches the shallow slot that the degree of depth is 100nm at the PMOS device active region, utilizes the method for chemical vapor deposition (CVD), at 600～750 ℃, mixes in PMOS device area growth one deck N type, and doping content is 5 * 10 16～5 * 10 17Cm -3, thickness is the Si epitaxial loayer of 80nm, regrowth one N type strain SiGe layer, and the Ge component is 10～30%, thickness is 10～20nm, the intrinsic relaxation Si cap layer of growing at last, thickness is 3～5nm, forms the PMOS device active region;
The 11 the step, utilize chemical vapor deposition (CVD) method, at 600～780 ℃, at substrate surface deposit one deck SiO 2And layer of sin, form the barrier layer; The photoetching nmos device leaks groove, utilizes dry etch process, and etching the degree of depth is the leakage groove of 0.4～0.6 μ m; Utilize chemical vapor deposition (CVD) method, at 600～780 ℃, at substrate surface deposit one deck SiO 2, forming nmos device and leak the trenched side-wall isolation, dry etching falls the SiO on surface 2, keep the SiO that leaks trenched side-wall 2, utilize chemical vapor deposition (CVD) method, at 600～780 ℃, the deposit doping content is 1～5 * 10 20Cm -3N type Ploy-Si, groove is filled up, chemico-mechanical polishing (CMP) method is removed the unnecessary Ploy-Si of substrate surface, forms nmos device and leaks the bonding pad; Utilize wet etching, etch away the layer SiO on surface 2And SiN;
The 12 the step, utilize chemical vapor deposition (CVD) method, at 600～780 ℃, at substrate surface deposit one deck SiO 2And layer of sin, form the barrier layer once more; Photoetching nmos device grid window utilizes dry etch process, etches the gate groove that the degree of depth is 0.4～0.6 μ m; Utilizing atomic layer chemical vapour deposition (ALCVD) method, at 300～400 ℃, is the HfO of 5～8nm at substrate surface deposit one layer thickness 2, form the nmos device gate dielectric layer, utilize chemical vapor deposition (CVD) method then, at 600～780 ℃, be 1～5 * 10 in substrate surface deposit doping content 20Cm -3N type Poly-Si, the nmos device gate groove is filled up, get rid of the nmos device gate groove again with outer surface part Poly-Si and HfO 2, form nmos device grid, source region, finally form nmos device; Utilize wet etching, etch away the layer SiO on surface 2And SiN;
The 13 the step, utilize chemical vapor deposition (CVD) method, at 600～780 ℃, at substrate surface deposit one deck SiO 2, photoetching PMOS device active region utilizes chemical vapor deposition (CVD) method, at 600～780 ℃, is the SiO of 10～15nm at substrate surface deposit one layer thickness 2With a layer thickness be the Poly-Si of 200～300nm, photoetching Poly-Si and SiO 2, form the empty grid of PMOS device; The PMOS device is carried out P type ion inject, forming doping content is 1～5 * 10 18Cm -3P type lightly-doped source drain structure (P-LDD);
The 14 the step, utilize chemical vapor deposition (CVD) method, at 600～780 ℃, deposit one layer thickness is the SiO of 3～5nm on substrate surface 2, dry etching falls the SiO on the substrate surface 2, the SiO of reservation Ploy-Si sidewall 2, form PMOS device gate electrode side wall; Again the PMOS device active region is carried out P type ion and inject, autoregistration generates the source region and the drain region of PMOS device, makes the source-drain area doping content reach 5 * 10 19～1 * 10 20Cm -3
The 15 the step, utilize chemical vapor deposition (CVD) method, at 600～780 ℃, at substrate surface deposit SiO 2Layer with chemico-mechanical polishing (CMP) method flat surface, is used dry etch process etching surface SiO again 2To empty grid upper surface, expose empty grid; The empty grid of wet etching form a groove at the gate electrode place; Utilize chemical vapor deposition (CVD) method, at 600～780 ℃, at substrate surface deposit one deck SiON, thickness is 1.5～5nm; With physical vapor deposition (PVD) deposit W-TiN composite grid, (CMP) removes surface metal with chemico-mechanical polishing, with the stop layer of W-TiN composite grid as chemico-mechanical polishing (CMP), thereby forms grid, finally forms the PMOS device;
The 16 the step, utilize chemical vapor deposition (CVD) method, at 600～780 ℃, at substrate surface deposit SiO 2Layer, lithography fair lead, metallization, splash-proofing sputtering metal, photoetching lead-in wire, formation MOS device conducting channel are that the strain SiGe of 22～45nm returns type channel SOI BiCMOS integrated device.
8. method according to claim 7 is characterized in that, the nmos device channel length is confirmed according to the P type strain SiGe layer thickness of the 9th step deposit, got 22～45nm; The PMOS device channel length is controlled by photoetching process.
9. preparation method according to claim 7 is characterized in that, SiGe HBT device base thickness decides according to the epitaxy layer thickness of the 3rd step SiGe, gets 20～60nm.
10. a strain SiGe returns the preparation method of type channel SOI BiCMOS integrated circuit, it is characterized in that this preparation method comprises the steps:
Step 1, the implementation method of epitaxial material preparation is:
(1a) choose the SOI substrate slice, this substrate lower layer support material is Si, and the intermediate layer is SiO 2, thickness is 400nm, upper layer of material is that doping content is 1 * 10 17Cm -3N type Si, thickness is 150nm;
(1b) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the N type epitaxy Si layer of 300nm on the Si material of upper strata, and as collector region, this layer doping content is 1 * 10 17Cm -3
(1c) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer;
(1d) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiN layer of 200nm at substrate surface deposit one layer thickness;
(1e) the photoetching base utilizes dry etching, and etching the degree of depth is the zone, base of 200nm;
(1f) utilize the method for chemical vapor deposition (CVD), at 750 ℃, growth one layer thickness is the SiGe layer of 60nm on substrate, and as the base, this layer Ge component is 25%, and doping content is 5 * 10 19Cm -3
(1g) utilize the method for chemical vapor deposition (CVD), at 750 ℃, the unadulterated intrinsic Si layer of growth one layer thickness 20nm on substrate;
(1h) utilize the method for chemical vapor deposition (CVD), at 750 ℃, the unadulterated intrinsic Poly-Si layer of growth one layer thickness 300nm on substrate;
Step 2, the implementation method of device deep trench isolation preparation is:
(2a) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer;
(2b) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiN layer of 200nm at substrate surface deposit one layer thickness;
(2c) deep trench isolation zone between the lithographic device, dry etching goes out the deep trouth that the degree of depth is 5 μ m in the deep trench isolation zone;
(2d) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 800 ℃ 2, form the device deep trench isolation;
Step 3, the implementation method of collector electrode shallow-trench isolation preparation is:
(3a) fall surperficial SiO with wet etching 2With the SiN layer;
(3b) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer;
(3c) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiN layer of 200nm at substrate surface deposit one layer thickness;
(3d) photoetching collector electrode shallow trench isolation areas goes out the shallow slot that the degree of depth is 300nm at the shallow trench isolation areas dry etching;
(3e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 800 ℃ 2, form the collector electrode shallow-trench isolation;
Step 4, the implementation method of base stage shallow-trench isolation preparation is:
(4a) fall surperficial SiO with wet etching 2With the SiN layer;
(4b) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiO of 300nm at substrate surface deposit one layer thickness 2Layer;
(4c) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiN layer of 200nm at substrate surface deposit one layer thickness;
(4d) photoetching base stage shallow trench isolation areas goes out the shallow slot that the degree of depth is 325nm at the shallow trench isolation areas dry etching;
(4e) utilize chemical vapor deposition (CVD) method,, in shallow slot, fill SiO at 800 ℃ 2, form the base stage shallow-trench isolation;
Step 5, SiGe HBT forms the implementation method that is equipped with and is:
(5a) fall surperficial SiO with wet etching 2With the SiN layer;
(5b) utilizing the method for chemical vapor deposition (CVD), at 800 ℃, is the SiO of 500nm at substrate surface deposit one layer thickness 2Layer;
(5c) photoetching base region carries out p type impurity to this zone and injects, and making the contact zone doping content is 1 * 10 20Cm -3, form base stage;
(5d) photoetching emitter region is carried out N type impurity to this zone and is injected, and making doping content is 5 * 10 17Cm -3, form the emitter region;
(5e) photoetching collector region, and utilize the method for chemico-mechanical polishing (CMP), remove intrinsic Si layer and the intrinsic Poly-Si layer of collector region, the injection of N type impurity is carried out in this zone, making collector electrode contact zone doping content is 1 * 10 20Cm -3, form collector electrode;
(5f) to substrate under 1100 ℃ of temperature, annealing 15s carries out impurity activation, forms SiGe HBT;
Step 6, the implementation method of MOS epitaxial material preparation is:
(6a) photoetching nmos device active area utilizes dry etch process, etches the deep trouth that the degree of depth is 3 μ m at the nmos device active area;
(6b) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the N type Si epitaxial loayer of 2.6 μ m at nmos device active area selective growth thickness, and doping content is 5 * 10 19Cm -3, as the nmos device drain region;
(6c) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the N type strain SiGe layer of 5nm at nmos device active area selective growth thickness, and doping content is 5 * 10 17Cm -3, the Ge component is 10%, as a N type lightly-doped source drain structure (N-LDD) layer of nmos device;
(6d) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the P type strain SiGe layer of 45nm at nmos device active area selective growth thickness, and doping content is 5 * 10 16Cm -3, the Ge component is a Gradient distribution, and lower floor is 10%, and the upper strata is 30%, as the nmos device channel region;
(6e) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the N type strain SiGe layer of 5nm at nmos device active area selective growth thickness, and doping content is 5 * 10 17Cm -3, the Ge component is 30%, as the 2nd N type lightly-doped source drain structure (N-LDD) layer of nmos device;
(6f) utilizing the method for chemical vapor deposition (CVD), at 600 ℃, is the N type Si layer of 400nm at nmos device active area selective growth thickness, and doping content is 5 * 10 19Cm -3, as the nmos device source region;
(6g) utilize the method for chemical vapor deposition (CVD), at 600 ℃, at substrate surface deposit one deck SiO 2
(6h) photoetching PMOS device active region etches the shallow slot that the degree of depth is 100nm at the PMOS device active region;
(6i) utilize the method for chemical vapor deposition (CVD), at 600 ℃, mix in PMOS device area growth one deck N type, doping content is 5 * 10 16Cm -3, thickness is the Si epitaxial loayer of 80nm, regrowth one N type strain SiGe layer, and doping content is 5 * 10 16Cm -3, the Ge component is 10%, thickness is 20nm;
(6j) utilize the method for chemical vapor deposition (CVD), at 600 ℃, at PMOS device active region selective growth one intrinsic relaxation Si cap layer, thickness is 5nm, forms the PMOS device active region;
Step 7, nmos device are leaked the implementation method that connects preparation and are:
(7a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at nmos device surfaces of active regions deposit one deck SiO 2And layer of sin, form the barrier layer;
(7b) the photoetching nmos device leaks groove, utilizes dry etch process, and etching the degree of depth is the leakage groove of 0.6 μ m;
(7c) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one deck SiO 2, forming nmos device and leak the trenched side-wall isolation, dry etching falls the SiO on surface 2, keep the SiO that leaks trenched side-wall 2
(7d) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is 1 * 10 in substrate surface deposit doping content 20Cm -3N type Ploy-Si, nmos device is leaked groove fills up;
(7e) utilize chemico-mechanical polishing (CMP) method, remove the unnecessary Ploy-Si of substrate surface, form nmos device and leak the bonding pad;
(7f) utilize wet etching, etch away the layer SiO on surface 2And SiN;
Step 8, the implementation method that nmos device forms is:
(8a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at nmos device surfaces of active regions deposit one deck SiO 2And layer of sin, form the barrier layer once more;
(8b) photoetching nmos device grid window utilizes dry etch process, etches the gate groove that the degree of depth is 0.6 μ m;
(8c) utilizing atomic layer chemical vapour deposition (ALCVD) method, at 300 ℃, is the HfO of 5nm at substrate surface deposit one layer thickness 2, form the nmos device gate dielectric layer;
(8d) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is 1 * 10 in substrate surface deposit doping content 20Cm -3N type Poly-Si, the nmos device gate groove is filled up;
(8e) get rid of nmos device gate groove surperficial part Poly-Si and HfO again 2Layer forms nmos device grid, source region, finally forms nmos device;
(8f) utilize wet etching, etch away the SiO on surface 2With the SiN layer;
Step 9, the implementation method that preparation is leaked in empty grid of PMOS device and source is:
(9a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at nmos device surfaces of active regions deposit one deck SiO 2
(9b) photoetching PMOS device active region utilizes chemical vapor deposition (CVD) method, at 600 ℃, is the SiO of 10nm at substrate surface deposit one layer thickness 2
(9c) utilizing chemical vapor deposition (CVD) method, at 600 ℃, is the Poly-Si of 200nm at substrate surface deposit one layer thickness;
(9d) photoetching Poly-Si and SiO 2, form the empty grid of PMOS device;
(9e) the PMOS device is carried out P type ion and inject, forming doping content is 1 * 10 18Cm -3P type lightly-doped source drain structure (P-LDD);
(9f) utilize chemical vapor deposition (CVD) method, at 600 ℃, deposit one layer thickness is the SiO of 3nm on substrate surface 2, dry etching falls the SiO on the substrate surface 2, the SiO of reservation Ploy-Si sidewall 2, form PMOS device gate electrode side wall;
(9g) the PMOS device active region is carried out P type ion and inject, autoregistration generates the source region and the drain region of PMOS device, makes the source-drain area doping content reach 5 * 10 19Cm -3
Step 10, the implementation method that the PMOS device forms is:
(10a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit SiO 2Layer with chemico-mechanical polishing (CMP) method flat surface, is used dry etch process etching surface SiO again 2To empty grid upper surface, expose empty grid;
(10b) the empty grid of wet etching form a groove at the gate electrode place;
(10c) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit one deck SiON, thickness is 5nm;
(10d) with physical vapor deposition (PVD) deposit W-TiN composite grid, (CMP) removes surface metal with chemico-mechanical polishing;
(10e) with the stop layer of W-TiN composite grid, thereby form grid, finally form the PMOS device as chemico-mechanical polishing (CMP);
Step 11, the implementation method that constitutes the BiCMOS integrated circuit is:
(11a) utilize chemical vapor deposition (CVD) method, at 600 ℃, at substrate surface deposit SiO 2Layer;
(11b) lithography fair lead;
(11c) metallization;
(11d) splash-proofing sputtering metal, photoetching lead-in wire, formation MOS device conducting channel are that the strain SiGe of 45nm returns type channel SOI BiCMOS integrated device and circuit.
CN201210243600.1A 2012-07-16 2012-07-16 A kind of strain SiGe hollow channel SOI BiCMOS integrated device and preparation method Expired - Fee Related CN102738173B (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6429061B1 (en) * 2000-07-26 2002-08-06 International Business Machines Corporation Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation
US20050104127A1 (en) * 2003-11-19 2005-05-19 Kang Jin Y. Bipolar transistor, BiCMOS device, and method for fabricating thereof
CN101295647A (en) * 2008-01-16 2008-10-29 清华大学 Method for reinforcing MOS device channel region strain
CN102184898A (en) * 2011-04-22 2011-09-14 上海宏力半导体制造有限公司 Method for manufacturing semiconductor device and method for manufacturing SiGe HBT (Heterojunction Bipolar Transistor)

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6429061B1 (en) * 2000-07-26 2002-08-06 International Business Machines Corporation Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation
US20050104127A1 (en) * 2003-11-19 2005-05-19 Kang Jin Y. Bipolar transistor, BiCMOS device, and method for fabricating thereof
CN101295647A (en) * 2008-01-16 2008-10-29 清华大学 Method for reinforcing MOS device channel region strain
CN102184898A (en) * 2011-04-22 2011-09-14 上海宏力半导体制造有限公司 Method for manufacturing semiconductor device and method for manufacturing SiGe HBT (Heterojunction Bipolar Transistor)

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