CN102707919A - Device and method for controlling FIFO (First In First Out) read-write by using finite state machine (FSM) - Google Patents

Abstract

The invention discloses a device for controlling FIFO (First In First Out) read-write by using a finite state machine (FSM), which comprises an image sensor, an FPGA (Field Programmable Gate Array) and a DSP (Digital Signal Processor) chip which are sequentially connected. The DSP chip is connected with a host computer through the FPGA. The device is characterized in that three FIFO reading and null signals in the FPGA are all controlled by the FSM; and the FSM further controls an FIFO writing and full signal used for writing. The device has the beneficial effects that the control of the FIFO read-write is changed to be state control through the method of using the FSM, so the design process is simplified, and the design period is shortened. Compared with the convention control of the FIFO read-write, the control applied by the FSM is more efficient and more stable.

Description

A kind of device and method of reading and writing between the finite states machine control FIFO that uses

Technical field

The present invention relates to a kind of control of the FIFO read-write when being used for realtime image data transmission data, in particular a kind of based on FPGA 3 data width of use in the high resolution scanning imaging be 8 FIFO to read with a data width be the control of writing of 8 FIFO.

Background technology

In the high resolution scanning imaging system; The data of acceptance pattern image-position sensor among the FPGA; After the bayer2rgb module is accomplished preliminary 24 rgb image datas of interpolation arithmetic generation; Be 38 YCbCr data again through the rgb2ycbcr module converts, transfer to kernel processor chip such as DSP to carry out complicated digital signal processing computing.DSP transfers to FPGA to view data with identical data layout after accomplishing calculation process; FPGA accomplishes YCbCr4:2:2 after the 4:4:4 format conversion through deinterleaving and interpolating module; Use ycbcr2rgb module is data-switching 38 a rgb image data; Write respectively among 3 FIFO, owing to controller and the host computer of final transmission channel interface by USB constitutes, and the transmission data width of USB controller is 8.Therefore must be in a certain order before final transmission the view data among 3 FIFO, be written to a data width and be among 8 the FIFO and cushion, finally transfer data to host computer by FPGA control USB controller again.

Summary of the invention

The object of the present invention is to provide a kind of device of reading and writing between the finite states machine control FIFO that uses; Utilize FSM finite state machine method to be converted into State Control to the control of reading and writing between the FIFO; Simplify design process, shortened the design cycle, compared the control of reading and writing between traditional FIFO; State machine is more efficient, and is stable.

The technical matters that the present invention solved can adopt following technical scheme to realize:

A kind of device of reading and writing between the finite states machine control FIFO that uses; It comprises imageing sensor, FPGA, RGB module and the dsp chip that connects successively; Said dsp chip connects host computer through FPGA; It is characterized in that: the reading of 3 FIFO among the said FPGA, spacing wave be by the FSM finite states machine control, and the FSM finite state machine is also controlled the writing of 1 FIFO that is used to write, full signal.

In one embodiment of the invention, the data width of said FIFO is 8.

A kind of method of reading and writing between the finite states machine control FIFO of using is characterized in that said method comprises the steps:

1) under the driving of clock signal, produce next state next_state, simultaneously 3 spacing wave empty and read signal read that store the FIFO of BGR data are respectively done a clock delay;

2) under input signal and clock effect, accomplish the conversion of existing attitude current_state and next state next_state, use solely hot sign indicating number one-hot to carry out state encoding to 3 read signal states of storing the FIFO of BGR data respectively;

3) under the effect of read signal, realize the control of writing to the FIFO that writes data through time-delay.

Beneficial effect of the present invention is: utilize FSM finite state machine method to be converted into State Control to the control of reading and writing between the FIFO, simplified design process, shortened the design cycle, compare the control of reading and writing between traditional FIFO, state machine is more efficient, and is stable.

Description of drawings

Fig. 1 is the structured flowchart of FSM finite state machine.

Fig. 2 is the state transition diagram of FSM finite state machine.

Fig. 3 is that FIFO is connected synoptic diagram with state machine among the FPGA.

Embodiment

For technological means, creation characteristic that the present invention is realized, reach purpose and effect and be easy to understand and understand, below in conjunction with embodiment, further set forth the present invention.

Referring to Fig. 3; A kind of device of reading and writing between the finite states machine control FIFO that uses; It comprises imageing sensor, FPGA, RGB module and the dsp chip that connects successively; Said dsp chip connects host computer through FPGA, it is characterized in that: the reading of 3 FIFO among the said FPGA, spacing wave be by the FSM finite states machine control, and the FSM finite state machine is also controlled the writing of 1 FIFO that is used to write, full signal.

A kind of method of reading and writing between the finite states machine control FIFO of using is characterized in that said method comprises the steps:

1) under the driving of clock signal, produce next state next_state, simultaneously 3 spacing wave empty and read signal read that store the FIFO of BGR data are respectively done a clock delay;

2) under input signal and clock effect, accomplish the conversion of existing attitude current_state and next state next_state, use solely hot sign indicating number one-hot to carry out state encoding to 3 read signal states of storing the FIFO of BGR data respectively;

3) under the effect of read signal, realize the control of writing to the FIFO that writes data through time-delay.

Below combine Fig. 1 and Fig. 2 respectively, to this method in the high resolution scanning imaging system, utilize the FSM finite state machine to 3 data width be 8 FIFO read with a data width be that the Control work of writing of 8 FIFO is elaborated.

The high resolving power bayer picture signal pre-service of the 2592*1944 (pixel/frame) that this imaging system will be obtained from imageing sensor becomes the RGB colour signal; Through rgb2ycbcr module and output timing control module; Let DSP accomplish the core digital signal processing computing of image; After finishing dealing with, DSP returns image data transmission among the FPGA; FPGA converts view data into 24 RGB data through input timing control module and ycbcr2rgb module, because final data must carry out last splicing and processing by 8 bit data channel transfer to host computers of USB controller; So FPGA is earlier in 24 RGB data storage to 3 asynchronous FIFOs; Again by the writing of FIFO of reading and finally is connected the USB controller of 3 FIFO of FSM finite states machine control, accomplishes of the transmission of 38 RGB data according to BMP document order (8 B 8 R data behind 8 G) earlier again, transmit completion entire image data until in this order.

In the next state logic of the structured flowchart of FSM finite state machine, adopted asynchronous reset among Fig. 1, if reset signal is effective, then state is original state state_B; Under the effect of clock signal; Accomplish the conversion of existing attitude and next state, the spacing wave empty_B, empty_G, the empty_R that preserve 3 current storage data FIFO respectively by 6 one shift register simultaneously are respectively empty_B_d, empty_G_d, empty_R_d and 3 current read signal read_en_B, reda_en_G, read_en_R that store data FIFO and are respectively read_en_B_d, read_en_G_d, read_en_R_d.

The function that status register among Fig. 1 in the structured flowchart of FSM finite state machine is accomplished can be described by the state transition diagram of the FSM finite state machine among Fig. 2:

1) the existing attitude of acquiescence is that original state is state_B, if among the FIFO of storage data B for sky is that empty_B is 1 o'clock, then NextState or state_B; Be that read_B_en puts 0; Read_G_en puts 0, and read_R_en puts 0, promptly accomplishes latency function and does not read any data.If one data are arranged is that empty_B is 0 o'clock among the FIFO of storage data B; If preparation writes the FIFO that just reads storage data B when the FIFO of data is discontented with; Be that read_B_en puts 1, read_G_en puts 0, and read_G_en puts 0; Accomplish the function of reading of first data B, the NextState that enters into read data simultaneously is state_G.Otherwise NextState is state_B still, and read_B_en puts 0, and read_G_en puts 0, and read_R_en puts 0, and the FIFO that promptly wait for to prepare to write data becomes the state of can writing and just begins read data B.

When 2) after state state_B accomplishes, entering into state state_G; If preparation writes the FIFO that just reads storage data G when the FIFO of data is discontented with; Be that read_B_en puts 0, read_G_en puts 1, and read_R_en puts 0; Accomplish the function of reading of second data G, the NextState that enters into read data simultaneously is state_R.Otherwise NextState is state_G still, and read_B_en puts 0, and read_G_en puts 0, and read_R_en puts 0, and the FIFO that promptly wait for to prepare to write data becomes the state of can writing and just begins read data G.

When 3) after state state_G accomplishes, entering into state state_R; If preparation writes the FIFO that just reads storage data R when the FIFO of data is discontented with; Be that read_B_en puts 0, read_G_en puts 0, and read_R_en puts 1; Accomplish the function of reading of the 3rd data R, the NextState that enters into read data simultaneously is state_B.Otherwise NextState is state_R still, and read_B_en puts 0, and read_G_en puts 0, and read_R_en puts 0, and the FIFO that promptly wait for to prepare to write data becomes the state of can writing and just begins read data R.

4) repeat said process accomplish 3 storing image data BGR FIFO read control.

Output logic among Fig. 1 in the structured flowchart of FSM finite state machine is accomplished the data of finally writing FIFO and is write the control with write signal wr_end:

1) be read_en_B_d when being 1 after the FIFO read data of storage B data is accomplished, the write signal wr_end that writes the FIFO of data puts 1, writes data B simultaneously.

2) be read_en_G_d when being 1 after the FIFO read data of storage G data is accomplished, the write signal wr_end that writes the FIFO of data puts 1, writes data G simultaneously.

3) be read_en_R_d when being 1 after the FIFO read data of storage R data is accomplished, the write signal wr_end that writes the FIFO of data puts 1, writes data R simultaneously.

4) order of repetition said process completion view data BGR is written among the FIFO.

More than show and described ultimate principle of the present invention and principal character and advantage of the present invention.The technician of the industry should understand; The present invention is not restricted to the described embodiments; That describes in the foregoing description and the instructions just explains principle of the present invention; Under the prerequisite that does not break away from spirit and scope of the invention, the present invention also has various changes and modifications, and these variations and improvement all fall in the scope of the invention that requires protection.The present invention requires protection domain to be defined by appending claims and equivalent thereof.

Claims (3)

1. one kind is used the device of reading and writing between the finite states machine control FIFO; It comprises imageing sensor, FPGA and the dsp chip that connects successively; Said dsp chip connects host computer through FPGA; It is characterized in that the reading of 3 FIFO that are used to read, spacing wave are by the FSM finite states machine control among the said FPGA, the FSM finite state machine is also controlled the writing of 1 FIFO that is used to write, full signal.

2. a kind of device that uses read-write completion data transmission between the finite states machine control FIFO according to claim 1 is characterized in that the data width of said FIFO is 8.

3. one kind is used the method for reading and writing between the finite states machine control FIFO, it is characterized in that, said method comprises the steps:

1) under clock signal drives, produces next state next_state, simultaneously 3 spacing wave empty and read signal read that store the FIFO of BGR data are respectively done a clock delay;

2) under input signal and clock effect, accomplish the conversion of existing attitude current_state and next state next_state, use solely hot sign indicating number one-hot to carry out state encoding to 3 read signal states of storing the FIFO of BGR data respectively;

3) under the effect of read signal, realize the control of writing to the FIFO that writes data through time-delay.

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