CN102623414A - Semiconductor package - Google Patents
Semiconductor package Download PDFInfo
- Publication number
- CN102623414A CN102623414A CN2012101048085A CN201210104808A CN102623414A CN 102623414 A CN102623414 A CN 102623414A CN 2012101048085 A CN2012101048085 A CN 2012101048085A CN 201210104808 A CN201210104808 A CN 201210104808A CN 102623414 A CN102623414 A CN 102623414A
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- CN
- China
- Prior art keywords
- projection
- fid
- crystal grain
- semiconductor packages
- passivation layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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- Wire Bonding (AREA)
Abstract
The invention relates to a semiconductor package, which comprises a base plate, a die and a plurality of supporting members. The base plate is provided with an upper surface and a plurality of connection pads which are formed on the upper surface. The die provided with an active face, a passivation layer and a plurality of protrusion blocks is arranged on the upper surface of the base plate, the passiviation layer and the protrusion blocks are formed on the active face, and the protrusion blocks abut to the connection blocks respectively. The supporting blocks are respectively arranged among the protrusion blocks, each of the supporting blocks has a first end and an opposite second end, the first end of each of the supporting members contacts with the passivation layer of the die, and the second end of each of the supporting members contacts with the upper surface of the base plate. Accordingly, programs of the thermo-compression bonding technology can be effectively controlled; certain height is guaranteed to exist between the protrusion blocks and the connection pads after thermo-compression bonding, and thermo-compression bonding qualities of the protrusion blocks are improved as for the effect.
Description
Technical field
The present invention is about a kind of semiconductor packages, especially in regard to a kind of semiconductor packages with fid.
Background technology
The crystal grain of known semiconductor encapsulation is carrying out must accomplishing X, Y axle contraposition program through accurate contraposition board earlier before thermocompression bonding engages with substrate, and must when carrying out thermocompression bonding and engage, effectively control Z axle height, thereby increase thermocompression bonding process time and complexity.
In addition, in general thermocompression bonding technology, use non-conductive adhesive (nonconductive paste through regular meeting; NCP) projection of sealing crystal grain; Only, when the thickness of crystal grain less than to a certain degree the time, take place easily that NCP climbs glue to the crystal grain back side and the problem of polluting the circuit at the crystal grain back side.
In view of this, be necessary to provide the semiconductor packages of an innovation and tool progressive, to address the above problem.
Summary of the invention
The present invention is provided with fid between the projection of crystal grain, can possess certain height between projection after can guaranteeing thermocompression bonding when the thermocompression bonding technology via this fid and the connection gasket, thereby can promote the hot press quality of projection.The present invention forms a ponding in addition on crystal grain, this ponding is climbed glue to the crystal grain back side around projection in order to the non-conductive adhesive (NCP) that prevents to seal projection.
The present invention provides a kind of semiconductor packages, comprises a substrate, a crystal grain and a plurality of fid.This substrate has a upper surface and a plurality of connection gasket, and these connection gaskets are formed at this upper surface.This crystal grain is arranged at the upper surface of this substrate, and this crystal grain has an active surface, a passivation layer and a plurality of projection, and this passivation layer and these projections are formed at this active surface, and these projections are distinguished respectively this connection gasket of butts.These fids are arranged at respectively respectively between this projection, and each fid has one first end and a second opposed end, this passivation layer of first this crystal grain of end in contact of this fid respectively, and the upper surface of second this substrate of end in contact of this fid respectively.
The present invention provides another kind of semiconductor packages, comprises a substrate, a crystal grain, a plurality of fid and a ponding.This substrate has a upper surface and a plurality of connection gasket, and these connection gaskets are formed at this upper surface.This crystal grain is arranged at the upper surface of this substrate, and this crystal grain has an active surface, a passivation layer and a plurality of projection, and this passivation layer and these projections are formed at this active surface, and these projections are distinguished respectively this connection gasket of butts.These fids are arranged at respectively respectively between this projection, and each fid has one first end and a second opposed end, this passivation layer of first this crystal grain of end in contact of this fid respectively, and the upper surface of second this substrate of end in contact of this fid respectively.This ponding is formed on this crystal grain, and this ponding is around these projections.
For there is better understanding above-mentioned and other aspects of the present invention, hereinafter is special lifts preferred embodiment, and conjunction with figs., elaborates as follows:
Description of drawings
Fig. 1 shows the structural representation of the semiconductor packages of first embodiment of the invention;
Fig. 2 A to 2B shows the different array distribution sketch mapes of fid of the present invention;
Fig. 3 shows the figure of another distribution aspect of fid of the present invention;
Fig. 4 A to 4K shows the manufacturing process sketch map according to the semiconductor packages of first embodiment of the invention;
Fig. 5 shows the structural representation of the semiconductor packages of second embodiment of the invention;
Fig. 6 shows the structural representation of the ponding of second embodiment of the invention;
Fig. 7 shows the structural representation of the ponding of another embodiment of the present invention;
Fig. 8 shows the structural representation of the ponding of further embodiment of this invention; And
Fig. 9 A to 9F shows the manufacturing process sketch map according to the semiconductor packages of second embodiment of the invention.
Embodiment
See also Fig. 1, it shows the structural representation of the semiconductor packages of first embodiment of the invention.This semiconductor packages 10 of first embodiment of the invention comprises a substrate 11, a crystal grain 12 and a plurality of fid 13.
This substrate 11 has a upper surface 11a and a plurality of connection gasket 111, and these connection gaskets 111 are formed at this upper surface 11a.
This crystal grain 12 is arranged at the upper surface 11a of this substrate 11, and this crystal grain 12 has an active surface 12a, a back side 12b, a passivation layer 121 and a plurality of projection 122.This passivation layer 121 and these projections 122 are formed at this active surface 12a, and these projections 122 are distinguished respectively this connection gasket 111 of butts.In the present embodiment, respectively this projection 122 has a bronze medal post portion 123 and a solder sections 124, and respectively this solder sections 124 is arranged at a respectively end of this copper post portion 123, and respectively this solder sections 124 is engaged in respectively this connection gasket 111.In addition, in the present embodiment, this back side 12b also can be formed with a passivation layer 125.
Fig. 2 A to 2B shows the different array distribution sketch mapes of fid of the present invention.Please cooperate and consult Fig. 1 and Fig. 2 A to 2B, these fids 13 are arranged at respectively respectively between this projection 122, and preferably, these fid 13 array distribution are in respectively between this projection 122, and these fids 13 hardness material hard than fusion scolding tin when being high temperature.In the present embodiment; Each fid 13 has one first an end 13a and a second opposed end 13b; Respectively this crystal grain 12 of the first end 13a of this fid 13 contact this passivation layer 121; And the upper surface 11a of this substrate 11 of the second end 13b of this fid 13 contact respectively, preferably, respectively this fid 13 does not contact respectively this projection 122.
In addition; In the present embodiment, respectively the width W 1 of this fid 13 is not less than the respectively radius R of this projection 122, i.e. W1 >=R; And respectively the height H 1 of this fid 13 be not less than the height H 2 of this copper post portion 123 respectively and half height of this solder sections 124 respectively (0.5 * H3) with; Preferably, respectively the height H 1 of this fid 13 equal the height H 2 of this copper post portion 123 respectively and half height of this solder sections 124 respectively (0.5 * H3) with, that is H1 >=H2+0.5H3.
See also Fig. 3, it shows the figure of another distribution aspect of fid of the present invention.As shown in Figure 3, but these fids 13 of the present invention also distributed and arranged in four corners of the active surface 12a of this crystal grain 12.
Fig. 4 A to 4K shows the manufacturing process sketch map according to the semiconductor packages of first embodiment of the invention.
Shown in Fig. 4 A, a base material 120 is provided, in the present embodiment, this base material 120 has an active surface 12a, a back side 12b and passivation layer 121,125, and these passivation layers 121,125 are formed at this active surface 12a and this back side 12b respectively;
Shown in Fig. 4 B, form one first photoresist layer 210 on the passivation layer 121 of this base material 120, in the present embodiment, this first photoresist layer 210 forms with the rotary coating mode;
Shown in Fig. 4 C, carry out one first patterning step, this first patterning step comprises makes public and step such as development to this first photoresist layer 210, so that this first photoresist layer 210 is formed with a plurality of first grooves 211;
Shown in Fig. 4 D, form a fid 13 in this first groove 211 respectively, in the present embodiment, this fid 13 forms with plating mode;
Shown in Fig. 4 E, remove this first photoresist layer 210, to appear this passivation layer 121 and these fids 13;
Shown in Fig. 4 F, form one second photoresist layer 220 on the passivation layer 121 of this base material 120, in the present embodiment, this second photoresist layer 220 covers this passivation layer 121 and these fids 13;
Shown in Fig. 4 G; Carry out one second patterning step; This second patterning step comprises makes public to this second photoresist layer 220 earlier and step such as development, so that this second photoresist layer 220 is formed with a plurality of second grooves 221, afterwards; The passivation layer 121 that these second grooves 221 are appeared carries out etching, to appear the active surface 12a of this base material 120;
Shown in Fig. 4 H, form a projection 122 in this second groove 221 respectively, in the present embodiment, to electroplate earlier and form a bronze medal post portion 123 on this active surface 12a, re-plating forms a solder sections 124 in this copper post portion 123, to form this projection 122 by this;
Shown in Fig. 4 I, remove this second photoresist layer 220, to appear this passivation layer 121, these fids 13 and these projections 122;
Shown in Fig. 4 J, carry out a reflow step, so that respectively respectively these solder sections 124 formation of this projection 122 are hemispherical, so far promptly accomplish the making of crystal grain 12; And
Shown in Fig. 4 K, carry out a thermocompression bonding step, with these projection 122 hot press of this crystal grain 12 in a plurality of connection gaskets 111 of a substrate 11, promptly accomplish the making of the semiconductor packages of first embodiment of the invention.
Certain height can be possessed between these projections 122 after the semiconductor packages of first embodiment of the invention can be guaranteed thermocompression bonding when the thermocompression bonding technology via this fid 13 and these connection gaskets 111, thereby the hot press quality of these projections 122 can be promoted.
See also Fig. 5, it shows the structural representation of the semiconductor packages of second embodiment of the invention.The semiconductor packages of second embodiment of the invention is identical with first embodiment basically, and its difference place only is that the semiconductor packages 10 of second embodiment comprises a ponding 14 in addition, and this ponding 14 is formed on this crystal grain 12; And this ponding 14 is around these projections 122; In this embodiment, this ponding 14 is formed on this passivation layer 121 of this crystal grain 12, and preferably; The height H 4 of this ponding 14 be not less than this projection 122 respectively half height (0.5 * H), i.e. H4 >=0.5H.
Fig. 6 shows the structural representation of the ponding of second embodiment of the invention.As shown in Figure 6, this ponding 14 has four strip shape bodies 141, and these strip shape bodies 141 are separated from one another, and is arranged in a block form, and in the present embodiment, the width W 2 of these strip shape bodies 141 is not less than the respectively radius R of this projection 122, i.e. W2 >=R.
Fig. 7 shows the structural representation of the ponding of another embodiment of the present invention.As shown in Figure 7, this ponding 14 has two L type strip shape bodies 142, and these L type strip shape bodies 142 are separated from one another, and are arranged in a block form, and likewise, the width W 3 of these L type strip shape bodies 142 is not less than the respectively radius R of this projection 122.
Fig. 8 shows the structural representation of the ponding of further embodiment of this invention.As shown in Figure 8, this ponding 14 can be the square frame body.
Fig. 9 A to 9F shows the manufacturing process sketch map according to the semiconductor packages of second embodiment of the invention.The manufacturing step of the semiconductor packages of second embodiment of the invention manufacturing step Fig. 4 A to Fig. 4 I with first embodiment basically is identical, and its difference place only is to carry out manufacturing step Fig. 9 A to Fig. 9 F behind manufacturing step Fig. 4 I.
Shown in Fig. 9 A, removing this second photoresist layer 220 (Fig. 4 I) afterwards, form one the 3rd photoresist layer 230 on the passivation layer 121 of this base material 120, in the present embodiment, the 3rd photoresist layer 230 covers this passivation layer 121, these fids 13 and these projections 122;
Shown in Fig. 9 B, carry out one the 3rd patterning step, the 3rd patterning step comprises makes public and step such as development to the 3rd photoresist layer 230, so that the 3rd photoresist layer 230 is formed with at least one the 3rd groove 231;
Shown in Fig. 9 C, form a ponding 14 in the 3rd groove 231, in the present embodiment, this ponding 14 can be coated with or plating mode forms.
Shown in Fig. 9 D, remove the 3rd photoresist layer 230, to appear this passivation layer 121, these fids 13, these projections 122 and this ponding 14;
Shown in Fig. 9 E, carry out a reflow step, so that respectively respectively these solder sections 124 formation of this projection 122 are hemispherical, so far promptly accomplish the making of crystal grain 12; And
Shown in Fig. 9 F, carry out a thermocompression bonding step, with these projection 122 hot press of this crystal grain 12 in a plurality of connection gaskets 111 of a substrate 11, promptly accomplish the making of the semiconductor packages of second embodiment of the invention.In this step, can a non-conductive adhesive (NCP) 30 these projections 122 of sealing and these fids 13.
The semiconductor packages of second embodiment of the invention through the setting of this ponding 14, also has the non-conductive adhesive (NCP) 30 that prevents to seal these projections 122 and climbs the effect of glue to these crystal grain 12 back sides except possessing the effect like the semiconductor packages of first embodiment.
The foregoing description is merely explanation principle of the present invention and effect thereof, and unrestricted the present invention, and therefore practising makes amendment to the foregoing description and change in this technological personage does not still take off spirit of the present invention.Interest field of the present invention should be listed like claims.
Claims (10)
1. semiconductor packages comprises:
One substrate has a upper surface and a plurality of connection gasket, and said connection gasket is formed at this upper surface;
One crystal grain is arranged at the upper surface of this substrate, and this crystal grain has an active surface, a passivation layer and a plurality of projection, and this passivation layer and said projection are formed at this active surface, and said projection butt this connection gasket respectively respectively; And
A plurality of fids are arranged at respectively respectively between this projection, and each fid has one first end and a second opposed end, this passivation layer of first this crystal grain of end in contact of this fid respectively, and the upper surface of second this substrate of end in contact of this fid respectively.
2. semiconductor packages as claimed in claim 1, wherein respectively this fid does not contact respectively this projection.
3. semiconductor packages as claimed in claim 1; Wherein respectively this projection of this crystal grain has a bronze medal post portion and a solder sections; Respectively this solder sections is arranged at a respectively end of this copper post portion; And respectively this solder sections is engaged in respectively this connection gasket, respectively the height of this fid be not less than the height of this copper post portion respectively and this solder sections respectively half height with.
4. semiconductor packages as claimed in claim 1, wherein respectively the width of this fid is not less than the respectively radius of this projection.
5. semiconductor packages as claimed in claim 1, wherein said fid array distribution is in respectively between this projection.
6. semiconductor packages comprises:
One substrate has a upper surface and a plurality of connection gasket, and said connection gasket is formed at this upper surface;
One crystal grain is arranged at the upper surface of this substrate, and this crystal grain has an active surface, a passivation layer and a plurality of projection, and this passivation layer and said projection are formed at this active surface, and said projection butt this connection gasket respectively respectively;
A plurality of fids are arranged at respectively respectively between this projection, and each fid has one first end and a second opposed end, this passivation layer of first this crystal grain of end in contact of this fid respectively, and the upper surface of second this substrate of end in contact of this fid respectively; And
One ponding is formed on this crystal grain, and this ponding is around said projection.
7. semiconductor packages as claimed in claim 6, wherein this ponding is formed on this passivation layer of this crystal grain.
8. semiconductor packages as claimed in claim 6, wherein the height of this ponding is not less than respectively half height of this projection.
9. semiconductor packages as claimed in claim 6, wherein this ponding has four strip shape bodies, and said strip shape body is separated from one another, and is arranged in a block form.
10. semiconductor packages as claimed in claim 6, wherein this ponding has two L type strip shape bodies, and said L type strip shape body is separated from one another, and is arranged in a block form.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012101048085A CN102623414A (en) | 2012-04-11 | 2012-04-11 | Semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012101048085A CN102623414A (en) | 2012-04-11 | 2012-04-11 | Semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102623414A true CN102623414A (en) | 2012-08-01 |
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ID=46563241
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2012101048085A Pending CN102623414A (en) | 2012-04-11 | 2012-04-11 | Semiconductor package |
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| Country | Link |
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| CN (1) | CN102623414A (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6399426B1 (en) * | 1998-07-21 | 2002-06-04 | Miguel Albert Capote | Semiconductor flip-chip package and method for the fabrication thereof |
| TWM248160U (en) * | 2003-11-20 | 2004-10-21 | Chipmos Technologies Inc | Image sensor for avoiding sensing area being contaminated |
| US20060098244A1 (en) * | 2004-11-05 | 2006-05-11 | Samsung Electronics Co., Ltd. | Image sensor assembly and method for fabricating the same |
| CN1925163A (en) * | 2005-09-01 | 2007-03-07 | 南茂科技股份有限公司 | Glass coating package structure for image detector |
| CN100420004C (en) * | 2004-01-09 | 2008-09-17 | 日月光半导体制造股份有限公司 | Flip chip packaging body |
| CN101562157A (en) * | 2008-04-17 | 2009-10-21 | 南茂科技股份有限公司 | Chip encapsulation structure and support device thereof |
| CN101719485A (en) * | 2007-11-19 | 2010-06-02 | 日月光半导体制造股份有限公司 | Chip structure, substrate structure, chip package structure and process thereof |
| CN102208358A (en) * | 2011-04-25 | 2011-10-05 | 北京大学深圳研究生院 | Method for soldering flip chip on base plate and packaging apparatus |
-
2012
- 2012-04-11 CN CN2012101048085A patent/CN102623414A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6399426B1 (en) * | 1998-07-21 | 2002-06-04 | Miguel Albert Capote | Semiconductor flip-chip package and method for the fabrication thereof |
| TWM248160U (en) * | 2003-11-20 | 2004-10-21 | Chipmos Technologies Inc | Image sensor for avoiding sensing area being contaminated |
| CN100420004C (en) * | 2004-01-09 | 2008-09-17 | 日月光半导体制造股份有限公司 | Flip chip packaging body |
| US20060098244A1 (en) * | 2004-11-05 | 2006-05-11 | Samsung Electronics Co., Ltd. | Image sensor assembly and method for fabricating the same |
| CN1925163A (en) * | 2005-09-01 | 2007-03-07 | 南茂科技股份有限公司 | Glass coating package structure for image detector |
| CN101719485A (en) * | 2007-11-19 | 2010-06-02 | 日月光半导体制造股份有限公司 | Chip structure, substrate structure, chip package structure and process thereof |
| CN101562157A (en) * | 2008-04-17 | 2009-10-21 | 南茂科技股份有限公司 | Chip encapsulation structure and support device thereof |
| CN102208358A (en) * | 2011-04-25 | 2011-10-05 | 北京大学深圳研究生院 | Method for soldering flip chip on base plate and packaging apparatus |
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Application publication date: 20120801 |