CN102611411B - A kind of tracing compensation integrator, broadband filter and broadband analogue chip - Google Patents

Abstract

The embodiment of the invention discloses a kind of compensation integrator, described compensation integrator comprises: operational amplifier, integrating resistor and integrating capacitor and zero mark resistance; Described integrating resistor connects the input of described operational amplifier, and described integrating capacitor and described zero mark resistance series connection are between the input and output of described operational amplifier; Described zero mark resistance is for generation of a zero point; The zero point that described operational amplifier is used for described zero mark resistance to produce is associated with the limit that self finite bandwidth produces, and offsets described limit, realizes tracing compensation.The embodiment of the present invention also discloses a kind of broadband filter and broadband analogue chip.Adopt the embodiment of the present invention, the tracing compensation of zero point to the limit that operational amplifier finite bandwidth produces can be realized, thus because of the impact that amplifier finite bandwidth brings in elimination broadband filter, realize stable high bandwidth filter.

Description

A kind of tracing compensation integrator, broadband filter and broadband analogue chip

Technical field

The present invention relates to broadband communications technologies field, particularly relate to a kind of tracing compensation integrator, broadband filter and broadband analogue chip.

Background technology

Along with LTE (Long Term Evolution, Long Term Evolution) and the progress of microwave communication in broadband communications technologies field, strong to the demand of broadband analogue chip.Analog filter is the circuit that in chip, baseband portion carries out filtering, and present base band frequency bandwidth is even wider more than 20,000,000.In order to realize high linearity while realizing high bandwidth, it is main selection that amplifier and resistance capacitance combine the analog filter formed, and this filter can be claimed to be active RC filter.

The transfer function of desirable active RC filter is determined by the value of resistance capacitance, has nothing to do with the bandwidth of amplifier itself.But when filter bandwidht is larger, the finite bandwidth of amplifier can not be ignored, has even had a strong impact on the transfer function of filter, cause uneven in filter band increase and spike increase, have impact on use.And the bandwidth of amplifier can change along with flow-route and temperature, cause eliminating the impact of amplifier finite bandwidth on filter more difficult.

For reducing the finite bandwidth of amplifier to the impact of filter, present common way is the bandwidth increasing amplifier, make the bandwidth of amplifier far above the bandwidth of filter itself, but, this method can increase power consumption greatly when increasing the bandwidth of amplifier, and is also difficult to unlimited raising because of the restriction amplifier bandwidth of technique.

The quality factor of its transfer function can also be adjusted by tandem tap resistance in biquadratic filter in prior art.But, this method needs to increase extra quality factor and detects and RC calibration circuit, calibrated by the quality factor of value to filter adjusting switch resistance, but the parasitic capacitance that the switch resistance increased produces can worsen the performance of broadband filter, and described RC calibration circuit structure is very complicated, be not easy to realize.

Summary of the invention

Embodiments of the invention provide a kind of tracing compensation integrator, broadband filter and broadband analogue chip, and this compensation integrator can be eliminated in broadband filter because of the impact that amplifier finite bandwidth brings, and realizes stable high bandwidth filter.

The embodiment of the present invention provides a kind of and compensates integrator, and described compensation integrator comprises: operational amplifier, integrating resistor and integrating capacitor and zero mark resistance;

Described integrating resistor connects the input of described operational amplifier, and described integrating capacitor and described zero mark resistance series connection are between the input and output of described operational amplifier;

Described zero mark resistance is for generation of a zero point;

The zero point that described operational amplifier is used for described zero mark resistance to produce is associated with the limit that self finite bandwidth produces, and offsets described limit, realizes tracing compensation.

The embodiment of the present invention also provides a kind of broadband filter, described filter comprises the compensation integrator described in two, be respectively the first compensation integrator and second and compensate integrator, the input of the second compensation integrator described in the output termination of described first compensation integrator;

Described filter also comprises the 3rd resistance and the 4th resistance;

Described 3rd resistance is connected between the described first input compensating the operational amplifier of integrator and output, and described 4th resistance is connected on the described first input and described second compensating the operational amplifier of integrator and compensates between the output of the operational amplifier of integrator.

The embodiment of the present invention also provides a kind of broadband analogue chip, and described chip comprises described broadband filter.

According to specific embodiment provided by the invention, the invention discloses following technique effect:

In the embodiment of the present invention, by a zero mark resistance of connecting for described integrating capacitor, produce Left half-plane zero point, utilize the limit that the finite bandwidth of offsetting described operational amplifier this zero point produces integrator, thus because of impact that the finite bandwidth of operational amplifier brings in elimination filter, and by Current Control tail current source, zeros and poles is associated, realize tracing compensation.

Adopt the embodiment of the present invention, its scheme implementation is simple, only needs the current source increasing zero mark resistance and associate with amplifier bandwidth, does not need extra complicated calibration circuit, and circuit is easy to realize.

Accompanying drawing explanation

Fig. 1 is the circuit diagram of the tracing compensation integrator of the embodiment of the present invention;

Fig. 2 is a kind of implementation circuit diagram of the operational amplifier of the embodiment of the present invention;

Fig. 3 is a kind of implementation circuit diagram of the tail current source of the embodiment of the present invention;

Fig. 4 is the another kind of implementation circuit diagram of the tail current source of the embodiment of the present invention;

Fig. 5 is the circuit diagram of the broadband filter of the embodiment of the present invention.

Embodiment

For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, and below in conjunction with the drawings and specific embodiments, the present invention is further detailed explanation.

The object of the present invention is to provide a kind of tracing compensation integrator, broadband filter and broadband analogue chip, this compensation integrator can realize the tracing compensation of zero point to the limit that operational amplifier finite bandwidth produces, thus because of the impact that amplifier finite bandwidth brings in elimination broadband filter, realize stable high bandwidth filter.

In the embodiment of the present invention, described tracing compensation integrator comprises operational amplifier, integrating resistor, integrating capacitor and zero mark resistance, described integrating resistor connects the input of described operational amplifier, and described integrating capacitor and zero mark resistance series connection are between the input and output of described operational amplifier.

Wherein, one end that described integrating resistor is not connected with described operational amplifier is as the input of described compensation integrator, and the output of described operational amplifier is as the output of described compensation integrator.

Described zero mark resistance is for generation of a zero point.

The zero point that described operational amplifier is used for described zero mark resistance to produce is associated with the limit that self finite bandwidth produces, and offsets described limit, realizes tracing compensation.

In the embodiment of the present invention, by a zero mark resistance of connecting for described integrating capacitor, produce Left half-plane zero point, utilize the limit that the finite bandwidth of offsetting described operational amplifier this zero point produces integrator, thus because of impact that the finite bandwidth of operational amplifier brings in elimination filter, and by Current Control tail current source, zeros and poles is associated, realize tracing compensation.

With reference to Fig. 1, it is the circuit diagram of the tracing compensation integrator of the embodiment of the present invention.Described tracing compensation integrator can be difference form, and as shown in Figure 1, described operational amplifier is specially broadband operational amplifier.

Described tracing compensation integrator comprises: operational amplifier A, integrating resistor, integrating capacitor and zero mark resistance.

Described integrating resistor comprises first integral resistance R01 and second integral resistance R02; Described integrating capacitor comprises first integral electric capacity C01 and second integral electric capacity C02; Described zero mark resistance comprises first zero resistance Rz1 and the second zero mark resistance Rz2.

Described first integral resistance R01 connects the in-phase input end of described operational amplifier A, between the in-phase input end being connected on described operational amplifier A after described first integral electric capacity C01 connects with first zero resistance Rz1 and negative output terminal.

Described second integral resistance R02 connects the inverting input of described operational amplifier A, between the inverting input being connected on described operational amplifier A after described second integral electric capacity C02 connects with the second zero mark resistance Rz2 and positive output end.

Wherein, one end that described first integral resistance R01 is not connected with operational amplifier A and described second integral resistance R02 do not have one end of being connected with operational amplifier A as the input in of described compensation integrator, and the positive output end of described operational amplifier and negative output terminal are as the output out of described compensation integrator; This zero mark resistance is for generation of a zero point; The zero point that described operational amplifier is used for described zero mark resistance to produce is associated with the limit that self finite bandwidth produces, and offsets described limit, realizes tracing compensation.

Below the operation principle of the tracing compensation integrator described in the embodiment of the present invention is described in detail.

For traditional not for integrating capacitor series connection zero mark resistance integrator for, the ideal transfer of integrator is:

$H_i\left(s\right)=-\frac{1}{s{R}_0{C}_0}---\left(1\right)$

Wherein, R0 is integrating resistor; C0 is integrating capacitor.

For traditional integrator, when considering the imperfect bandwidth of operational amplifier, its transfer function is:

$H_p\left(s\right)=-\frac{A\left(s\right)}{1+{\mathrm{sR}}_0{C}_0(1+A\left(s\right))}=\frac{1}{{\mathrm{sR}}_0{C}_0(\frac{s}{A_0{\mathrm{\ω}}_0}+1+\frac{1}{A_0}+\frac{1}{A_0{\mathrm{\ω}}_0{C}_0{R}_0})+\frac{1}{A_0}}---\left(2\right)$

Wherein, A ₀> > 1, A ₀ω ₀c ₀r ₀> > 1, then formula (2) can be reduced to:

$H_p\left(s\right)\≈-\frac{1}{s{R}_0{C}_0(1+\frac{s}{A_0{\mathrm{\ω}}_0})}---\left(3\right)$

And the tracing compensation integrator described in the embodiment of the present invention, for integrating capacitor C0 connects a zero mark resistance Rz, be equivalent on the basis of traditional quadrature device, integrating capacitor replaced with the form of resistance capacitance series connection, now, the transfer function compensating integrator is:

$H_c\left(s\right)\≈-\frac{1+{\mathrm{sC}}_0{R}_z}{{\mathrm{sR}}_0{C}_0(1+\frac{s}{A_0{\mathrm{\ω}}_0})}---\left(4\right)$

Limit in the zero point making described zero mark resistance Rz produce and above formula (4) is equal, just can realize zero point to the compensation of imperfect limit and counteracting, when realizing offsetting completely, has:

$C_0{R}_z=\frac{1}{A_0{\mathrm{\ω}}_0}---\left(5\right)$

In order to the tracing compensation of antipodal points at zero point in tracing compensation integrator can be realized, only need formula (50) both sides to associate, associate by zeros and poles, just can eliminate in filter because of impact that amplifier finite bandwidth brings.

In the embodiment of the present invention, the broadband operational amplifier that described operational amplifier A can adopt tail current to control.With reference to Fig. 2, it is a kind of implementation circuit diagram of the operational amplifier of the embodiment of the present invention.It should be noted that, circuit shown in Fig. 2 is only a kind of specific implementation circuit diagram of operational amplifier, and in other embodiments of the present invention, described operational amplifier can also circuit realiration by other means.

Operational amplifier shown in Fig. 2 is the broadband operational amplifier that tail current controls, and is one-pole system.Described operational amplifier can be made up of one-level or dual-stage amplifier, and Fig. 2 is described for two-stage system.

As shown in Figure 2, described operational amplifier comprises: third transistor M3, the 4th transistor M4, the 5th transistor M5, the 6th transistor M6, the first triode T1, the second triode T2, the first miller capacitance Cc1, the second miller capacitance Cc2, tail current source I ₀, the first current source load Is1, the second current source load Is2.

The described grid of the 4th transistor M4 and the grid short circuit of third transistor M3, the drain electrode of described 4th transistor M4 connects the collector electrode of described second triode T2, and the drain electrode of described third transistor M3 connects the collector electrode of described first triode T1.

The emitter of described second triode T2 and the collector electrode of described first triode T1 meet described tail current source I jointly ₀first end.

The grid of described 5th transistor M5 connects the drain electrode of described third transistor M3, and the drain electrode of described 5th transistor M5 connects the first end of described first current source load Is1.

The grid of described 6th transistor M6 connects the drain electrode of described 4th transistor M4, and the drain electrode of described 6th transistor M6 connects the first end of described second current source load Is2.

The source electrode of described 4th transistor M4, the source electrode of third transistor M3, the source electrode of the 5th transistor M5 and the source electrode of the 6th transistor M6 connect working power jointly; Described tail current source I ₀the second end, second end of the first current source load Is1 and the second end common ground of the second current source load Is2.

Described first miller capacitance Cc1 is connected between the grid of described 5th transistor M5 and drain electrode; Described second miller capacitance Cc2 is connected between the grid of described 6th transistor M6 and drain electrode.

Wherein, the base stage of described first triode T1 and the base stage of the second triode T2 are as the input of described operational amplifier, and the first end of described first current source load Is1 and the first end of the second current source load Is2 are as the output of described operational amplifier.

The broadband operational amplifier that tail current shown in Fig. 2 controls is made up of dual-stage amplifier.The first order is input stage, by bipolar devices first triode T1, the second triode T2, tail current source I ₀, and third transistor M3 and the 4th transistor M4 is formed; The second level is driving stage, is made up of the 5th transistor M5, the 6th transistor M6 and the first current source load Is1 and the second current source load Is2.

Wherein, described third transistor M3 and the 4th transistor M4 plays the effect of current source, and Vbias shown in Fig. 2 is for current source M3 and M4 provides biased fixed level.

Wherein, the drain electrode of described third transistor M3 and the drain electrode of the 4th transistor M4 are the output of the first order, and the drain electrode of described 5th transistor M5 and the drain electrode of the 6th transistor M6 are the output of the second level.Described first miller capacitance Cc1 and the second miller capacitance Cc2 is connected across between the output of the first order and the output of the second level.

The broadband operational amplifier that tail current shown in Fig. 2 controls is an one-pole system, and its transfer function is:

$A\left(s\right)=\frac{A_0{\mathrm{\ω}}_0}{s+{\mathrm{\ω}}_0}---\left(6\right)$

Wherein, A ₀for the DC current gain of operational amplifier, ω ₀for the dominant pole frequency of operational amplifier; Then A ₀ω ₀gain for operational amplifier drops to bandwidth during unit gain, is called that unity gain bandwidth amasss GBP.

The unity gain bandwidth of operational amplifier shown in Fig. 2 is amassed GBP and can be determined by the ratio of input stage mutual conductance and miller capacitance, that is:

$\mathrm{GBP}=\frac{1}{A_0{\mathrm{\ω}}_0}=\frac{g_m}{C_c}=\frac{I_0}{V_T{k}_1{C}_0}---\left(7\right)$

Wherein, g _mfor the function of biased tail current source,

Make miller capacitance (the first miller capacitance Cc1 and the second miller capacitance Cc2) proportional with the integrating capacitor compensated in integrator, that is: C _c=k ₁c ₀.

Tail current source I in operational amplifier shown in Fig. 2 ₀multiple generation form can be had, below with tail current source I ₀two kinds of specific implementation forms be that example is described.

With reference to Fig. 3, it is a kind of implementation circuit diagram of the tail current source of the embodiment of the present invention.It should be noted that, the tail current source shown in Fig. 3 realizes producing with the bias current generating circuit of zero mark resistance and temperature correlation by one.

As shown in Figure 3, described bias current generating circuit comprises: the 11 transistor M11, the tenth two-transistor M12, the 13 transistor M13, the 14 transistor M14, the 15 transistor M15, the 16 transistor M16, the 3rd triode T3, the 4th triode T4, the first resistance Rt1.

The source shorted of described 11 transistor M11, the tenth two-transistor M12, the 13 transistor M13, the door short circuit of described 11 transistor M11, the tenth two-transistor M12, the 13 transistor M13.

The drain and gate short circuit of described 11 transistor M11, the drain electrode of described 11 transistor M11 connects the collector electrode of the 3rd triode T3; The emitter of described 3rd triode T3 through the first temperature and resistance Rt1 ground connection, the base stage of described 3rd triode T3 and the base stage short circuit of the 4th transistor T4.

The drain electrode of described tenth two-transistor M12 connects the collector electrode of the 4th triode T4, the base stage of described 4th triode T4 and collector electrode short circuit, the grounded emitter of the 4th triode T4.

The drain electrode of described 13 transistor M13 connects the drain electrode of the 14 transistor M14, the drain and gate short circuit of described 14 transistor M14.

The grid short circuit of described 14 transistor M14, the 15 transistor M15, the 16 transistor M16, the source electrode common ground of described 14 transistor M14, the 15 transistor M15, the 16 transistor M16.

The drain electrode of described 15 transistor M15 drain electrode and the 16 transistor M16 is as described tail current source I ₀first end.

Tail current source shown in Fig. 3 is the bias current generating circuit of a realization and zero mark resistance and temperature correlation.Wherein, the 3rd triode T3 and the 4th triode T4 is all bipolarity triodes of NPN type, and its area ratio is A.Zero mark resistance in first resistance Rt1 and described compensation integrator is of the same type and proportional.Described 11 transistor M11, the tenth two-transistor M12, the 13 transistor M13, the 14 transistor M14 are the current mirror realizing current mirror.The described drain electrode of the 15 transistor M15 and the drain electrode of the 16 transistor M16 are as the first end of described tail current source.

Explaination explanation is carried out to the operation principle of tail current source shown in Fig. 3 below.

In Fig. 3, the area ratio of the 3rd triode T3 and the 4th triode T4 is A, then the electric current produced at the 14 transistor M14 is:

$I=\frac{V_T\ln A}{R_t}---\left(8\right)$

The electric current of described 15 transistor M15 and the 16 transistor M16 and the current in proportion shown in formula (8), as the tail current source I of the operational amplifier compensated in integrator ₀electric current.First resistance Rt1 is proportional with the zero mark resistance compensated in integrator, i.e. R _t=k ₂r _z, then have:

$I_0=\frac{k_3{V}_T\ln A}{k_2{R}_z}---\left(9\right)$

Wherein, I ₀for the electric current of tail current source; R _zfor compensating the zero mark resistance of integrator; k ₂, k ₃for constant.Comprehensive above-mentioned formula (5), (7), (9), when zero pole point is offset, draw:

$\frac{k_3\ln A}{k_1{k}_2}\·\frac{C_0}{C}=1---\left(10\right)$

Can find out, the equation left side of above formula (10) is every is constant, show to compensate integrator on technique the impact of scattered and temperature insensitive, achieve zero point to operational amplifier finite bandwidth at the tracing compensation compensating the limit formed in integrator.

Tail current source shown in Fig. 3 and zero mark resistance and temperature correlation, when variations in temperature is little, described tail current source also can adopt circuit realiration shown in Fig. 4.

With reference to Fig. 4, it is the another kind of implementation circuit diagram of the tail current source of the embodiment of the present invention.It should be noted that, the tail current source shown in Fig. 4 realizes the reference bias current relevant to zero mark resistance by one and produces circuit generation.

As shown in Figure 4, described bias current generating circuit comprises: the 21 transistor M21, the 20 two-transistor M22, the 23 transistor M23, the 24 transistor M24, the 25 transistor M25, the 26 transistor M26, the second amplifier U2, the second resistance Rt2.

The source shorted of described 21 transistor M21, the 20 two-transistor M22, the grid short circuit of described 21 transistor M21, the 20 two-transistor M22, the grid of described 21 transistor M21 and drain electrode short circuit.

The drain electrode of described 21 transistor M21 connects the drain electrode of the 23 transistor M23, and the grid of described 23 transistor M23 connects the output of the second amplifier U2; The in-phase input end of described second amplifier U2 meets reference voltage V bg, the source electrode of anti-phase input termination the 23 transistor M23 of the second amplifier U2.

The source electrode of the 23 transistor M23 is through the second resistance Rt2 ground connection.

The drain electrode of described 20 two-transistor M22 connects the drain electrode of the 24 transistor M24, the drain and gate short circuit of described 24 transistor M24.

The grid short circuit of described 24 transistor M24, the 25 transistor M25, the 26 transistor M26, the source electrode common ground of described 24 transistor M24, the 25 transistor M25, the 26 transistor M26.

The drain electrode of described 25 transistor M25 drain electrode and the 26 transistor M26 is as described tail current source I ₀first end.

In tail current source shown in Fig. 4, the second amplifier U2 is base amplifier, and the output of current mirror is the ratio of reference voltage and the second resistance Rt2.Described 21 transistor M21, the 20 two-transistor M22, the 23 transistor M23, the 24 transistor M24 are current mirror, and the drain electrode of described 25 transistor M25 drain electrode and the 26 transistor M26 is as described tail current source I ₀first end.

Circuit shown in above-mentioned Fig. 3 and Fig. 4 is only two kinds of specific implementation circuit diagrams of operational amplifier, and in other embodiments of the present invention, described operational amplifier can also circuit realiration by other means.

Tracing compensation integrator described in the embodiment of the present invention, by increasing the method can following the tracks of the zero point of operational amplifier bandwidth, counteracts the finite bandwidth of operational amplifier to the impact of broadband filter transfer function.Compensate counteracting method that integrator adopts described in the embodiment of the present invention discrete and variations in temperature is insensitive to technique, and when filter bandwidht is not very wide, power consumption can be reduced by the operational amplifier adopting smaller strip wide.Tracing compensation integrator described in the embodiment of the present invention, its scheme implementation is simple, and only needing increases zero mark resistance, does not need extra complicated calibration circuit, enhances the competitiveness of circuit scheme.

Corresponding to the compensation integrator that the embodiment of the present invention provides, the embodiment of the present invention also provides a kind of broadband filter.Described broadband filter adopts the compensation integrator as described in aforementioned any embodiment.

Described broadband filter can be two step low-pass or band pass filter.Described broadband filter comprises the compensation integrator described in two, is respectively the first compensation integrator and second and compensates integrator; The input of the second compensation integrator described in the output termination of described first compensation integrator.

Described broadband filter also comprises the 3rd resistance and the 4th resistance.

Described 3rd resistance is connected between the described first input compensating the operational amplifier of integrator and output, and described 4th resistance is connected on the described first input and described second compensating the operational amplifier of integrator and compensates between the output of the operational amplifier of integrator.

Described compensation integrator can for the compensation integrator described in aforementioned any embodiment.

Broadband filter described in the embodiment of the present invention, adopt and compensate integrator, by a zero mark resistance of connecting for the integrating capacitor of described compensation integrator, produce Left half-plane zero point, utilize the limit that the finite bandwidth of offsetting described operational amplifier this zero point produces integrator, thus eliminate in filter because of impact that the finite bandwidth of operational amplifier brings.

Be described for biquadratic filter.With reference to Fig. 5, it is the circuit diagram of the broadband filter of the embodiment of the present invention.The compensation integrator of the difference form shown in Fig. 1 is adopted in broadband filter shown in Fig. 5.

As shown in Figure 5, described broadband filter comprises: first compensates integrator, second compensates integrator, the 3rd resistance and the 4th resistance.

For the compensation integrator of difference form, its 3rd resistance comprises the one or three resistance R13 and the two or three resistance R23; 4th resistance comprises the one or four resistance R14 and the two or four resistance R24.

The annexation that described first device compensating integrator and the second compensation integrator is formed between each device is same as shown in Figure 1, does not repeat them here.

The described first positive output termination second compensating integrator compensates the in-phase input end of integrator, and the described first negative output termination second compensating integrator compensates the inverting input of integrator.

Described one or three resistance R13 is connected between the described first in-phase input end compensating the operational amplifier of integrator and negative output terminal, and described one or four resistance R14 is connected on the described first in-phase input end and second compensating the operational amplifier of integrator and compensates between the negative output terminal of the operational amplifier of integrator.

Described two or three resistance R23 is connected between the described first inverting input compensating the operational amplifier of integrator and positive output end, and described two or four resistance R24 is connected on the described first inverting input and second compensating the operational amplifier of integrator and compensates between the positive output end of the operational amplifier of integrator.

Wherein, the input of described first integral compensator is as the input input of described filter, the output of described first integral compensator is as the first order output output1 of described filter, and the output of described second integral device is as the second level output output2 of described filter.

Filter shown in Fig. 5 is two step low-pass or band pass filter.A kind of specific implementation form of broadband filter of what Fig. 5 provided is the only compensation integrator utilized described in the embodiment of the present invention, in other embodiments of the present invention, described broadband filter can also adopt other forms to realize.

The embodiment of the present invention also provides a kind of broadband analogue chip, and described chip comprises the broadband filter as described in above-described embodiment.

The technical scheme that the embodiment of the present invention provides is with a wide range of applications in the integrated simulation broadband filters such as terminal LTE chip, microwave communication chip and base station ic.

Above to a kind of tracing compensation integrator broadband filter provided by the present invention and broadband analogue chip, be described in detail, apply specific case herein to set forth principle of the present invention and execution mode, the explanation of above embodiment just understands method of the present invention and core concept thereof for helping; Meanwhile, for one of ordinary skill in the art, according to thought of the present invention, all will change in specific embodiments and applications.In sum, this description should not be construed as limitation of the present invention.

Claims (9)

1. compensate an integrator, it is characterized in that, described compensation integrator comprises: operational amplifier, integrating resistor and integrating capacitor and zero mark resistance;

Described integrating resistor connects the input of described operational amplifier, and described integrating capacitor and described zero mark resistance series connection are between the input and output of described operational amplifier;

Described zero mark resistance is for generation of Left half-plane zero point;

The zero point that described operational amplifier is used for described zero mark resistance to produce is associated with the limit that self finite bandwidth produces, and offsets described limit, realizes tracing compensation;

Described operational amplifier is the broadband operational amplifier that tail current controls.

2. compensation integrator according to claim 1, is characterized in that, described integrating resistor comprises first integral resistance and second integral resistance; Described integrating capacitor comprises first integral electric capacity and second integral electric capacity; Described zero mark resistance comprises first zero resistance and the second zero mark resistance;

Described first integral resistance connects the in-phase input end of described operational amplifier, between the in-phase input end being connected on described operational amplifier after described first integral electric capacity and first zero resistant series and negative output terminal;

Described second integral resistance connects the inverting input of described operational amplifier, between the inverting input that described second integral electric capacity is connected on described operational amplifier after connecting with the second zero mark resistance and positive output end.

3. compensation integrator according to claim 1, it is characterized in that, described operational amplifier comprises: third transistor, the 4th transistor, the 5th transistor, the 6th transistor, the first triode, the second triode, the first miller capacitance, the second miller capacitance, tail current source, the first current source load, the second current source load;

The described grid of the 4th transistor and the grid short circuit of third transistor, the drain electrode of described 4th transistor connects the collector electrode of described second triode, and the drain electrode of described third transistor connects the collector electrode of described first triode;

The emitter of described second triode and the emitter of described first triode connect the first end of described tail current source jointly;

The grid of described 5th transistor connects the drain electrode of described third transistor, and the drain electrode of described 5th transistor connects the first end of described first current source load;

The grid of described 6th transistor connects the drain electrode of described 4th transistor, and the drain electrode of described 6th transistor connects the first end of described second current source load;

The source electrode of described 4th transistor, the source electrode of third transistor, the source electrode of the 5th transistor and the source electrode of the 6th transistor connect working power jointly; Second end common ground of the second end of described tail current source, the second end of the first current source load and the second current source load;

Described first miller capacitance is connected between the grid of described 5th transistor and drain electrode; Described second miller capacitance is connected between the grid of described 6th transistor and drain electrode.

4. compensation integrator according to claim 3, is characterized in that, described tail current source becomes positively related bias current generating circuit to produce with described zero mark resistance with temperature by one.

5. compensation integrator according to claim 4, it is characterized in that, described bias current generating circuit comprises: the 11 transistor, the tenth two-transistor, the 13 transistor, the 14 transistor, the 15 transistor, the 16 transistor, the 3rd triode, the 4th triode, the first resistance;

The source shorted of described 11 transistor, the tenth two-transistor, the 13 transistor, the grid short circuit of described 11 transistor, the tenth two-transistor, the 13 transistor;

The drain and gate short circuit of described 11 transistor, the drain electrode of described 11 transistor connects the collector electrode of the 3rd triode; The emitter of described 3rd triode through the first grounding through resistance, the base stage of described 3rd triode and the base stage short circuit of the 4th transistor;

The drain electrode of described tenth two-transistor connects the collector electrode of the 4th triode, the base stage of described 4th triode and collector electrode short circuit, the grounded emitter of the 4th triode;

The drain electrode of described 13 transistor connects the drain electrode of the 14 transistor, the drain and gate short circuit of described 14 transistor;

The grid short circuit of described 14 transistor, the 15 transistor, the 16 transistor, the source electrode common ground of described 14 transistor, the 15 transistor, the 16 transistor;

The described drain electrode of the 15 transistor and the drain electrode of the 16 transistor are as the first end of described tail current source.

6. compensation integrator according to claim 3, is characterized in that, described tail current source becomes positively related bias current generating circuit to produce by one with described zero mark resistance.

7. compensation integrator according to claim 6, it is characterized in that, described bias current generating circuit comprises: the 21 transistor, the 20 two-transistor, the 23 transistor, the 24 transistor, the 25 transistor, the 26 transistor, the second amplifier, the second resistance;

The source shorted of described 21 transistor, the 20 two-transistor, the grid short circuit of described 21 transistor, the 20 two-transistor, the grid of described 21 transistor and drain electrode short circuit;

The drain electrode of described 21 transistor connects the drain electrode of the 23 transistor, and the grid of described 23 transistor connects the output of the second amplifier; The in-phase input end of described second amplifier connects reference voltage, the source electrode of anti-phase input termination the 23 transistor of the second amplifier;

The source electrode of the 23 transistor is through the second grounding through resistance;

The drain electrode of described 20 two-transistor connects the drain electrode of the 24 transistor, the drain and gate short circuit of described 24 transistor;

The grid short circuit of described 24 transistor, the 25 transistor, the 26 transistor, the source electrode common ground of described 24 transistor, the 25 transistor, the 26 transistor;

The drain electrode of described 25 transistor drain and the 26 transistor is as the first end of described tail current source.

8. a broadband filter, it is characterized in that, described filter comprises two compensation integrators as described in any one of claim 1 to 7, is respectively the first compensation integrator and second and compensates integrator, the input of the second compensation integrator described in the output termination of described first compensation integrator;

Described filter also comprises the 3rd resistance and the 4th resistance;

Described 3rd resistance is connected between the described first input compensating the operational amplifier of integrator and output, and described 4th resistance is connected on the described first input and described second compensating the operational amplifier of integrator and compensates between the output of the operational amplifier of integrator.

9. a broadband analogue chip, is characterized in that, described chip comprises broadband filter as claimed in claim 8.