CN102593158A - Flash memory unit structure and flash memory device - Google Patents
Flash memory unit structure and flash memory device Download PDFInfo
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- CN102593158A CN102593158A CN2012100619652A CN201210061965A CN102593158A CN 102593158 A CN102593158 A CN 102593158A CN 2012100619652 A CN2012100619652 A CN 2012100619652A CN 201210061965 A CN201210061965 A CN 201210061965A CN 102593158 A CN102593158 A CN 102593158A
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Abstract
The invention provides a flash memory unit structure and a flash memory device. According to the invention, the flash memory unit structure comprises an L-shaped ONO (oxide-nitride-oxide) structure, a control grid polycrystalline silicon arranged on a right-angle inner side of the L-shaped ONO structure, a silicon dioxide region which is arranged on the other side of the control grid polycrystalline silicon relative to the L-shaped ONO structure, a word line polycrystalline silicon which is arranged on the other side of the silicon dioxide region relative to the control grid polycrystalline silicon and a bit line which is arranged on the other side of the L-shaped ONO structure relative to the control grid polycrystalline silicon. The novel flash memory unit structure and the flash memory device provided by the invention fully utilize the size of the vertical direction of the silicon substrate, realize L-shaped channel, utilize the ONO structure as a storage material, and can finish reading, writing and smearing writing operations; and compared with the conventional flash memory device, the main part of a device channel is positioned on the vertical direction of the silicon substrate, thereby being beneficial to shortening device size, and increasing the device integration density.
Description
Technical field
The present invention relates to semiconductor applications, more particularly, the flash memory device that the present invention relates to a kind of flash memory unit structure and adopted this flash memory unit structure.
Background technology
Flash memory is convenient with it, and storage density is high, and advantages such as good reliability become the focus of studying in the non-volatility memorizer.
Since first flash memory products comes out from the 1980s; Along with the development and the demand of each electronic product to storage of technology, flash memory is widely used in mobile phone, notebook; Palmtop PC and USB flash disk etc. move with communication apparatus in, flash memory is a kind of nonvolatile memory.
The operation principles of flash memory be control the gate pole passage through the critical voltage that changes transistor or memory cell switch to reach the purpose of storage data; Make the data that are stored in the memory can be, and flash memory be a kind of special construction of electric erasable and programmable read-only memory because of power interruptions does not disappear.
Nowadays flash memory has occupied most of market share of non-volatile semiconductor memory, becomes non-volatile semiconductor memory with fastest developing speed.
Progress along with consumption electronic product and commercial electronic product etc.; For miniaturization and the portability that realizes consumption electronic product and commercial electronic product; Hope further miniaturization of storage device wherein; Promptly for flash memory device, hope can reduce device size, increase the device integration density.
Summary of the invention
Technical problem to be solved by this invention is to have above-mentioned defective in the prior art, and a kind of help reducing device size, the flash memory unit structure that increases the device integration density and the flash memory device that has adopted this flash memory unit structure are provided.
According to a first aspect of the invention; A kind of flash memory unit structure is provided, and it comprises: L shaped ONO structure, be arranged in the inboard control grid polycrystalline silicon in the right angle of said L shaped ONO structure, be arranged in said control grid polycrystalline silicon the silicon dioxide region with respect to the opposite side of said L shaped ONO structure, be arranged in said silicon dioxide region with respect to the word line polysilicon of the opposite side of said control grid polycrystalline silicon and the bit line that is arranged in said L shaped ONO structure with respect to the opposite side of said control grid polycrystalline silicon.
Preferably, another flash memory unit structure common word line polysilicon of said flash memory unit structure and word line polysilicon side.
Preferably, said flash memory unit structure and said another flash memory unit structure are with respect to the symmetry axis symmetric arrangement of said shared word line polysilicon.
Preferably, when said flash memory unit structure is wiped, bit line is suspended, the control grid polycrystalline silicon is added-voltage of 8V, the substrate at said flash memory unit structure place is added the voltage of 8V.
Preferably, when said flash memory unit structure was programmed, pairs of bit line added the voltage of 5V, and the control grid polycrystalline silicon is added the voltage of 8V, and the substrate at said flash memory unit structure place is added the voltage of 0V, the word line polysilicon was added the voltage of 1.5V.
Preferably, when said flash memory unit structure was read, pairs of bit line added the voltage of 1V, and the control grid polycrystalline silicon is added the voltage of 0V, and the substrate at said flash memory unit structure place is added the voltage of 0V, the word line polysilicon was added the voltage of 3V.
Preferably, when said flash memory unit structure is programmed, the bit line of said another flash memory unit structure is added the voltage that size equals Vdp, the control grid polycrystalline silicon 2 of said another flash memory unit structure is added the voltage of 5V.
Preferably, when said flash memory unit structure is read, the bit line of said another flash memory unit structure is added the voltage of 0V, the control grid polycrystalline silicon of said another flash memory unit structure is added the voltage of 5V.
According to a second aspect of the invention, a kind of flash memory device that has adopted according to the described flash memory unit structure of first aspect present invention is provided.
The present invention proposes a kind of novel flash memory unit structure and flash memory device, makes full use of the size of silicon substrate vertical direction, realizes the raceway groove of " L " shape, utilizes the ONO structure as storage medium, can accomplish reading and writing, put the operation of writing on the skin.Compare with the conventional flash memory device, the major part of device channel is positioned at the silicon substrate vertical direction, can more help reducing device size like this, increases the device integration density.
Description of drawings
In conjunction with accompanying drawing, and, will more easily more complete understanding be arranged and more easily understand its attendant advantages and characteristic the present invention through with reference to following detailed, wherein:
Fig. 1 schematically shows the flash memory unit structure according to the embodiment of the invention.
Fig. 2 schematically shows flash memory unit structure according to another embodiment of the present invention.
Need to prove that accompanying drawing is used to explain the present invention, and unrestricted the present invention.Notice that the accompanying drawing of expression structure possibly not be to draw in proportion.And in the accompanying drawing, identical or similar elements indicates identical or similar label.
Embodiment
In order to make content of the present invention clear more and understandable, content of the present invention is described in detail below in conjunction with specific embodiment and accompanying drawing.
Fig. 1 schematically shows the flash memory unit structure according to the embodiment of the invention.
As shown in Figure 1; Flash memory unit structure according to the embodiment of the invention comprises: L shaped ONO (Oxide-Nitride-Oxide, silicon dioxide/silicon nitride/silicon dioxide) structure 1, be arranged in the inboard control grid polycrystalline silicon 2 in the right angle of L shaped ONO structure 1, be arranged in control grid polycrystalline silicon 2 the silicon dioxide region 3 with respect to the opposite side of L shaped ONO structure 1, be arranged in silicon dioxide region 3 with respect to the word line polysilicon 4 of the opposite side of control grid polycrystalline silicon 2 and the bit line 5 that is arranged in L shaped ONO structure 1 with respect to the opposite side of control grid polycrystalline silicon 2.
Further, when the flash memory unit structure according to the embodiment of the invention shown in Figure 1 is wiped, bit line 5 is suspended, control grid polycrystalline silicon 2 is added-voltage of 8V, the substrate at flash memory unit structure place is added the voltage of 8V.
When the flash memory unit structure according to the embodiment of the invention shown in Figure 1 is programmed; Pairs of bit line 5 adds the voltage of 5V; Control grid polycrystalline silicon 2 is added the voltage of 8V, the substrate at flash memory unit structure place is added the voltage of 0V, word line polysilicon 4 is added the voltage of 1.5V.
When the flash memory unit structure according to the embodiment of the invention shown in Figure 1 is read; Pairs of bit line 5 adds the voltage of 1V; Control grid polycrystalline silicon 2 is added the voltage of 0V, the substrate at flash memory unit structure place is added the voltage of 0V, word line polysilicon 4 is added the voltage of 3V.
Further, Fig. 2 schematically shows flash memory unit structure according to another embodiment of the present invention.As shown in Figure 2, preferably, another flash memory unit structure common word line polysilicon of above-mentioned flash memory unit structure and word line polysilicon side.
And preferably as shown in Figure 2, said flash memory unit structure and said another flash memory unit structure are with respect to the symmetry axis A-A symmetric arrangement of said shared word line polysilicon.Thus, the symmetry axis A-A of said shared word line polysilicon also is the symmetry axis of said flash memory unit structure and said another flash memory unit structure.
For flash memory unit structure according to another embodiment of the present invention shown in Figure 2; Similarly; When flash memory unit structure shown in Figure 2 is wiped; The bit line 5 of said flash memory unit structure and said another flash memory unit structure is suspended, the control grid polycrystalline silicon 2 of said flash memory unit structure and said another flash memory unit structure is all added-voltage of 8V, the substrate that said flash memory unit structure and said another flash memory unit structure are belonged to all adds the voltage of 8V.
When a flash memory unit structure in the flash memory unit structure according to another embodiment of the present invention shown in Figure 2 is programmed; Flash memory unit structure for programming; Pairs of bit line 5 adds the voltage of 5V; Control grid polycrystalline silicon 2 is added the voltage of 8V, the substrate at flash memory unit structure place is added the voltage of 0V, word line polysilicon 4 is added the voltage of 1.5V.And for the adjacent flash memory unit structure of flash memory unit structure of programming, pairs of bit line adds the voltage that size equals Vdp (Vdp is the voltage of the bit line of constant current when keeping programming, can regulate size automatically), the control grid polycrystalline silicon is added the voltage of 5V.
When a flash memory unit structure in the flash memory unit structure according to another embodiment of the present invention shown in Figure 2 is read; For the flash memory unit structure that is read; Pairs of bit line 5 adds the voltage of 1V; Control grid polycrystalline silicon 2 is added the voltage of 0V, the substrate at flash memory unit structure place is added the voltage of 0V, word line polysilicon 4 is added the voltage of 3V.And for the flash memory unit structure adjacent with the flash memory unit structure that is read, pairs of bit line adds the voltage of 0V, the control grid polycrystalline silicon is added the voltage of 5V.
According to another embodiment of the present invention, the present invention also provides a kind of flash memory device that has adopted above-mentioned flash memory unit structure shown in Figure 1 or shown in Figure 2.
It is understandable that though the present invention with the preferred embodiment disclosure as above, yet the foregoing description is not in order to limit the present invention.For any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the technology contents of above-mentioned announcement capable of using is made many possible changes and modification to technical scheme of the present invention, or is revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (9)
1. flash memory unit structure is characterized in that comprising: L shaped ONO structure, be arranged in the inboard control grid polycrystalline silicon in the right angle of said L shaped ONO structure, be arranged in said control grid polycrystalline silicon the silicon dioxide region with respect to the opposite side of said L shaped ONO structure, be arranged in said silicon dioxide region with respect to the word line polysilicon of the opposite side of said control grid polycrystalline silicon and the bit line that is arranged in said L shaped ONO structure with respect to the opposite side of said control grid polycrystalline silicon.
2. flash memory unit structure according to claim 1 is characterized in that, another flash memory unit structure common word line polysilicon of said flash memory unit structure and word line polysilicon side.
3. flash memory unit structure according to claim 2 is characterized in that, said flash memory unit structure and said another flash memory unit structure are with respect to the symmetry axis symmetric arrangement of said shared word line polysilicon.
4. according to the described flash memory unit structure of one of claim 1 to 3; It is characterized in that, when said flash memory unit structure is wiped, bit line is suspended; The control grid polycrystalline silicon is added-voltage of 8V, the substrate at said flash memory unit structure place is added the voltage of 8V.
5. according to the described flash memory unit structure of one of claim 1 to 3; It is characterized in that; When said flash memory unit structure was programmed, pairs of bit line added the voltage of 5V, the control grid polycrystalline silicon was added the voltage of 8V; The substrate at said flash memory unit structure place is added the voltage of 0V, the word line polysilicon is added the voltage of 1.5V.
6. according to the described flash memory unit structure of one of claim 1 to 3; It is characterized in that; When said flash memory unit structure was read, pairs of bit line added the voltage of 1V, the control grid polycrystalline silicon was added the voltage of 0V; The substrate at said flash memory unit structure place is added the voltage of 0V, the word line polysilicon is added the voltage of 3V.
7. flash memory unit structure according to claim 3; It is characterized in that; When said flash memory unit structure is programmed, the bit line of said another flash memory unit structure is added the voltage that size equals Vdp, the control grid polycrystalline silicon 2 of said another flash memory unit structure is added the voltage of 5V.
8. flash memory unit structure according to claim 3; It is characterized in that; When said flash memory unit structure is read, the bit line of said another flash memory unit structure is added the voltage of 0V, the control grid polycrystalline silicon of said another flash memory unit structure is added the voltage of 5V.
9. one kind has been adopted the flash memory device according to the described flash memory unit structure of one of claim 1 to 5.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111370420A (en) * | 2020-03-18 | 2020-07-03 | 上海华虹宏力半导体制造有限公司 | Preparation method of SONOS (silicon oxide nitride oxide semiconductor) memory device and SONOS memory device |
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| US5414287A (en) * | 1994-04-25 | 1995-05-09 | United Microelectronics Corporation | Process for high density split-gate memory cell for flash or EPROM |
| CN1954433A (en) * | 2004-05-10 | 2007-04-25 | 微米技术股份有限公司 | NROM device |
| CN101419972A (en) * | 2008-11-13 | 2009-04-29 | 上海宏力半导体制造有限公司 | High-efficient erasing and writing flash memory in grating |
| CN101465161A (en) * | 2008-12-30 | 2009-06-24 | 上海宏力半导体制造有限公司 | Gate-division type flash memory sharing word line |
-
2012
- 2012-03-09 CN CN201210061965.2A patent/CN102593158B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5414287A (en) * | 1994-04-25 | 1995-05-09 | United Microelectronics Corporation | Process for high density split-gate memory cell for flash or EPROM |
| CN1954433A (en) * | 2004-05-10 | 2007-04-25 | 微米技术股份有限公司 | NROM device |
| CN101419972A (en) * | 2008-11-13 | 2009-04-29 | 上海宏力半导体制造有限公司 | High-efficient erasing and writing flash memory in grating |
| CN101465161A (en) * | 2008-12-30 | 2009-06-24 | 上海宏力半导体制造有限公司 | Gate-division type flash memory sharing word line |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111370420A (en) * | 2020-03-18 | 2020-07-03 | 上海华虹宏力半导体制造有限公司 | Preparation method of SONOS (silicon oxide nitride oxide semiconductor) memory device and SONOS memory device |
| CN111370420B (en) * | 2020-03-18 | 2023-08-22 | 上海华虹宏力半导体制造有限公司 | Preparation method of SONOS memory device and SONOS memory device |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140504 |
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