CN102569274A - Semiconductor package structure and manufacturing method thereof - Google Patents
Semiconductor package structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN102569274A CN102569274A CN2012100763456A CN201210076345A CN102569274A CN 102569274 A CN102569274 A CN 102569274A CN 2012100763456 A CN2012100763456 A CN 2012100763456A CN 201210076345 A CN201210076345 A CN 201210076345A CN 102569274 A CN102569274 A CN 102569274A
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- China
- Prior art keywords
- substrate
- weld pad
- sealing
- tube core
- semiconductor package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/93—Batch processes
- H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention relates to a semiconductor package structure and a manufacturing method thereof. The semiconductor package structure comprises a first substrate, a first tube core, first sealing glue, a second substrate and at least one conduction column, wherein the first tube core is electrically connected to the upper surface of the first substrate; the first sealing glue covers the upper surfaces of the first tube core and the first substrate; the lower surface of the second substrate is adhered to the first sealing glue; the conduction columns pass through the first substrate, the first sealing glue and the second substrate; and the conduction columns are used as assemblies which are electrically connected in the vertical direction, and thus the distance between every two conduction columns can be shortened.
Description
Technical field
The present invention is about a kind of semiconductor package and manufacturing approach thereof, in detail, and about a kind of stack type semiconductor packaging structure and manufacturing approach thereof.
Background technology
Known stack type semiconductor packaging structure has encapsulating structure on, once encapsulating structure and a plurality of soldered ball.These soldered balls are positioned on the substrate of this time encapsulating structure.Should go up these soldered balls of lower surface contact of encapsulating structure, to be electrically connected to this time encapsulating structure.Therefore in this known stack type semiconductor packaging structure, these soldered balls are spherical, and the spacing between two soldered balls can't effectively be dwindled, otherwise easily bridge joint the takes place problem of (Bridge), and then cause the situation of short circuit.
Therefore, be necessary to provide a kind of semiconductor package and manufacturing approach thereof, to address the above problem.
Summary of the invention
The present invention provides a kind of semiconductor package, and it comprises one first substrate, one first tube core, one first sealing, one second substrate and at least one conduction column.This first substrate has a upper surface and a lower surface.This first tube core is adjacent to the upper surface of this first substrate, and is electrically connected to the upper surface of this first substrate.The upper surface of this first tube core of this first sealant covers and this first substrate.This second substrate has a upper surface and a lower surface, and the lower surface of this second substrate attaches in this first sealing.This conduction column runs through this first substrate, this first sealing and this second substrate.
In the present invention, the assembly of this conduction column in order to electrically connect as vertical direction.Because the external diameter of this conduction column is littler than known soldered ball, therefore can dwindle distance and increase density to each other.
The present invention provides a kind of manufacturing approach of semiconductor package in addition, and it may further comprise the steps: one first substrate (a) is provided, and this first substrate has a upper surface and a lower surface; (b) adhere to one first tube core in the upper surface of this first substrate, and electrically connect the upper surface of this first tube core to this first substrate; (c) form one first sealing to coat the upper surface of this first tube core and this first substrate; (d) one second substrate is provided, this second substrate has a upper surface and a lower surface, and the lower surface that sticks this second substrate is in this first sealing; (e) formation is at least always bored a hole to run through this first substrate, this first sealing and this second substrate; And (f) form a conducting metal in this at least one through hole to form at least one conduction column.
Description of drawings
Fig. 1 shows the sketch map of an embodiment of semiconductor package of the present invention; And
Fig. 2 to Figure 10 shows the sketch map of an embodiment of the manufacturing approach of semiconductor package of the present invention.
Embodiment
With reference to figure 1, show the sketch map of an embodiment of semiconductor package of the present invention.This semiconductor package 1 comprises one first substrate 10, one first tube core 12, many first leads 13, one first sealing 14, one second substrate 16, one second tube core 18, many second leads 19, one second sealing 20, at least one conduction column 22, an intermediate gelatine layer 24 and a plurality of soldered ball 26.
This first substrate 10, an organic substrate for example has weld pad 103 and at least one first time weld pad 104 on a upper surface 101, a lower surface 102, at least one first.This at least one first weld pad 103 be adjacent to the upper surface 101 of this first substrate 10, this at least one first time weld pad 104 is adjacent to the lower surface 102 of this first substrate 10.
This first tube core 12 is adjacent to the upper surface 101 of this first substrate 10, and is electrically connected to the upper surface 101 of this first substrate 10.In the present embodiment, this first tube core 12 utilizes one first glue-line 121 to attach to the upper surface 101 of this first substrate 10, and utilizes these first leads 13 to be electrically connected to the upper surface 101 of this first substrate 10.Yet in other embodiments, this first tube core 12 utilizes the flip chip bonding mode to be electrically connected to the upper surface 101 of this first substrate 10.
This first sealing 14 coats the upper surface 101 of this first tube core 12, these first leads 13 and this first substrate 10.This intermediate gelatine layer 24 is positioned at the upper surface of this first sealing 14, and wherein the surface area of this intermediate gelatine layer 24 equals the surface area of the upper surface of this first sealing 14 in fact.
This second substrate 16, an organic substrate for example has weld pad 163 and at least one second time weld pad 164 on a upper surface 161, a lower surface 162, at least one second.The lower surface 162 of this second substrate 16 utilizes this intermediate gelatine layer 24 to attach in this first sealing 14.This at least one second weld pad 163 be adjacent to the upper surface 161 of this second substrate 16, this at least one second time weld pad 164 is adjacent to the lower surface 162 of this second substrate 16.
This second tube core 18 is adjacent to the upper surface 161 of this second substrate 16, and is electrically connected to the upper surface 161 of this second substrate 16.In the present embodiment, this second tube core 18 utilizes one second glue-line 181 to attach to the upper surface 161 of this second substrate 16, and utilizes these second leads 19 to be electrically connected to the upper surface 161 of this second substrate 16.Yet in other embodiments, this second tube core 18 utilizes the flip chip bonding mode to be electrically connected to the upper surface 161 of this second substrate 16.
This second sealing 20 coats the upper surface 161 of this second tube core 18, these second leads 19 and this second substrate 16.
This at least one conduction column 22 runs through this first substrate 10, this first sealing 14 and this second substrate 16.In the present embodiment; The material of this at least one conduction column 22 is a copper; It runs through this weld pad 103 at least one first, this at least one first time weld pad 104, this weld pad 163 and this at least one second time weld pad 164 at least one second, and two ends of this at least one conduction column 22 are revealed in the lower surface 102 of this first substrate 10 and the upper surface 161 of this second substrate 16 respectively.
These soldered balls 26 are positioned on this at least one first time weld pad 104 of this first substrate 10, and are electrically connected to this at least one conduction column 22.
In the present embodiment, the assembly of this at least one conduction column 22 in order to electrically connect as vertical direction.Because the external diameter of this at least one conduction column 22 is littler than known soldered ball, therefore can dwindle distance and increase density to each other.
Referring to figs. 2 to Figure 10, the sketch map of an embodiment of the manufacturing approach of demonstration semiconductor package of the present invention.With reference to figure 2, one first substrate 10 is provided.This first substrate 10, an organic substrate for example has weld pad 103 and at least one first time weld pad 104 on a upper surface 101, a lower surface 102, at least one first.This at least one first weld pad 103 be adjacent to the upper surface 101 of this first substrate 10, this at least one first time weld pad 104 is adjacent to the lower surface 102 of this first substrate 10.
With reference to figure 3, adhere to the upper surface 101 of one first tube core 12, and electrically connect the upper surface 101 of this first tube core 12 to this first substrate 10 in this first substrate 10.In the present embodiment, this first tube core 12 utilizes one first glue-line 121 to attach to the upper surface 101 of this first substrate 10, and utilizes many first leads 13 to be electrically connected to the upper surface 101 of this first substrate 10.Yet in other embodiments, this first tube core 12 utilizes the flip chip bonding mode to be electrically connected to the upper surface 101 of this first substrate 10.
With reference to figure 4, form one first sealing 14 to coat the upper surface 101 of this first tube core 12, these first leads 13 and this first substrate 10.
With reference to figure 5, one second substrate 16 is provided.This second substrate 16, an organic substrate for example has weld pad 163 and at least one second time weld pad 164 on a upper surface 161, a lower surface 162, at least one second.The lower surface 162 of this second substrate 16 utilizes an intermediate gelatine layer 24 to attach in this first sealing 14, and wherein the surface area of this intermediate gelatine layer 24 equals the surface area of the upper surface of this first sealing 14 in fact.This at least one second weld pad 163 be adjacent to the upper surface 161 of this second substrate 16, this at least one second time weld pad 164 is adjacent to the lower surface 162 of this second substrate 16.
With reference to figure 6, form with machine drilling or laser drill mode and at least always to bore a hole 28 to run through this first substrate 10, this first sealing 14, this intermediate gelatine layer 24 and this second substrate 16.In the present embodiment, this at least one through hole 28 runs through this weld pad 103 at least one first, this at least one first time weld pad 104, this weld pad 163 and this at least one second time weld pad 164 at least one second.
With reference to figure 7, with plating mode form a conducting metal (for example copper) in this at least one through hole 28 to form at least one conduction column 22.This at least one conduction column 22 runs through this weld pad 103 at least one first, this first substrate 10, this at least one first time weld pad 104, this first sealing 14, this intermediate gelatine layer 24, this weld pad 163, this second substrate 16 and this at least one second time weld pad 164 at least one second, and two ends of this at least one conduction column 22 are revealed in the lower surface 102 of this first substrate 10 and the upper surface 161 of this second substrate 16 respectively.
With reference to figure 8, adhere to the upper surface 161 of one second tube core 18, and electrically connect the upper surface 161 of this second tube core 18 to this second substrate 16 in this second substrate 16.In the present embodiment, this second tube core 18 utilizes one second glue-line 181 to attach to the upper surface 161 of this second substrate 16, and utilizes many second leads 19 to be electrically connected to the upper surface 161 of this second substrate 16.Yet in other embodiments, this second tube core 18 utilizes the flip chip bonding mode to be electrically connected to the upper surface 161 of this second substrate 16.
With reference to figure 9, form one second sealing 20 to coat the upper surface 161 of this second tube core 18, these second leads 19 and this second substrate 16.Then, form a plurality of soldered balls 26 on this at least one first time weld pad 104 of this first substrate 10, to be electrically connected to this at least one conduction column 22.
With reference to Figure 10, carry out cutting step, cutting this first substrate 10, this first sealing 14, this intermediate gelatine layer 24, this second substrate 16 and this second sealing 20, and make a plurality of these semiconductor packages 1 as shown in Figure 1.
The foregoing description is merely explanation principle of the present invention and effect thereof, but not in order to restriction the present invention.Therefore, understanding this technological personage makes amendment to the foregoing description and changes and still do not take off spirit of the present invention.The claim scope that interest field Ying Ruhou of the present invention states is listed.
Claims (15)
1. semiconductor package comprises:
One first substrate has a upper surface and a lower surface;
One first tube core is adjacent to the upper surface of this first substrate, and is electrically connected to the upper surface of this first substrate;
One first sealing coats the upper surface of this first tube core and this first substrate;
One second substrate has a upper surface and a lower surface, and the lower surface of this second substrate attaches in this first sealing; And
At least one conduction column runs through this first substrate, this first sealing and this second substrate.
2. semiconductor package as claimed in claim 1; It is characterized in that; This first substrate also has weld pad and at least one first time weld pad at least one first; This at least one first weld pad be adjacent to the upper surface of this first substrate, this at least one first time weld pad is adjacent to the lower surface of this first substrate, and this at least one conduction column runs through this weld pad and this at least one first time weld pad at least one first.
3. semiconductor package as claimed in claim 1 is characterized in that, also comprises an intermediate gelatine layer, and the lower surface of this second substrate utilizes this intermediate gelatine layer to attach in this first sealing, and this at least one conduction column runs through this intermediate gelatine layer.
4. semiconductor package as claimed in claim 1; It is characterized in that; This second substrate also has weld pad and at least one second time weld pad at least one second; This at least one second weld pad be adjacent to the upper surface of this second substrate, this at least one second time weld pad is adjacent to the lower surface of this second substrate, and this at least one conduction column runs through this weld pad and this at least one second time weld pad at least one second.
5. semiconductor package as claimed in claim 1 is characterized in that, two ends of this at least one conduction column are revealed in the lower surface of this first substrate and the upper surface of this second substrate respectively.
6. semiconductor package as claimed in claim 1 is characterized in that, also comprises one second tube core, is adjacent to the upper surface of this second substrate, and is electrically connected to the upper surface of this second substrate.
7. semiconductor package as claimed in claim 6 is characterized in that, also comprises one second sealing, and it coats the upper surface of this second tube core and this second substrate.
8. the manufacturing approach of a semiconductor package may further comprise the steps:
(a) one first substrate is provided, this first substrate has a upper surface and a lower surface;
(b) adhere to one first tube core in the upper surface of this first substrate, and electrically connect the upper surface of this first tube core to this first substrate;
(c) form one first sealing to coat the upper surface of this first tube core and this first substrate;
(d) one second substrate is provided, this second substrate has a upper surface and a lower surface, and the lower surface that sticks this second substrate is in this first sealing;
(e) formation is at least always bored a hole to run through this first substrate, this first sealing and this second substrate; And
(f) form a conducting metal in this at least one through hole to form at least one conduction column.
9. manufacturing approach as claimed in claim 8; It is characterized in that in this step (a), this first substrate also has weld pad and at least one first time weld pad at least one first; This at least one first weld pad be adjacent to the upper surface of this first substrate; This at least one first time weld pad is adjacent to the lower surface of this first substrate, and in this step (e), and this at least one through hole runs through this weld pad and this at least one first time weld pad at least one first.
10. manufacturing approach as claimed in claim 8 is characterized in that, in this step (d), the lower surface of this second substrate utilizes an intermediate gelatine layer to attach in this first sealing; In this step (e), this at least one through hole runs through this intermediate gelatine layer; And in this step (f), this at least one conduction column runs through this intermediate gelatine layer.
11. manufacturing approach as claimed in claim 8; It is characterized in that in this step (d), this second substrate also has weld pad and at least one second time weld pad at least one second; This at least one second weld pad be adjacent to the upper surface of this second substrate; This at least one second time weld pad is adjacent to the lower surface of this second substrate, and in this step (e), and this at least one through hole runs through this weld pad and this at least one second time weld pad at least one second.
12. manufacturing approach as claimed in claim 8 is characterized in that, in this step (f), two ends of this at least one conduction column are revealed in the lower surface of this first substrate and the upper surface of this second substrate respectively.
13. manufacturing approach as claimed in claim 8 is characterized in that, comprises that also one adheres to one second tube core in the upper surface of this second substrate, and electrically connects the step of this second tube core to the upper surface of this second substrate.
14. manufacturing approach as claimed in claim 13 is characterized in that, comprises that also one forms the step of one second sealing with the upper surface that coats this second tube core and this second substrate.
15. manufacturing approach as claimed in claim 14 is characterized in that, also comprises the step of this first substrate of cutting, this first sealing, this second substrate and this second sealing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012100763456A CN102569274A (en) | 2012-03-21 | 2012-03-21 | Semiconductor package structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012100763456A CN102569274A (en) | 2012-03-21 | 2012-03-21 | Semiconductor package structure and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
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| CN102569274A true CN102569274A (en) | 2012-07-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN2012100763456A Pending CN102569274A (en) | 2012-03-21 | 2012-03-21 | Semiconductor package structure and manufacturing method thereof |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040056277A1 (en) * | 2002-09-17 | 2004-03-25 | Chippac, Inc. | Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages |
| CN1933147A (en) * | 2005-09-15 | 2007-03-21 | 南茂科技股份有限公司 | Chip packaging body and stack chip packaging structure |
| CN101047167A (en) * | 2006-03-29 | 2007-10-03 | 海力士半导体有限公司 | Semiconductor package stack with through-via connection |
| CN101110409A (en) * | 2006-07-21 | 2008-01-23 | 日月光半导体制造股份有限公司 | System packaging package |
-
2012
- 2012-03-21 CN CN2012100763456A patent/CN102569274A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040056277A1 (en) * | 2002-09-17 | 2004-03-25 | Chippac, Inc. | Semiconductor multi-package module including stacked-die package and having wire bond interconnect between stacked packages |
| CN1933147A (en) * | 2005-09-15 | 2007-03-21 | 南茂科技股份有限公司 | Chip packaging body and stack chip packaging structure |
| CN101047167A (en) * | 2006-03-29 | 2007-10-03 | 海力士半导体有限公司 | Semiconductor package stack with through-via connection |
| CN101110409A (en) * | 2006-07-21 | 2008-01-23 | 日月光半导体制造股份有限公司 | System packaging package |
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Application publication date: 20120711 |