CN102540937A

CN102540937A - Information processor

Info

Publication number: CN102540937A
Application number: CN2010105882147A
Authority: CN
Inventors: 陈飞; 饶兴桥; 何叶; 邓小群
Original assignee: Guizhou Aerospace Control Technology Co Ltd
Current assignee: Guizhou Aerospace Control Technology Co Ltd
Priority date: 2010-12-15
Filing date: 2010-12-15
Publication date: 2012-07-04

Abstract

The invention discloses an information processor, which comprises a DSP (digital signal processor), and a parallel interface controller, a serial interface controller, a logic decoding controller and a storage which are realized by an FPGA (field programmable gate array). The information processor employs the DSP as a computing control center, the parallel interface controller and the serial interface controller are used for exchanging information of peripheral equipment in real time under the control of the DSP, the logic decoding controller is used for realizing storage allocation of a peripheral interface device of the processor, and the storage is used for caching information exchange data of a parallel interface or a serial interface. The special devices such as the parallel interface controller, the serial interface controller, the logic decoding controller, the storage and the like in the information processor are built by the FPGA, the performance, service reliability and use maintenance of the information processor are improved, the size of the information processor is reduced, and cost is reduced.

Description

Message handler

Technical field

The present invention relates to a kind of message handler, specifically a kind of message handler based on FPGA.

Background technology

Along with the development of spationautics, novel aerospacecraft continues to bring out, and the weight and volume of control system is had higher requirement; Require the communication of control information processor stable more good more, The faster the better for speed, and volume is more little good more; Message handler is the key equipment of aerospacecraft information handling system, is that the center is resolved in commander's control, and existing message handler mostly is to add the interface device that matches by nonshared control unit to realize; The defective of its existence is: 1. because the function of message handler is more, need realize with more dedicated devices, make complicated circuit; The use components and parts are many; Board area is big, thereby makes the volume of product become big, the also corresponding increase of the cost of product; 2. Primary Components such as the communication interface controller in the message handler, logic decoding controller, storer need select for use dedicated devices to realize; The homemade chip that but lacks at present corresponding function admirable; Most device is produced by offshore company; Need import to buy, this has received restriction with regard to the production that makes message handler; 3. the peripheral circuit of message handler is realized by hardware circuit fully, is unfavorable for the maintenance and the upgrading of product.

Summary of the invention

For solving the problems of the technologies described above; The object of the present invention is to provide a kind of message handler; Utilize FPGA to make up the dedicated devices such as parallel interface controller, serial interface controller, logic decoding controller and storer in the message handler; Improve performance, functional reliability and the working service property of message handler, reduced the volume of message handler, reduced cost.

The present invention is achieved through following technical scheme.

A kind of message handler comprises the DSP digital signal processor, and parallel interface controller, serial interface controller, logic decoding controller and the FIFO storer realized by FPGA.Message handler is the calculation control center with the digital signal processor; Under DSP control, in real time peripherals is carried out message exchange by parallel interface controller and serial interface controller; The logic decoding controller is realized the storage allocation of processor peripheral interface device, and the FIFO storer is used for the data of buffer memory parallel interface or serial line interface message exchange.

Compared with prior art; The beneficial effect that the present invention reaches makes up parallel interface controller, serial interface controller, logic decoding controller and FIFO storer in the message handler for (1) with FPGA; Substituted dedicated devices, can reduce circuit area, can reduce cost; (2) in circuit synthesis to an integrated circuit of the present invention with multiple function, reduce number of components and volume significantly, reduced power consumption, dwindled the space of circuit; (3) the present invention adopts and holds a plurality of channel interfaces in the single FPGA, and the production cost of message handler is reduced greatly, and the life-span prolongs greatly; (4) owing to the reprogramming of support of the present invention to on-the-spot hardware; The enforcement of core has significantly reduced the design risk; If system requirements change, perhaps to repair one when wrong, can under control of software, upgrade based on the design of FPGA; This dirigibility can also redistrict function between hardware and software after hardware construction is accomplished; (5) the present invention utilizes the IP kernel of FPGA can reduce discarded risk significantly, and behind circuit enforcement FPGA, the design portable generally all need not change its function in up-to-date FPGA, reduced the modification number of times of flow software.

Description of drawings

Fig. 1 is a functional-block diagram of the present invention;

Fig. 2 is a parallel interface controller structural drawing among the present invention;

Fig. 3 is the processing flow chart that parallel interface controller is carried out among the present invention;

Fig. 4 is a serial interface controller structural drawing among the present invention;

Fig. 5 is the transmission data flowchart that serial interface controller is carried out among the present invention;

Fig. 6 is the receiving data stream journey figure that serial interface controller is carried out among the present invention.

Embodiment

Below through the embodiment form; Content of the present invention is done further explain; But the scope that should at this point not be interpreted as theme according to the invention only limits to following embodiment; Do not breaking away under the above-mentioned technological thought situation of the present invention, all various modifications, replacement and changes of making according to ordinary skill knowledge and customary means include within the scope of the invention.

Fig. 1 is a functional-block diagram of the present invention, and message handler of the present invention comprises the DSP digital signal processor, and parallel interface controller, serial interface controller, logic decoding controller and the FIFO storer realized by FPGA.Message handler is the calculation control center with the digital signal processor; Digital signal processor is TMS320VC33; Under DSP control, in real time peripherals is carried out message exchange by parallel interface controller and serial interface controller; The logic decoding controller is realized the storage allocation of processor peripheral interface device, and the FIFO storer is used for the data of buffer memory parallel interface or serial line interface message exchange.

Fig. 2 is a parallel interface controller structural drawing among the present invention; The LPT data line GD0 to GD7 of peripherals, write signal line GWE, reseting signal line GRESET, look-at-me line GINT are after photoelectricity is isolated; Be connected with the IO mouth of FPGA respectively; The data line D0 to D7 of microprocessor TMS320VC33, reading writing signal line R/W, outside imitative ask signal line/STRB, interrupt response signal wire INT0, address wire A0 to A6, A17, A18, A19 are connected with the IO mouth of FPGA respectively, and the clock of the 40MHz that crystal oscillator G1 produces is connected with the CLK pin of microprocessor TMS320VC33 and the IO mouth of FPGA respectively.

Fig. 3 is the processing flow chart that parallel interface controller is carried out among the present invention; The parallel interface controller that is made up by FPGA will be used to survey data storage that combination sends in FIFO; When look-at-me line GINT produces negative edge; The disconnected response signal line INT0 response of microprocessor TMS320VC33 is interrupted, and reads the data that store among the FIFO.

Fig. 4 is a serial interface controller structural drawing among the present invention; The DDRX that peripherals sends, YMRX, DYRX, YXRX signal are after photoelectricity is isolated; Be connected with the IO mouth of FPGA respectively; The data line D0 to D7 of microprocessor TMS320VC33, reading writing signal line R/W, outside imitative ask signal line/STRB, interrupt response signal wire INT0, address wire A0 to A6, A17, A18, A19 are connected with the IO mouth of FPGA respectively; Four IO of FPGA are connected with the input pin mouth of driver DS96F174; The clock of the 40MHz that crystal oscillator G1 produces is connected with the CLK pin of microprocessor TMS320VC33 and the IO mouth of FPGA respectively, and the clock of the 14.7456MHz that crystal oscillator G1 produces is connected with the IO mouth of FPGA.

Fig. 5 is the transmission data flowchart that serial interface controller is carried out among the present invention; When the serial interface controller that is made up by FPGA sent data, processor write data to sending FIFO, and steering logic is checked through sends FIFO for empty; Start process of transmitting immediately; Up to sending FIFO is empty, and whether steering logic gets into inspection FIFO again is empty state, and the data byte number that once can write is by the degree of depth decision of FIFO; When transmission FIFO has expired, processor will be left in the basket to the data that FIFO writes again.

Fig. 6 is the receiving data stream journey figure that serial interface controller is carried out among the present invention, and when the serial interface controller that is made up by FPGA received data, steering logic was monitored the state on the serial data line at any time; As long as monitor effective start bit; Promptly thinking has data to send over, thereby starts receiving course, receives to be about to it after the byte and to write and receive FIFO; Receiving FIFO writes full and till processor do not read, the data that after this send on the serial transmission line will not be received.

Claims

1. message handler; Comprise the DSP digital signal processor; It is characterized in that: also comprise parallel interface controller, serial interface controller, logic decoding controller and the FIFO storer realized by FPGA; Message handler is the calculation control center with the digital signal processor; Under DSP control, in real time peripherals is carried out message exchange by parallel interface controller and serial interface controller, the logic decoding controller is realized the storage allocation of processor peripheral interface device, and the FIFO storer is used for the data of buffer memory parallel interface or serial line interface message exchange.

2. a kind of message handler as claimed in claim 1 is characterized in that: said DSP digital signal processor is TMS320VC33.