CN102468187A - Chip packaging structure and chip packaging method - Google Patents
Chip packaging structure and chip packaging method Download PDFInfo
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- CN102468187A CN102468187A CN2010105479103A CN201010547910A CN102468187A CN 102468187 A CN102468187 A CN 102468187A CN 2010105479103 A CN2010105479103 A CN 2010105479103A CN 201010547910 A CN201010547910 A CN 201010547910A CN 102468187 A CN102468187 A CN 102468187A
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- 238000004806 packaging method and process Methods 0.000 title claims abstract description 61
- 238000000034 method Methods 0.000 title claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 48
- 239000002184 metal Substances 0.000 claims abstract description 38
- 229910052751 metal Inorganic materials 0.000 claims abstract description 38
- 238000003466 welding Methods 0.000 claims abstract description 9
- 238000000059 patterning Methods 0.000 claims abstract description 7
- 239000003292 glue Substances 0.000 claims abstract description 6
- 239000000853 adhesive Substances 0.000 claims description 35
- 230000001070 adhesive effect Effects 0.000 claims description 35
- 239000012528 membrane Substances 0.000 claims description 19
- 230000004888 barrier function Effects 0.000 claims description 17
- 239000000463 material Substances 0.000 claims description 8
- 239000004642 Polyimide Substances 0.000 claims description 5
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 claims description 5
- 229920001721 polyimide Polymers 0.000 claims description 5
- 239000004922 lacquer Substances 0.000 claims description 3
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- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 3
- 238000012856 packing Methods 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 2
- 238000005520 cutting process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 208000004350 Strabismus Diseases 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Abstract
The invention discloses a chip packaging method. The method comprises the following step of: sticking a first glue film on a metal substrate; patterning the metal substrate to form a plurality of externally connected pads and a plurality of leads, wherein the externally connected pads and the leads are respectively arranged on the opposite sides of a central blank area, the externally connected pads beside each side are arrayed into at least two rows at intervals in the direction far away from the central blank area, and each lead comprises a first end extended to the central blank area and a second end connected to the corresponding externally connected pad; sticking a second glue film with an opening on the externally connected pads, wherein the opening exposes the central blank area and the first ends of the leads; removing the first glue film; fixing a chip on the leads and the externally connected pads, wherein a plurality of welding pads of the chip correspond to the central blank area; and electrically connecting the welding pads to the first ends of the leads through a plurality of welding lines and the opening respectively.
Description
[technical field]
The present invention is about a kind of chip-packaging structure and chip packaging method, particularly about a kind of many rows flat non-leaded package and method for packing thereof of chip of tool central welding pad.
[background technology]
Existing four directions/two side's flat non-pin (QFN/DFN) chip-packaging structures 6 of Fig. 1 illustration one, it comprises a chip 61, a lead frame 62 and many bonding wires 64.Chip 61 comprises a plurality of weld pads 63, and said weld pad 63 is arranged on the middle section of active surface of chip 61.Lead frame 62 comprises a chip bearing 65 and a plurality of pin 66, and said pin 66 is arranged at least two opposite sides of chip bearing 65.Chip 61 is arranged on the chip bearing 65 of lead frame 62, and bonding wire 64 correspondingly connects weld pad 63 to the pin 66 on the chip 61 respectively.Because weld pad 63 is positioned at the middle section of the active surface of chip 61, so need long bonding wire 64 to connect the pin 66 of weld pad 63 to the lead frame 62 on the chip 61.Yet long bonding wire 64 causes line to collapse in the time of can influencing signal transmission, encapsulation or increases packaging cost.In addition, because of the restriction of wiring space, pin 66 quantity that lead frame 62 can be provided with can't increase, and the chip of going into (I/O) terminal design for more and more outputs is difficult to deal with its demand in fact.
The ball grid array packages 9 of Fig. 2 A and 2B difference illustration one ball grid array packages 7 and a chip stack formula.Ball grid array packages 7 is fixed on chip 72 on the upper surface of a substrate 71.The ball grid array packages 9 of chip stack formula is with on the stacked respectively upper surface that is fixed on a substrate 75 of chip 72 and 73.Wherein substrate 71 and 75 has a central slot 76, and the weld pad 77 of chip 72 is positioned at the middle section of active surface, and when chip 72 is fixed in substrate 71 or 75 last times, the weld pad 77 of chip 72 is over against answering central slot 76.Bonding wire 74 electrically connects weld pad 77 to the substrate 71 of chip 72 or 75 lower surface through central slot 76.In the ball grid array packages 9 of chip stack formula, after chip 73 is fixed on the chip 72, be electrically connected to the upper surface of substrate 75 again with bonding wire.Generally speaking, compare with lead frame, the substrate 71 of the ball grid array packages 9 of ball grid array packages 7 or chip stack formula and 75 is printed circuit board (PCB) (PCB), and its price is higher, causes ball grid array packages 9 packaging costs of ball grid array packages 7 and chip stack formula high.Especially the substrate 75 of the ball grid array packages 9 of chip stack formula is required to be double-deck copper clad laminate, and its price is higher.In semi-conductor market with keen competition, be difficult to get the mastery in fact.
Because the disappearance of aforementioned existing chip-packaging structure, be necessary to propose a new chip-packaging structure.
[summary of the invention]
According to the problems referred to above, a purpose of the present invention provides a chip-packaging structure and method for packing thereof.This chip-packaging structure can avoid the use of long bonding wire (long-span bonding wire) and can increase the quantity that (I/O) terminal is gone in output, and the low manufacturing cost of tool.
According to above-mentioned purpose, one embodiment of the invention discloses a kind of chip packaging method, comprises the following step: attach one first glued membrane on a first surface of a metal substrate; This metal substrate of patterning is with respect to a second surface of this first surface; To form a plurality of lead frames; Wherein each lead frame comprises respectively a first surface and a second surface, a central clear district of the correspondence that this first surface and this second surface by this metal substrate form and is positioned at two pin crowds of two opposite sides in this central clear district; Wherein each pin crowd comprises a plurality of outer connection pads and a plurality of lead-in wire; Said outer connection pad is arranged at least two rows; This at least two comes away from the direction each interval in this central clear district and arranges, and each lead-in wire comprises one first end and one second end, and wherein this first end extends to this central clear district and this second end connects corresponding outer connection pad; Attach one second glued membrane on said lead frame, wherein this second glued membrane comprises a plurality of perforates, and each perforate exposes this central clear district of each lead frame and first end of said lead-in wire; Remove this first glued membrane; One first chip is fixed on each lead frame; Wherein this first chip comprise an active surface, relatively this active surface a back side and be arranged at a plurality of weld pads on this active surface; This first chip is attached on the first surface of this lead frame with this active surface, and with said weld pad to should the central clear district; And through this perforate, said weld pad is electrically connected to first end of corresponding said lead-in wire on the second surface of this lead frame respectively with many first bonding wires.
Another embodiment of the present invention discloses a kind of chip packaging method; Comprise the following step: a first surface of patterning one metal substrate; To form a plurality of lead frames, wherein each lead frame comprises a recess and is positioned at two pin crowds of two opposite sides of this recess, and wherein each pin crowd comprises a plurality of outer connection pads and a plurality of lead-in wire; Said outer connection pad is arranged at least two rows; This at least two comes away from the direction each interval in this central clear district and arranges, and each lead-in wire comprises one first end and one second end, and wherein connect accordingly should outer connection pad for contiguous this recess of this first end and this second end; Form an insulating barrier outside said between connection pad and the said lead-in wire, wherein first end of this recess of this insulating layer exposing and said lead-in wire; Remove on this metal substrate a second surface of this first surface relatively, make this recess form a central clear district and let reach between the said lead-in wire between the said outer connection pad independently of one another; One first chip is fixed on each lead frame; Wherein this lead frame comprises respectively a first surface and a second surface of the correspondence that this first surface and this second surface by this metal substrate form; This first chip comprise an active surface, relatively this active surface a back side and be arranged at a plurality of weld pads on this active surface; This first chip is attached on the second surface of this lead frame with this active surface, and said weld pad is to should the central clear district; And through this central clear district, said weld pad is electrically connected to first end of corresponding said lead-in wire on the first surface of this lead frame respectively with many first bonding wires.
The present invention discloses a chip-packaging structure in addition, and it comprises a lead frame, one first chip, many first bonding wires and an adhesive body.
Lead frame comprises a central clear district and is positioned at two pin crowds of two opposite sides in this central clear district; Wherein each pin crowd comprises a plurality of outer connection pads and a plurality of lead-in wire; Said outer connection pad is arranged at least two rows; This at least two comes away from the direction each interval in this central clear district and arranges, and each lead-in wire has one first relative end and one second end, wherein this first end extend to that this central clear district and this second end connect accordingly should outer connection pad;
First chip comprise an active surface, relatively this active surface a back side and be arranged at a plurality of weld pads on this active surface.First chip is attached on the first surface of this lead frame with this active surface, and said weld pad is corresponding with this central clear district;
Many first bonding wires are electrically connected first end of corresponding said lead-in wire on the second surface of relative this first surface of said weld pad to this lead frame respectively through this central clear district;
Adhesive body covers this first chip, this lead frame and said first bonding wire, and wherein this adhesive body appears the bottom surface of said outer connection pad.
Long bonding wire compared to the existing chip-packaging structure 6 of Fig. 1; The lead frame of the chip-packaging structure in one embodiment of the invention has the central clear district; And the central welding pad that is electrically connected chip through the central clear district is to the lead-in wire that extends to the central clear district; Therefore can significantly shorten the length of bonding wire, the problem that line collapses or line squints and packaging cost increases when avoiding the issuable transmission signals decay of long bonding wire, encapsulation.In addition, because of lead frame comprises the outer connection pads of arranging more, can increase the quantity that (I/O) terminal is gone in output.Moreover compared to the existing ball grid array packages of Fig. 2, therefore the chip-packaging structure in one embodiment of the invention can reduce the encapsulation manufacturing cost with lower-cost lead frame carries chips.
The technical characterictic and the advantage of preceding text this exposure of sketch out are able to obtain preferable understanding in order to do this exposure detailed description that makes hereinafter.Other technical characterictic and the advantage that constitute the claim target of this exposure will be described in hereinafter.Having common knowledge the knowledgeable in the technical field under this exposure should understand, and the notion that hereinafter discloses can be used as the basis with specific embodiment and revises or design other structure or technology quite easily and realize the purpose identical with this exposure.Have common knowledge the knowledgeable in the technical field under this exposure and also should understand, the construction of this type equivalence also can't break away from the spirit and the scope of this exposure that accompanying claim proposes.
[description of drawings]
Fig. 1 illustration one existing chip-packaging structure;
Fig. 2 A illustration one existing ball grid array packages;
The ball grid array packages of Fig. 2 B illustration one existing chip stack formula;
Fig. 3 shows the cutaway view of the chip-packaging structure of one embodiment of the invention;
Fig. 4 shows the sketch map of the lead frame of one embodiment of the invention;
Fig. 5 shows the cutaway view of the chip-packaging structure of another embodiment of the present invention;
Fig. 6 A to 6G is a schematic cross-section, the process chart of the chip packaging method of its illustration one embodiment of the invention;
Fig. 7 A to 7G is a schematic cross-section, the process chart of the chip packaging method of its illustration another embodiment of the present invention; And
Fig. 8 shows the cutaway view of the chip-packaging structure of yet another embodiment of the invention.
[primary clustering symbol description]
1a, 1b, 1c, 1d chip-packaging structure
2 first glued membranes
3 metal substrates
4 second glued membranes
5 metal substrates
6 chip-packaging structures
7 ball grid array packages
8 glutinous crystal layers
The ball grid array packages of 9 chip stack formulas
10 lead frames
11 first chips
12 lead-in wires
13,13 ' outer connection pad
14 first bonding wires
15,15 ' adhesive body
16 insulating barriers
17 second chips
18 second bonding wires
20 pin crowds
21 central clear districts
31 first surfaces
32 second surfaces
41 perforates
51 first surfaces
52 second surfaces
H1 first thickness
H2 second thickness
61 chips
62 lead frames
63 weld pads
64 bonding wires
65 chip bearings
66 pins
71 substrates
72 chips
73 chips
74 bonding wires
75 substrates
76 central slots
77 weld pads
111 weld pads
112 active surfaces
113 back sides
121 first ends
122 second ends
123 first surfaces
124 second surfaces
131 bottom surfaces
151 first surfaces
152 second surfaces
511 recesses
[embodiment]
The invention relates to the encapsulating structure of the chip of tool central welding pad, wherein this chip-packaging structure can be tool and arranges flat non-pin (multi-row (quad/dual) flat non-leaded more; QFN/DFN) encapsulating structure.
Fig. 3 shows the cutaway view of the chip-packaging structure 1a of one embodiment of the invention.Fig. 4 shows the sketch map of the lead frame 10 of one embodiment of the invention.Shown in Fig. 3 and 4, chip-packaging structure 1a comprises a lead frame 10, one first chip 11, many first bonding wires 14 and an adhesive body 15.
With reference to shown in Figure 4, lead frame 10 comprises a central clear district 21 and is positioned at two pin crowds 20 of two opposite sides in this central clear district 21.Each pin crowd 20 comprises a plurality of outer connection pads (13,13 ') and a plurality of lead-in wire 12.Each pin crowd's 20 a plurality of outer connection pad (13,13 ') is many rows' arranged, and it is arranged at least two rows, and this at least two comes away from the direction each interval in this central clear district 21 and arrange.Lead-in wire 12 has the first relative end 121 and second end 122, and 12 first end 121 of wherein respectively going between extends to central clear district 21, and its second end 122 connects outer connection pad 13 accordingly.In the present embodiment; Each pin crowd's 20 a plurality of outer connection pad (13,13 ') is arranged in three rows; Wherein outer connection pad 13 connects second end 122 of corresponding lead-in wire 12, and outer connection pad 13 ' is not connected with lead-in wire 12, and most outer connection pads 13 ' is arranged in the outboard row farthest apart from central clear district 21.Yet the outer connection pad 13 ' that is not connected with lead-in wire 12 can be positioned at any row's outer connection pad.
With reference to shown in Figure 3, first chip 11 comprise an active surface 112, with these active surface 112 opposing backside surface 113, and be arranged at a plurality of weld pads 111 on this active surface 112.First chip 11 is to be fixed on the lead frame 10 with the mode that its active surface 112 is attached at the first surface 123 of lead frame 10, and is arranged at said weld pad 111 on the active surface 112 over against answering central clear district 21.
Many first bonding wires 14 are connected in first end 121 of said weld pad 111 and said lead-in wire 12 on the active surface 112 respectively.The spy's; Weld pad 111 is arranged at the middle section of the active surface 112 of first chip 11; One end of each first bonding wire 14 connects corresponding weld pad 111; First bonding wire 14 is through central clear district 21, at first end 121 that is connected corresponding lead-in wire 12 with first surface 123 opposing second surface 124 sides.
Shown in Fig. 4 and 5, chip-packaging structure 1b comprises one first chip 11, one second chip 17, a lead frame 10, many first bonding wires 14, many second bonding wires 18 and an adhesive body 15 '.
Each first bonding wire 14 reaches through the corresponding weld pad 111 of central clear district 21 connections at first end 121 that is connected respective lead 12 with first surface 123 opposing second surface 124 sides.
Adhesive body 15 ' then covers first chip 11, lead frame 10, second chip 17, many first bonding wires 14 and many second bonding wires 18, but appears the bottom surface 131 of outer connection pad 13 and 13 ', with the usefulness as outside electric connection.
With reference to shown in Figure 8, chip-packaging structure 1c comprises one first chip 11, a lead frame 10, many first bonding wires 14, an adhesive body 15 and insulating barriers 16.Lead frame 10 comprises a central clear district 21 and is positioned at two pin crowds 20 of two opposite sides in central clear district 21, the outer connection pad 13 that each pin crowd 20 comprises a plurality of lead-in wires 12 and is connected with second end 122 of lead-in wire 12.First chip 11 comprises a plurality of weld pad 111, the first chips 11 that are positioned at the active surface middle section the mode of a plurality of weld pads 111 towards central clear district 21 is attached at the first surface 123 of lead frame 10.First bonding wire 14 connects corresponding weld pad 111 at first end 121 that is connected respective lead 12 with first surface 123 opposing second surface 124 sides and through central clear district 21.Insulating barrier 16 is formed between said outer connection pad 13 and the said lead-in wire 12, fixing by this said outer connection pad 13 and said lead-in wire 12.The thickness of insulating barrier 16 can be identical with lead-in wire 12 thickness, or identical with the thickness of outer connection pad 13, also or any thickness between two thickness.Clearly, the thickness of insulating barrier 16 is big more, and its fixed effect is good more.If insulating barrier 16 is selected the material of agent of low hygroscopicity, then its thickness is big more, prevents that the effect of moisture entering encapsulating structure is good more.Insulating barrier 16 can be selected from: heat-conducting glue material, anti-welding lacquer (solder resist), Polyimide (Polyimide; PI) or benzocyclobutene (Benzocyclobutene; BCB) or other materials similar.
Fig. 6 A to 6G is a schematic cross-section, the process chart of the chip packaging method of its illustration one embodiment of the invention.
Shown in Fig. 6 A, one first glued membrane 2 and a metal substrate 3 at first are provided, wherein metal substrate 3 comprises a first surface 31 and a second surface 32 relative with first surface 31.Then, this first glued membrane 2 is attached on the first surface 31 of this metal substrate 3.
Shown in Fig. 6 B, the second surface 32 of pattern metal substrate 3 is to obtain a plurality of lead frames 10.Each lead frame 10 comprises a central clear district 21 and is positioned at two pin crowds 20 of two opposite sides in this central clear district 21; And each pin crowd 20 comprises outer connection pad 13 and 13 ' and a plurality of lead-in wire 12; Wherein each pin crowd's 20 outer connection pad 13 and 13 ' is many rows' arranged; It is arranged at least two rows, and this at least two comes away from the direction each interval in this central clear district 21 and arrange.In present embodiment, each pin crowd's 20 outer connection pad 13 and 13 ' is arranged in three rows.Each goes between and 12 comprises one first end 121 and one second end 122; Wherein first end 121 extends to central clear district 21; And second end 122 connects corresponding outer connection pad 13; Outer connection pad 13 ' then is not connected with lead-in wire 12, and most outer connection pads 13 ' is arranged in the outboard row farthest apart from central clear district 21.In present embodiment, the step of pattern metal substrate 3 is to carry out with etching mode, wherein removes metal substrate 3 to etch partially process portion, promptly forms said lead-in wire 12.
Shown in Fig. 6 C; Attach one second glued membrane 4 on the second surface 124 (being this surface of the second surface 32 patterned back formation lead frames 10 of metal substrate 3) of said lead frame 10; More specifically, second glued membrane 4 is to be attached on the said outer connection pad 13 and 13 ' bottom surface 131 of said lead frame 10.Second glued membrane 4 comprises a plurality of perforates 41, and wherein each perforate 41 exposes the central clear district 21 of each lead frame 10 and 12 first end 121 of going between.Then, remove first glued membrane 2.Afterwards, go up formation one glutinous crystal layer 8 at the first surface 123 (being the first surface 31 of metal substrate 3) of lead frame 10.
Shown in Fig. 6 D,, first chip 11 is fixed on the corresponding lead frame 10 through glutinous crystal layer 8.First chip 11 comprises an active surface 112, one and this active surface 112 opposing backside surface 113 and be arranged at a plurality of weld pads 111 on the active surface 112.First chip 11 is fixing with the mode of the first surface 123 that its active surface 112 is attached at lead frame 10 and lead frame 10.And, the central clear district 21 of the 111 corresponding lead frames 10 of a plurality of weld pads on first chip 11.
After first chip 11 is fixed; Then through perforate 41; Said weld pad 111 is electrically connected to first end 121 of the said lead-in wire 12 of lead frame 10 respectively with many first bonding wires 14; Wherein an end of each first bonding wire 14 connects corresponding weld pad 111, the first bonding wires 14 connect respective lead 12 through second surface 124 sides of central clear district 21 to lead frame 10 first end 121.
Shown in Fig. 6 E and 6F, first chip 11 then forms an adhesive body 15 after accomplishing routings, covers said first chip 11, said lead frame 10 and said first bonding wire 14.Afterwards, again according to dotted line L display position on Fig. 6 E, single this adhesive body 15 and said lead frame 10 of dividing, to form a plurality of chip-packaging structure 1a, wherein this list step by step for example cutting mode carry out.At last, second glued membrane 4 is removed, therefore, the outer connection pad 13 of chip-packaging structure 1a and 13 ' bottom surface 131 can be by adhesive body 15 coverings and for not appearing, with the usefulness as outside electric connection again.
Shown in Fig. 6 G, before forming earlier figures 6E structure, after first chip 11 attached, second chip 17 can then be fixed on the back side 113 of first chip 11, and wherein second chip 17 is to be fixed on the back side 113 of first chip 11 with the back side.Then; Through perforate 41; Said weld pad 111 is electrically connected to said first end 121 of the said lead-in wire 12 of lead frame 10 respectively with many first bonding wires 14; And form many second bonding wires 18, second chip 17 is electrically connected to the outer connection pad 13 ' of lead frame 10, wherein said second bonding wire 18 is connected to first surface 123 sides of lead frame 10.In another embodiment, can, first bonding wire 14 again second chip 17 be fixed on first chip 11, and form second bonding wire 18 after be electrically connected first end 121 of weld pad 111 and lead-in wire 12.Then, form an adhesive body 15 ' again, to cover said first chip 11, said second chip 17, said lead frame 10, said first bonding wire 14 and said second bonding wire 18.Then, carry out list step by step, last to form a plurality of chip-packaging structure 1b, remove second glued membrane 4, therefore, the outer connection pad 13 of chip-packaging structure 1b and 13 ' bottom surface 131 can be by adhesive body 15 ' covering and for not appearing, with the usefulness as outside electric connection
Fig. 7 A to 7G is a schematic cross-section, the process chart of the chip packaging method of its illustration another embodiment of the present invention.
Shown in Fig. 7 A, a metal substrate 5 at first is provided, wherein metal substrate 5 comprises a first surface 51 and and first surface 51 opposing second surface 52.Then, with first surface 51 patternings of metal substrate 5, to form a plurality of lead frames 10, wherein each lead frame 10 comprises a recess 511 and is positioned at two pin crowds 20 of two opposite sides of this recess 511.Each pin crowd 20 comprises a plurality of outer connection pads 13 and 13 ' and a plurality of lead-in wire 12, and wherein said outer connection pad 13 and 13 ' is many rows' arranged, and it is arranged at least two rows, and this at least two comes away from the direction each interval in this central clear district 21 and arrange.In present embodiment, each pin crowd's 20 outer connection pad 13 and 13 ' is arranged in three rows.Each goes between and 12 can comprise one first end 121 and one second end 122, first end, 121 contiguous recesses 511 wherein, and second end 122 connects corresponding outer connection pad 13.In one embodiment; The patterning of metal substrate 5 comprises part and removes zone to the one first thickness H1 outside metal substrate 5 the above outer connection pad 13 and 13 '; And the part remove these metal substrate 5 the above outer connection pads 13 and 13 ' and said lead-in wire 12 outside zone to the one second thickness H2 to form said lead-in wire 12 and this recess 511, wherein this second thickness H2 is greater than this first thickness H1.
Shown in Fig. 7 B, outside said connection pad 13 and 13 ' and said lead-in wire 12 between form an insulating barrier 16, with fixing said outer connection pad 13 and 13 ' and said lead-in wire 12, wherein first end 121 of these insulating barrier 16 these recesses 511 of exposure and said lead-in wire 12.The thickness of insulating barrier 16 can be identical with lead-in wire 12 thickness, or identical with the thickness of outer connection pad 13, also or any thickness between two thickness.Clearly, the thickness of insulating barrier 16 is big more, and its fixed effect is good more.If insulating barrier 16 is selected the material of agent of low hygroscopicity, then its thickness is big more, prevents that the effect of moisture entering encapsulating structure is good more.Insulating barrier 16 can be selected from: heat-conducting glue material, anti-welding lacquer (solder resist), Polyimide (Polyimide; PI) or benzocyclobutene (Benzocyclobutene; BCB) or other materials similar.
Shown in Fig. 7 B and 7C, the second surface 52 that removes metal substrate 5 becomes the central clear district 21 run through up to recess 511, and between said outer connection pad 13 and 13 ' and between the said lead-in wire 12 independently of one another separately.
Shown in Fig. 7 D, then, go up formation one glutinous crystal layer 8 at the second surface 152 (being the second surface 52 of metal substrate 5) of lead frame 10.Through glutinous crystal layer 8, first chip 11 is fixed on the corresponding lead frame 10.First chip 11 comprise an active surface 112, with this active surface 112 opposing backside surface 113 and a plurality of weld pad 111, wherein said weld pad 111 is arranged at the middle section of the active surface 112 of first chip 11.First chip 11 is attached on the second surface 152 of lead frame 10 with its active surface 112.And after first chip 11 was fixed, its weld pad 111 was over against the central clear district 21 of answering lead frame 10.
Then; Through this central clear district 21; Said weld pad 111 is electrically connected to first end 121 of the said lead-in wire 12 of this lead frame 10 respectively with many first bonding wires 14; After wherein an end of each first bonding wire 14 connects first surface 151 sides (being this surface of the first surface 51 patterned back formation lead frames 10 of metal substrate 5) of corresponding weld pad 111, the first bonding wires 14 through central clear district 21 to lead frame 10, connect first end 121 of respective lead 12 again.
Shown in Fig. 7 E; On the structure that Fig. 7 D shows, form an adhesive body 15, wherein this adhesive body 15 covers said first chip 11, said lead frame 10 and said first bonding wire 14; But the bottom surface 131 that appears said outer connection pad 13 and 13 ' is with the usefulness as outside electric connection.
With reference to Fig. 7 E and 7F, adhesive body 15 divides adhesive body 15 and said lead frame 10 according to dotted line M display position list on Fig. 7 E after forming again, to form a plurality of chip-packaging structure 1c, wherein this list step by step for example cutting mode carry out.
Shown in Fig. 7 G, before forming earlier figures 7E structure, after first chip 11 attached, second chip 17 can then be fixed on the back side 113 of first chip 11, and wherein second chip 17 is to be fixed on the back side 113 of first chip 11 with the back side.Then; Through central clear district 21; Said weld pad 111 is electrically connected to said first end 121 of the said lead-in wire 12 of lead frame 10 respectively with many first bonding wires 14; And form second bonding wire 18, second chip 17 is electrically connected to the outer connection pad 13 ' of lead frame 10, wherein said second bonding wire 18 is second surface 152 sides that are connected to lead frame 10.In another embodiment, can, first bonding wire 14 again second chip 17 be fixed on first chip 11, and form second bonding wire 18 after be electrically connected first end 121 of weld pad 111 and lead-in wire 12.Then, form an adhesive body 15 ' again, to cover said first chip 11, said second chip 17, said lead frame 10, said first bonding wire 14 and said second bonding wire 18.Afterwards, carry out list step by step, to form a plurality of chip-packaging structure 1d.
To sum up, the present invention discloses a chip-packaging structure and method for packing thereof.This chip-packaging structure comprises a chip, a plurality of outer connection pad and a plurality of lead-in wire.Chip comprises a plurality of weld pads, and wherein said weld pad is arranged at the middle section of this chip.Outer connection pad is used for the external electrical connection of chip-packaging structure.Lead-in wire connects corresponding outer connection pad, and the extension of one of which end so can be shortened the weld pad of connection chip and the wire length of lead-in wire near the weld pad of chip.
The technology contents and the technical characterstic of this exposure disclose as above, yet the personage who is familiar with this technology still maybe be based on the teaching of this exposure and announcement and done all replacement and modifications that does not deviate from this exposure spirit.Therefore, the protection range of this exposure should be not limited to embodiment announcement person, and should comprise various replacement and the modifications that do not deviate from this exposure, and is contained by following claim.
Claims (14)
1. chip packaging method comprises the following step:
Attach one first glued membrane on a first surface of a metal substrate;
This metal substrate of patterning is with respect to a second surface of this first surface; To form a plurality of lead frames; Wherein each this lead frame comprises respectively a first surface and a second surface, a central clear district of the correspondence that this first surface and this second surface by this metal substrate form and is positioned at two pin crowds of two opposite sides in this central clear district; Wherein each this pin crowd comprises a plurality of outer connection pads and a plurality of lead-in wire; Said outer connection pad is arranged at least two rows; This at least two comes away from the direction each interval in this central clear district and arranges, and respectively this lead-in wire comprises one first end and one second end, and this first end extends to that this central clear district and this second end connect accordingly should outer connection pad;
Attach one second glued membrane on said lead frame, wherein this second glued membrane comprises a plurality of perforates, and each this perforate exposes this central clear district of each this lead frame and said first end of said lead-in wire;
Remove this first glued membrane;
One first chip is fixed in respectively on this lead frame; Wherein this first chip comprise an active surface, relatively this active surface a back side and be arranged at a plurality of weld pads on this active surface; This first chip is attached on this first surface of this lead frame with this active surface, and said weld pad is to should the central clear district; And
Through this perforate, said weld pad is electrically connected to this first end of corresponding said lead-in wire on this second surface of this lead frame respectively with many first bonding wires.
2. chip packaging method according to claim 1 is characterized in that, the step of this pattern metal substrate comprises part and removes this metal substrate to form said lead-in wire.
3. chip packaging method according to claim 1 is characterized in that, it more comprises the step that forms an adhesive body, and to cover this first chip, said lead frame and said first bonding wire, wherein this adhesive body appears the bottom surface of said outer connection pad.
4. chip packaging method according to claim 1 is characterized in that, it more comprises the following step:
One second chip is fixed on this back side of this first chip;
Form many second bonding wires, with corresponding said outer connection pad on this first surface that this second chip is electrically connected to this lead frame; And
Form an adhesive body, to cover this first chip, this second chip, said lead frame, said first bonding wire and said second bonding wire, wherein this adhesive body appears the bottom surface of said outer connection pad.
5. according to claim 3 or 4 described chip packaging methods, it is characterized in that, after the step that forms this adhesive body, more comprise the following step:
Single this adhesive body and said lead frame of dividing is to form a plurality of chip-packaging structures; And
Remove this second glued membrane.
6. chip packaging method comprises the following step:
One first surface of patterning one metal substrate; To form a plurality of lead frames, wherein each lead frame comprises a recess and is positioned at two pin crowds of two opposite sides of this recess, and wherein each this pin crowd comprises a plurality of outer connection pads and a plurality of lead-in wire; Said outer connection pad is arranged at least two rows; This at least two comes away from the direction each interval of this recess and arranges, and respectively this lead-in wire comprises one first end and one second end, and contiguous this recess of this first end and this second end connect accordingly should outer connection pad;
Form an insulating barrier outside said between connection pad and the said lead-in wire, wherein said first end of this recess of this insulating layer exposing and said lead-in wire;
Remove on this metal substrate a second surface of this first surface relatively so that this recess form reach between the said lead-in wire between a central clear district and the said outer connection pad independently of one another;
One first chip is fixed in respectively on this lead frame; Wherein this lead frame comprises respectively a first surface and a second surface of the correspondence that this first surface and this second surface by this metal substrate form; This first chip comprise an active surface, relatively this active surface a back side and be arranged at a plurality of weld pads on this active surface; This first chip is attached on this second surface of this lead frame with this active surface, and said weld pad is to should the central clear district; And
Through this central clear district, said weld pad is electrically connected to this first end of corresponding said lead-in wire on this first surface of this lead frame respectively with many first bonding wires.
7. chip packaging method according to claim 6; It is characterized in that; The step of this pattern metal substrate comprises part and removes zone to one first thickness outside the above outer connection pad of this metal substrate; And part removes zone to one second thickness outside the above outer connection pad of this metal substrate and the said lead-in wire to form said lead-in wire and this recess, and wherein this second thickness is greater than this first thickness.
8. chip packaging method according to claim 6 is characterized in that, it more comprises the step that forms an adhesive body, and to cover this first chip, said lead frame and said first bonding wire, wherein this adhesive body appears the bottom surface of said outer connection pad.
9. chip packaging method according to claim 6 is characterized in that, it more comprises the following step:
One second chip is fixed on this back side of this first chip;
Form many second bonding wires, with corresponding said outer connection pad on this second surface that this second chip is electrically connected to this lead frame; And
Form an adhesive body, to cover this first chip, this second chip, said lead frame, said first bonding wire and said second bonding wire, wherein this adhesive body appears the bottom surface of said outer connection pad.
10. according to Claim 8 or 9 described chip packaging methods, it is characterized in that, after the step that forms this adhesive body, more comprise the following step:
Single this adhesive body and said lead frame of dividing is to form a plurality of chip-packaging structures.
11. a chip-packaging structure comprises:
One lead frame; Comprise a central clear district and be positioned at two pin crowds of two opposite sides in this central clear district; Wherein each this pin crowd comprises a plurality of outer connection pads and a plurality of lead-in wire, and said outer connection pad is arranged at least two rows, and this at least two comes away from the direction each interval in this central clear district and arrange; Respectively this lead-in wire has one first relative end and one second end, and wherein this first end extends to this central clear district and corresponding this outer connection pad of this second end connection;
One first chip, comprise an active surface, relatively this active surface a back side and be arranged at a plurality of weld pads on this active surface, this first chip is attached on the first surface of this lead frame with this active surface, and said weld pad is to should the central clear district;
Many first bonding wires are electrically connected this first end of corresponding said lead-in wire on the second surface of relative this first surface of said weld pad to this lead frame respectively through this central clear district; And
One adhesive body covers this first chip, this lead frame and said first bonding wire, and wherein this adhesive body appears the bottom surface of said outer connection pad.
12. chip-packaging structure according to claim 11 is characterized in that, it more comprises an insulating barrier, be formed between said outer connection pad and the said lead-in wire, and said first end of the said lead-in wire of this insulating layer exposing.
13. chip-packaging structure according to claim 12 is characterized in that, the material of this insulating barrier can be selected from: heat-conducting glue material, anti-welding lacquer, Polyimide and benzocyclobutene.
14. chip-packaging structure according to claim 11; It is characterized in that; It more comprises one second chip and many second bonding wires; Wherein this second chip is fixed on this back side of this first chip, and said second bonding wire be electrically connected respectively on this first surface of this second chip to this lead frame corresponding said outside connection pad, this adhesive body more covers this second chip and said second bonding wire.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105479103A CN102468187A (en) | 2010-11-05 | 2010-11-05 | Chip packaging structure and chip packaging method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105479103A CN102468187A (en) | 2010-11-05 | 2010-11-05 | Chip packaging structure and chip packaging method |
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| CN102468187A true CN102468187A (en) | 2012-05-23 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104843632A (en) * | 2014-02-14 | 2015-08-19 | 南茂科技股份有限公司 | Micro-electromechanical chip package and manufacturing method thereof |
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| US6075284A (en) * | 1998-06-30 | 2000-06-13 | Hyundai Electronics Industries Co., Ltd. | Stack package |
| US20020158347A1 (en) * | 2000-03-13 | 2002-10-31 | Hiroshi Yagi | Resin -encapsulated packing lead member for the same and method of fabricating the lead member |
| US20100072590A1 (en) * | 2008-09-22 | 2010-03-25 | Yong Liu | Stacking Quad Pre-Molded Component Packages, Systems Using the Same, and Methods of Making the Same |
| US20100200972A1 (en) * | 2006-10-05 | 2010-08-12 | Hung-Tsun Lin | BGA package with leads on chip |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6075284A (en) * | 1998-06-30 | 2000-06-13 | Hyundai Electronics Industries Co., Ltd. | Stack package |
| US20020158347A1 (en) * | 2000-03-13 | 2002-10-31 | Hiroshi Yagi | Resin -encapsulated packing lead member for the same and method of fabricating the lead member |
| US20100200972A1 (en) * | 2006-10-05 | 2010-08-12 | Hung-Tsun Lin | BGA package with leads on chip |
| US20100072590A1 (en) * | 2008-09-22 | 2010-03-25 | Yong Liu | Stacking Quad Pre-Molded Component Packages, Systems Using the Same, and Methods of Making the Same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104843632A (en) * | 2014-02-14 | 2015-08-19 | 南茂科技股份有限公司 | Micro-electromechanical chip package and manufacturing method thereof |
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Application publication date: 20120523 |