CN102446870A - Packaging component with electrostatic discharge and anti-interference of electromagnetic wave functions - Google Patents
Packaging component with electrostatic discharge and anti-interference of electromagnetic wave functions Download PDFInfo
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- CN102446870A CN102446870A CN2010105086833A CN201010508683A CN102446870A CN 102446870 A CN102446870 A CN 102446870A CN 2010105086833 A CN2010105086833 A CN 2010105086833A CN 201010508683 A CN201010508683 A CN 201010508683A CN 102446870 A CN102446870 A CN 102446870A
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- ground structure
- electromagnetic wave
- bearing part
- static discharge
- packaging part
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/30107—Inductance
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Abstract
The invention relates to a packaging component with electrostatic discharge and anti-interference of electromagnetic wave functions. The packaging component comprises a carrier, a semiconductor component and a covering component, wherein the carrier is provided with a first grounding structure with an electric property insulation function and a second grounding structure with an electric property insulation, the semiconductor component is connected and arranged on one surface of the carrier and is electrically connected with the first grounding structure, and the covering component is arranged on the carrier and the semiconductor component in a covering manner and is electrically connected with the second grounding structure. In the packaging component, the semiconductor component and the covering component are respectively and electrically connected with the first grounding structure and the second grounding structure so that static electricity and charges of electromagnetic waves are respectively removed, and the semiconductor component is prevented from being damaged by static electricity; and therefore, the rate of finished products can be increased, and the short-circuiting can be avoided.
Description
Technical field
The present invention relates to a kind of packaging part, relate in particular to a kind of packaging part that has static discharge and avoid Electromagnetic Interference.
Background technology
Along with the fast development of science and technology, various new products are constantly weeded out the old and bring forth the new, and conveniently use and carry easy demand in order to satisfy the consumer, and various now electronic product is invariably towards light, thin, short, little development; Wherein, Semiconductor package part (Semiconductor Package) is electrically connected at semiconductor chip (chip) on the bearing part of a base plate for packaging for a kind of; Packing colloid with for example epoxy resin coats this semiconductor chip and bearing part again; Protect this semiconductor chip and bearing part to pass through this packing colloid, and avoid the infringement of extraneous aqueous vapor or pollutant, on this packing colloid, be covered with the covering member of a metal-back again; Or only on this semiconductor chip and bearing part, be covered with the covering member of a metal-back; Impaired to avoid ectocine (like Electrostatic Discharge etc.) through this semiconductor chip of this covering member protection; And stop electromagnetic interference (the Electro-Magnetic Interference of inside and outside through this covering member; EMI) and Electro Magnetic Compatibility (Electro-Magnetic Compatibility, EMC).
And existing packing component or system in package (System in Package; SiP or System Integrated Package; SIP) grounding system; Be located at outside covering member and the ground structure of himself electric connection through this, with system's the earth electric connection, remove outside electromagnetism and electrostatic charge again thereby lead.
The 5th, 166, No. 772 United States Patent (USP) proposes a kind of semiconductor package part with net metal cover cap.Shown in Figure 1A and 1B; The 5th; 166; The semiconductor package part that No. 772 United States Patent (USP) disclosed connects on substrate 10 puts a net metal cover cap (Meshed Metallic Shield) 12, and chip 11 is taken in wherein, with packing colloid 13 this net metal cover cap 12 and chip 11 is coated fully again.This semiconductor package part provides through this net metal cover cap 12, to cover the Electromagnetic Interference that chip 11 produced or by the Electromagnetic Interference that external device (ED) was produced, wherein, this net metal cover cap 12 electrically connects the ground path 14 of these substrates 10.
Seeing also Fig. 2, is the cross-sectional schematic of the 6th, 187, No. 613 another existing semiconductor package parts that United States Patent (USP) disclosed.As shown in the figure, on substrate 10, connect with flip-chip (flip-chip) mode and put a chip 11 through projection 15, on this substrate 10 and chip 11, stick lid again and establish a metal forming 16, and between this metal forming 16 and substrate 10 filling packing colloid 13.This semiconductor package part outer is located at the metal forming 16 on the packing colloid 13 through this, to cover Electromagnetic Interference that chip 11 produced or by Electromagnetic Interference that external device (ED) was produced.
But; The earthing mode of these above-mentioned packaging parts all is electrically connected to the ground path of chip and master/passive device through net metal cover cap or metal forming, when semiconductor package part connects when placing on the circuit board; If this net metal cover cap or metal forming have static; Then this static can be along the path of this ground path towards circuit board and chip and master/passive device conduction, and static when conducting to chip and master/passive device static takes place and discharges, and just causes chip and master/passive device to damage easily.
Moreover; It is long that this net metal cover cap or metal forming are connected to the path of system's the earth; When especially having substrate 10 now less than six layer line roads; Reduce because of circuit too much causes the ground connection effect of this ground path, make that electric charge is difficult for discharging, and might cause this chip or other master/passive device internal damage.
Therefore, how a kind of packaging part being provided, can avoiding inner chip or master/passive device by electrostatic breakdown, and have good electrostatic defending and have discharge and the function that anti electromagnetic wave disturbs concurrently, is an important topic in fact.
Summary of the invention
Disadvantages in view of above-mentioned prior art; The present invention discloses a kind of packaging part with electrostatic defending and anti electromagnetic wave interference; Comprise: bearing part have first and second relative surface, and this bearing part has first ground structure and second ground structure that is electrically insulated; At least one semiconductor element connects on the first surface that places this bearing part, and is electrically connected to this bearing part and first ground structure thereof; And covering member, be covered on this bearing part first surface covering this semiconductor element, and this covering member electrically connects this second ground structure.
In above-mentioned packaging part, this second ground structure be located at this bearing part around or four corners, the second surface of this bearing part has planted a plurality of conducting elements, and respectively this conducting element electrically connects this first ground structure and second ground structure.
In one embodiment, this second ground structure directly runs through this first and second surperficial conductive hole, and this covering member connects and puts at the terminal of this conductive hole at first surface.
The above-mentioned packaging part with static discharge and anti electromagnetic wave interference, this bearing part also has internal wiring.
According to above-mentioned packaging part, this semiconductor element electrically connects the internal wiring and first ground structure of this bearing part with wire-bonded (wire bonding) mode or flip-chip (flip-chip) mode; This semiconductor element be selected from active member like chip, passive device or its two; This passive device is electric capacity, resistance or inductance.
According to the packaging part of the above, this second surface is provided with empty pad, and this second ground structure electrically connects should the void pad, and should the void pad be positioned at around this bearing part or the position beyond four corners.
In above-mentioned packaging part, also comprise encapsulating material again, coat this semiconductor element, and this covering member is formed on this encapsulating material.
Described packaging part with static discharge and anti electromagnetic wave interference also comprises encapsulating material, coats this covering member.
By on can know; This bearing part that the present invention has the packaging part of electrostatic defending and anti electromagnetic wave interference has first and second ground structure that is electrically insulated; Make this semiconductor element and covering member electrically connect this first ground structure and second ground structure respectively; When packaging part connects when placing circuit board,, make electrostatic charge be directly conducted to circuit board through second ground structure by this covering member if covering member has static; And can be via this first ground structure, make this semiconductor element can not receive the influence that static discharges and be protected; And can stop that outside electromagnetism involves interference such as radio frequency through this covering member, and discharge electric charge, disturbed to avoid this semiconductor element through this second ground structure.
Description of drawings
Figure 1A and 1B are the schematic perspective view of the 5th, 166, No. 772 semiconductor package parts that United States Patent (USP) disclosed;
Fig. 2 is a United States Patent (USP) the 6th, 187, the cross-sectional schematic of the semiconductor package part that is disclosed for No. 613;
Fig. 3 A, 3B and 3C have the cross-sectional schematic of the different embodiment of the packaging part that static discharge and anti electromagnetic wave disturb for the present invention;
Fig. 4 A and 4B have the upward view of the bearing part of the packaging part that static discharge and anti electromagnetic wave disturb for the present invention; And
Fig. 4 B ' is the cutaway view with packaging part of the present invention of Fig. 4 B bearing part.
The primary clustering symbol description
10 substrates, 11 chips
12 net metal cover caps, 13 packing colloids
14 ground paths, 15,342 projections
16 metal formings, 20 packaging parts
31 bearing parts, 310 internal wirings
311 first ground structures, 312 second ground structures
31a first surface 31b second surface
32 semiconductor elements, 33 covering members
321 chips, 322 passive devices
341 leads, 35 conducting elements
331 contact site 312a conductive holes
313,313 ' weld pad, 36 circuit boards
37a, 37b encapsulating material
Embodiment
Below through particular specific embodiment execution mode of the present invention is described, those skilled in the art can understand other advantage of the present invention and effect easily by the content that this specification disclosed.
See also Fig. 3 A, 3B and 3C, be the cross-sectional schematic with different embodiment of the packaging part that static discharge and anti electromagnetic wave disturb of the present invention.
The present invention provides a kind of packaging part with static discharge and anti electromagnetic wave interference, comprising: bearing part 31, at least one semiconductor element 32 and covering member 33.
Described bearing part 31; Comprise ball grid array base plate (BGA substrate) or planar gate array (LGA) substrate; This bearing part 31 has opposite first 31a and second surface 31b, and this bearing part 31 has internal wiring 310 (comprising signal and partial power) and first ground structure 311 that is electrically insulated and second ground structure 312.
Described semiconductor element 32 be selected from active member like chip 321, passive device 322 or its two, this passive device 322 is electric capacity, resistance or inductance; And this semiconductor element 32 connects on the first surface 31a that places this bearing part 31, and electrically connects the internal wiring 310 and first ground structure 311 of this bearing part 31 with the projection (bump) 342 (shown in Fig. 3 B) of the lead 341 (shown in Fig. 3 A) of wire-bonded mode or flip-chip mode.
Described covering member 33, the first surface 31a that is covered on this bearing part 31 are gone up covering on this semiconductor element 32, and this covering member 33 electrically connects these second ground structures 312.
Above-mentioned packaging part can carry out mold pressing (molding) earlier form to coat the encapsulating material 37a of this semiconductor element 32, again on this encapsulating material 37a the jet-plating metallization layer to form this covering member 33 (shown in Fig. 3 A and 3B); Perhaps, after lid is established this covering member 33 of moulding in advance, carry out mold pressing for the second time again to form the encapsulating material 37b (shown in Fig. 3 C) that coats this covering member 33.
In a preferred embodiment, this second ground structure 312 directly runs through the conductive hole 312a of this first surface 31a and second surface 31b, and shortening electrical conducting path, and this covering member 33 connects and puts at the terminal of this conductive hole 312a at first surface 31a.
According to above-mentioned packaging part; The second surface 31b of this bearing part has planted a plurality of conducting elements 35; This conducting element 35 can be soldered ball, capillary or weld pad, and respectively this conducting element 35 electrically connects this internal wiring 310, first ground structure 311 and second ground structure 312; Then packaging part is connect and place on the circuit board 36; The signal or the electric power of semiconductor element 32 can be conducted through internal wiring 310 and conducting element 35; And be electrically connected to the ground structure (not shown) of circuit board 36 through first ground structure 311, and covering member 33 can be through second ground structure 312 and conducting element 35 to electrically connect this circuit board 36.
According to the above, this conducting element 35 directly is located at the below of this second ground structure 312 again, and this second ground structure 312 vertically is arranged in the below of this covering member 33, thereby shortens conducting path, thus the speed that can accelerated charge discharges.
From the above; This semiconductor element 32 electrically connects first ground structure 311 of this bearing part 31; And this covering member 33 electrically connects these second ground structures 312, when packaging part connects when placing circuit board 36, if when covering member 33 or packaging part have static; Then this electrostatic charge can directly be discharged towards circuit board 36 through second ground structure 312 by this covering member 33 and get rid of; And can not make this semiconductor element 32 can not receive the influence of electrostatic charge, thereby this semiconductor element 32 can be protected and be unlikely damage via first ground structure 311.
Moreover, can stop outside electromagnetic interference (EMI) and Electromagnetic Compatibility through this covering member 33, and discharge electric charge through this second ground structure 312, disturbed to avoid this semiconductor element 32; The inner electrostatic charge of this semiconductor element 32, electromagnetic wave, and interference such as radio frequency then can discharge by this first ground structure 311 separately, thereby to protect this semiconductor element 32.
See also Fig. 4 A and 4B, be the upward view of this bearing part 31; Shown in Fig. 4 A; In this preferred embodiment; The weld pad 313 that this second ground structure 312 is connected on second surface 31b be located at this bearing part 31 around or four corners, thereby provide this covering member 33 extend to it around or the contact site 331 (shown in Fig. 3 A to 3C) in corner electrically connect this second ground structure 312 and weld pad 313.In the practical implementation, this second ground structure 312 can be located at this bearing part 31 around or the conductive hole 312a in four corners.In like manner, the conducting element 35 that connects this second ground structure 312 is also corresponding be located at this bearing part 31 second surface 31b around or on the weld pad 313 in four corners.
In another embodiment shown in Fig. 4 B and the 4B '; The weld pad 313 ' that this second ground structure 312 is connected on second surface 31b also can be located at this bearing part 31 around or the position beyond four corners; For example comparatively interior position of arranging; And this weld pad 313 ' can be empty pad (dummy pad), as long as second ground structure 312 that it electrically connected and first ground structure 311 are independence and are electrically insulated.
In sum; This bearing part that the present invention has the packaging part of static discharge and anti electromagnetic wave interference has electrically isolated first ground structure and second ground structure, make first ground structure of this this bearing part of semiconductor element electric connection, and this covering member electrically connects this second ground structure; When packaging part connects when placing circuit board; If covering member has static, this electrostatic charge can be directly conducted to circuit board through second ground structure by this covering member, and can be via this first ground structure; Make this semiconductor element can not receive the influence that static discharges and be protected, be unlikely damage; And can stop that outside electromagnetism involves interference such as radio frequency through this covering member, and discharge electric charge, disturbed to avoid this semiconductor element through this second ground structure.
The foregoing description is in order to exemplary illustration principle of the present invention and effect thereof, but not is used to limit the present invention.Any those skilled in the art all can make amendment to the foregoing description under spirit of the present invention and category.So rights protection scope of the present invention, should be listed like claim.
Claims (11)
1. the packaging part with static discharge and anti electromagnetic wave interference is characterized in that, comprising:
Bearing part has first and second relative surface, and this bearing part has first ground structure and second ground structure that is electrically insulated;
At least one semiconductor element connects on the first surface that places this bearing part, and is electrically connected to this bearing part and first ground structure thereof; And
Covering member be covered on this bearing part first surface covering this semiconductor element, and this covering member electrically connects this second ground structure.
2. according to claim 1 have a packaging part that static discharge and anti electromagnetic wave disturb, it is characterized in that, this second ground structure be located at this bearing part around or four corners.
3. the packaging part with static discharge and anti electromagnetic wave interference according to claim 2 it is characterized in that the second surface of this bearing part has planted a plurality of conducting elements, and respectively this conducting element electrically connects this first ground structure and second ground structure.
4. according to claim 2 have a packaging part that static discharge and anti electromagnetic wave disturb, and it is characterized in that, this second ground structure directly runs through this first and second surperficial conductive hole, and this covering member connects and puts at the terminal of this conductive hole at first surface.
5. the packaging part with static discharge and anti electromagnetic wave interference according to claim 1 is characterized in that this bearing part also has internal wiring.
6. the packaging part with static discharge and anti electromagnetic wave interference according to claim 5 is characterized in that this semiconductor element electrically connects the internal wiring and first ground structure of this bearing part with wire-bonded mode or flip-chip mode.
7. according to claim 1 have a packaging part that static discharge and anti electromagnetic wave disturb, it is characterized in that, this semiconductor element be selected from active member, passive device or its two.
8. the packaging part with static discharge and anti electromagnetic wave interference according to claim 1 is characterized in that this second surface is provided with empty pad, and this second ground structure electrically connects should the void pad.
9. the packaging part with static discharge and anti electromagnetic wave interference according to claim 8 is characterized in that, this void pad is positioned at around this bearing part or position in addition, four corners.
10. the packaging part with static discharge and anti electromagnetic wave interference according to claim 1 is characterized in that, also comprises encapsulating material, coat this semiconductor element, and this covering member is formed on this encapsulating material.
11. the packaging part with static discharge and anti electromagnetic wave interference according to claim 1 is characterized in that, also comprises encapsulating material, coats this covering member.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105086833A CN102446870A (en) | 2010-10-13 | 2010-10-13 | Packaging component with electrostatic discharge and anti-interference of electromagnetic wave functions |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105086833A CN102446870A (en) | 2010-10-13 | 2010-10-13 | Packaging component with electrostatic discharge and anti-interference of electromagnetic wave functions |
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| CN102446870A true CN102446870A (en) | 2012-05-09 |
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| CN2010105086833A Pending CN102446870A (en) | 2010-10-13 | 2010-10-13 | Packaging component with electrostatic discharge and anti-interference of electromagnetic wave functions |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103513124A (en) * | 2012-06-29 | 2014-01-15 | 环旭电子股份有限公司 | Electromagnetic shielding testing device |
| CN105321933A (en) * | 2014-08-01 | 2016-02-10 | 乾坤科技股份有限公司 | Semiconductor package with conformal EM shielding structure and manufacturing method of same |
| CN107172549A (en) * | 2017-06-06 | 2017-09-15 | 广东欧珀移动通信有限公司 | Electroacoustic component and electronic equipment |
| CN107481997A (en) * | 2017-09-05 | 2017-12-15 | 中国电子科技集团公司第二十九研究所 | A kind of double stacked level Hermetic Package structure and method |
| US10469174B2 (en) * | 2016-09-05 | 2019-11-05 | Wingcomm Co. Ltd. | Anti-interference semiconductor device for optical transceiver |
| CN110993508A (en) * | 2019-11-22 | 2020-04-10 | 青岛歌尔智能传感器有限公司 | Packaging structure, manufacturing method thereof and electronic equipment |
| CN112616240A (en) * | 2020-12-08 | 2021-04-06 | 海光信息技术股份有限公司 | Chip substrate and mainboard |
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