CN102431960A - Silicon through hole etching method - Google Patents
Silicon through hole etching method Download PDFInfo
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- CN102431960A CN102431960A CN2011104025061A CN201110402506A CN102431960A CN 102431960 A CN102431960 A CN 102431960A CN 2011104025061 A CN2011104025061 A CN 2011104025061A CN 201110402506 A CN201110402506 A CN 201110402506A CN 102431960 A CN102431960 A CN 102431960A
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- etching
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- silicon chip
- passivation
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Abstract
The invention provides a silicon through hole etching method and belongs to the field of micro nano machining of micro electro mechanical systems, and the method can be used for solving the problems that the side wall of a substrate generates ripples, a photoresist can be easily damaged and metal pollution is caused when an existing Bosch process and a metal mask are utilized to carry out deep silicon etching. The method provided by the invention comprises a pattern preparation step, an etching step, a culture slice adding step, a penetrating step and a photoresist removing step. In the etching step, processing is stopped after circulative and alternative etching is finished, so that the photoresist is cooled and the protective action of the photoresist is prevented from being reduced; then circulative etching is carried out again; passivating gas is added into etching gas; and the etching gas is added into the passivating gas for improving the smoothness of the side wall. In the culture slice adding step, a silicon wafer is adhered to the upper surface of a culture slice,thus preventing silicon wafer fracture and equipment damage after etching penetration. The method provided by the invention has the advantages that the process is simple and the etching speed is quick; the photoresist utilized as the mask can be easily removed after being etched, and metal pollution is avoided; the verticality of the side wall of a through hole is easily controlled; the smoothness of the side wall is improved; and the ripples on the side wall are eliminated.
Description
Technical field
The invention belongs to MEMS (MEMS) micro-nano manufacture field, relate in particular to a kind of silicon etching method for forming through hole.
Background technology
In recent years; Computer, communication, automotive electronics, aerospace industry and other consumer products are had higher requirement to microelectronics Packaging; Promptly littler, thinner, lighter, highly reliable, multi-functional, low-power consumption and low cost; Need realize the electrical interconnection between the different chips producing many perpendicular interconnection through holes on the silicon wafer, so the silicon via etch process becomes important technology of MEMS (MEMS) micro-nano manufacture field.
The silicon via etch process is a kind of dark silicon etching process that adopts dry plasma etch, and at present, dark silicon etching generally adopts Bosch technology and metal mask.Bosch technology also is known as " suitching type etching technics ", with the plasma gas chemical method etch silicon of fluorine; In etching process; Add etching gas etching a period of time, and then with carbon fluorine plasma gas to the passivation of etching base side wall, passivation a period of time; Carry out etching afterwards again, carry out alternately processing of etching and passivation so circularly; In actual etching process, need up to a hundred times etching and passivation alternately to repeat processing, improve the selectivity of etching.This alternately method for processing inevitably will produce ripple in base side wall, and alternately the energy of processing accumulation will make photoresist damage, and the silicon chip below can not fine protection influences the surface quality of etching sample; Adopt metal mask, can produce undercut (undercut) phenomenon man-hour adding, also can bring metallic pollution in addition.
Summary of the invention
The present invention provides a kind of silicon etching method for forming through hole, solve to adopt existing Bosch technology and metal mask to carry out that there is base side wall generation ripple in dark silicon etching, photoresist damages easily and the problem of metallic pollution.
A kind of silicon etching method for forming through hole of the present invention comprises:
(1) preparation figure step:
On silicon chip, evenly apply photoresist, photoresist thickness 10～15 μ m; Adopt photoetching process on photoresist, to prepare required figure;
(2) etch step:
Utilize Bosch technology, in inductive couple plasma etching machine, the silicon chip of preparation figure carried out 40～80 etchings and passivation alternately after the processing, suspend processing, treat the photoresist cooling after, carry out 40～80 etchings again and replace with passivation and process; So cycle alternation is etched the part residual thickness less than 150um until silicon chip; Inductive couple plasma etching machine process chamber pressure: 30～40mtorr, temperature: 10～30 ℃;
During each etching and passivation are alternately processed, etch stages: radio-frequency power 25～30w, inductive couple plasma power 700～800W, etch period 10～12 seconds, adding gas is C
4F
8And SF
6, C
4F
8Flow: 5 ± 1sccm, SF
6Flow: 100 ± 5sccm;
The passivation stage: radio-frequency power 10～15W, inductive couple plasma power 700～800W, passivation time 10～12 seconds, adding gas is C
4F
8And SF
6, C
4F
8Flow: 100 ± 5sccm, SF
6Flow: 5 ± 1sccm;
(3) add training sheet step:
Select for use thickness greater than the full wafer silicon chip of 300 μ m as the training sheet, on the training sheet, apply vacuum heat-conduction oil, the silicon chip that will pass through step (2) processing sticks to above the training sheet;
(4) penetration step:
To the silicon chip of handling through step (3), adopt the etching technics of step (2) to wear silicon chip until quarter;
(5) remove the photoresist step:
The silicon chip of wearing quarter is immersed acetone soln,, remove photoresist remaining on the silicon chip, obtain having the silicon chip of through-hole structure through ultrasonic Treatment.
In etch step, for fear of long-time etching and passivation alternately the energy of processing accumulation photoresist will be damaged, adopts 40～80 cycle alternation etchings after, suspend processing, photoresist is cooled off, avoid reducing its protective effect, etching then circulates; At etching gas SF
6In added passivation gas C simultaneously
4F
8In the passivation deposition step, at passivation gas C
4F
8In added etching gas SF simultaneously
6,, eliminate the sidewall ripple in order to improve the sidewall smoothness; Etching and passivation time all are 10～15 seconds, are guaranteeing to improve etching speed as much as possible under the vertical future of sidewall.
In adding training sheet step, when the fast etching of silicon chip is worn, select greater than the thick silicon chip of 300 μ m on the training sheet, to apply vacuum heat-conduction oil as the training sheet, above sticking to silicon chip, with prevent to carve wear after, silicon chip breaks, and infringement equipment.And then follow etching, wear silicon chip until quarter.
The present invention adopts standard photolithography process to prepare figure, and technology is simple, and etching speed is very fast, can reach 3.3 μ m/min; Adopt photoresist to do mask, be very easy to after the etching remove the metallic pollution that to avoid metal mask to bring; Utilize Bosch technology, in inductive couple plasma etching machine, silicon chip is carried out etching, control the through-hole side wall perpendicularity easily; Improve the sidewall smoothness, eliminated the sidewall ripple.
Description of drawings
Fig. 1 is a process chart of the present invention;
Fig. 2 is the SEM figure of etching rear wall;
Fig. 3 is that the thick silicon chip of 4 in2s, 00 μ m is worn the sketch map of various through holes by quarter;
Fig. 4 is that the thick silicon chip of 2 in2s, 50 μ m is by the sketch map of wearing quarter.
Fig. 5 is that the thick silicon chip of 4 in2s, 50 μ m is by the sketch map of wearing quarter.
The specific embodiment
Embodiment 1, comprising:
(1) preparation figure step:
On thickness 200 μ m, 4 inches silicon chips, evenly apply photoresist, photoresist thickness 10 μ m; Adopt photoetching process and karl suss MA6 litho machine on photoresist, to prepare required figure;
(2) etch step:
Utilize Bosch technology; In the Oxford of Oxford instrument company Plasmalab ICP inductive couple plasma etching machine, the silicon chip of preparation figure is carried out 50 etchings and passivation alternately after the processing, suspend and process; After treating photoresist cooling, carry out 50 etchings again and alternately process with passivation; So cycle alternation is etched the part residual thickness less than 150um until silicon chip; Its etching verticality of side wall and smoothness are as shown in Figure 2; Inductive couple plasma etching machine process chamber pressure: 40mtorr, temperature: 20 ℃;
During each etching and passivation are alternately processed, etch stages: radio-frequency power 25w, inductive couple plasma power 700W, etch period 10 seconds, adding gas is C
4F
8And SF
6, C
4F
8Flow: 5sccm, SF
6Flow: 100sccm;
The passivation stage: radio-frequency power 10W, inductive couple plasma power 700W, passivation time 10 seconds, adding gas is C
4F
8And SF
6, C
4F
8Flow: 100sccm, SF
6Flow: 5sccm;
(3) add training sheet step:
4 inches silicon chips of full wafer of selecting thickness 500 μ m for use apply vacuum heat-conduction oil as the training sheet on the training sheet, the silicon chip that will pass through step (2) processing sticks to above the training sheet;
(4) penetration step:
To the silicon chip of handling through step (3), adopt the etching technics of step (2) to wear silicon chip until quarter;
(5) remove the photoresist step:
The silicon chip of wearing quarter is immersed acetone soln,, remove photoresist remaining on the silicon chip, obtain having the silicon chip of through-hole structure through ultrasonic Treatment, as shown in Figure 3.
The required etch period of present embodiment is 60min.
Embodiment 2, comprising:
(1) preparation photoresist figure step:
On thickness 250 μ m, 2 inches silicon chips, evenly apply photoresist, photoresist thickness 15 μ m; Adopt photoetching process on photoresist, to prepare required figure;
(2) etch step:
Utilize Bosch technology; In the Oxford of Oxford instrument Plasmalab ICP inductive couple plasma etching machine, the silicon chip of preparation figure is carried out 40 etchings and passivation alternately after the processing, suspend and process; After treating photoresist cooling, carry out 40 etchings again and alternately process with passivation; So cycle alternation is etched the part residual thickness less than 150um until silicon chip; Inductive couple plasma etching machine process chamber pressure: 40mtorr, temperature: 10 ℃;
During each etching and passivation are alternately processed, etch stages: radio-frequency power 30w, inductive couple plasma power 800W, etch period 12 seconds, adding gas is C
4F
8And SF
6, C
4F
8Flow: 4sccm, SF
6Flow: 95sccm;
The passivation stage: radio-frequency power 15W, inductive couple plasma power 800W, passivation time 12 seconds, adding gas is C
4F
8And SF
6, C
4F
8Flow: 95sccm, SF
6Flow: 4sccm;
(3) add training sheet step:
Select for use thickness be the full wafer silicon chip of 350 μ m as the training sheet, on the training sheet, apply vacuum heat-conduction oil, the silicon chip that will pass through step (2) processing sticks to above the training sheet;
(4) penetration step:
To the silicon chip of handling through step (3), adopt the etching technics of step (2) to wear silicon chip until quarter;
(5) remove the photoresist step:
The silicon chip of wearing quarter is immersed acetone soln,, remove photoresist remaining on the silicon chip, obtain having the silicon chip of through-hole structure through ultrasonic Treatment, as shown in Figure 4.
The required etch period of present embodiment is 75min.
Embodiment 3, comprising:
(1) preparation photoresist figure step:
On thickness 250 μ m, 4 inches silicon chips, evenly apply photoresist, photoresist thickness 15 μ m; Adopt photoetching process and karl suss MA6 litho machine on photoresist, to prepare required figure;
(2) etch step:
Utilize Bosch technology; In the Oxford of Oxford instrument Plasmalab ICP inductive couple plasma etching machine, the silicon chip of preparation figure is carried out 80 etchings and passivation alternately after the processing, suspend and process; After treating photoresist cooling, carry out 80 etchings again and alternately process with passivation; So cycle alternation is etched the part residual thickness less than 150um until silicon chip; Its etching verticality of side wall and smoothness are as shown in Figure 2; Inductive couple plasma etching machine process chamber pressure: 30mtorr, temperature: 30 ℃;
During each etching and passivation are alternately processed, etch stages: radio-frequency power 25w, inductive couple plasma power 750W, etch period 10 seconds, adding gas is C
4F
8And SF
6, C
4F
8Flow: 6sccm, SF
6Flow: 105sccm;
The passivation stage: radio-frequency power 10W, inductive couple plasma power 750W, passivation time 10 seconds, adding gas is C
4F
8And SF
6, C
4F
8Flow: 105sccm, SF
6Flow: 6sccm;
(3) add training sheet step:
4 inches silicon chips of full wafer of selecting thickness 500 μ m for use apply vacuum heat-conduction oil as the training sheet on the training sheet, the silicon chip that will pass through step (2) processing sticks to above the training sheet;
(4) penetration step:
To the silicon chip of handling through step (3), adopt the etching technics of step (2) to wear silicon chip until quarter;
(5) remove the photoresist step:
The silicon chip of wearing quarter is immersed acetone soln,, remove photoresist remaining on the silicon chip, obtain having the silicon chip of through-hole structure through ultrasonic Treatment, as shown in Figure 5.
The required etch period of present embodiment is 80min.
Claims (1)
1. silicon etching method for forming through hole comprises:
(1) preparation figure step:
On silicon chip, evenly apply photoresist, photoresist thickness 10～15 μ m; Adopt photoetching process on photoresist, to prepare required figure;
(2) etch step:
Utilize Bosch technology, in inductive couple plasma etching machine, the silicon chip of preparation figure carried out 40～80 etchings and passivation alternately after the processing, suspend processing, treat the photoresist cooling after, carry out 40～80 etchings again and replace with passivation and process; So cycle alternation is etched the part residual thickness less than 150um until silicon chip; Inductive couple plasma etching machine process chamber pressure: 30～40mtorr, temperature: 10～30 ℃;
During each etching and passivation are alternately processed, etch stages: radio-frequency power 25～30w, inductive couple plasma power 700～800W, etch period 10～12 seconds, adding gas is C
4F
8And SF
6, C
4F
8Flow: 5 ± 1sccm, SF
6Flow: 100 ± 5sccm;
The passivation stage: radio-frequency power 10～15W, inductive couple plasma power 700～800W, passivation time 10～12 seconds, adding gas is C
4F
8And SF
6, C
4F
8Flow: 100 ± 5sccm, SF
6Flow: 5 ± 1sccm;
(3) add training sheet step:
Select for use thickness greater than the full wafer silicon chip of 300 μ m as the training sheet, on the training sheet, apply vacuum heat-conduction oil, the silicon chip that will pass through step (2) processing sticks to above the training sheet;
(4) penetration step:
To the silicon chip of handling through step (3), adopt the etching technics of step (2) to wear silicon chip until quarter;
(5) remove the photoresist step:
The silicon chip of wearing quarter is immersed acetone soln,, remove photoresist remaining on the silicon chip, obtain having the silicon chip of through-hole structure through ultrasonic Treatment.
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| CN2011104025061A CN102431960A (en) | 2011-12-07 | 2011-12-07 | Silicon through hole etching method |
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| CN2011104025061A CN102431960A (en) | 2011-12-07 | 2011-12-07 | Silicon through hole etching method |
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102983096A (en) * | 2012-11-29 | 2013-03-20 | 上海华力微电子有限公司 | Method for optimizing shallow slot isolating etching process |
| CN103072939A (en) * | 2013-01-10 | 2013-05-01 | 林红 | Temperature-controlled deep silicon etching method |
| CN103400800A (en) * | 2013-08-14 | 2013-11-20 | 中微半导体设备(上海)有限公司 | Bosch etching method |
| CN103950887A (en) * | 2014-04-09 | 2014-07-30 | 华中科技大学 | Deep silicon etching method |
| WO2014161462A1 (en) * | 2013-04-02 | 2014-10-09 | 无锡华润上华半导体有限公司 | Method for reinforcing micro-electro-mechanical systems device in manufacturing process |
| CN104617033A (en) * | 2013-11-05 | 2015-05-13 | 中芯国际集成电路制造(上海)有限公司 | Wafer level packaging method |
| CN113800466A (en) * | 2021-09-23 | 2021-12-17 | 华东光电集成器件研究所 | Deep silicon etching method for MEMS suspension structure |
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| CN101330019A (en) * | 2007-06-18 | 2008-12-24 | 中芯国际集成电路制造(上海)有限公司 | Method for etching through-hole and method for removing passivation layer within the through-hole |
| CN201408748Y (en) * | 2008-11-04 | 2010-02-17 | 西安工业大学 | Silicon deep slot structure with depth-to-width ratio |
| CN102226986A (en) * | 2011-06-27 | 2011-10-26 | 天津环鑫科技发展有限公司 | Manufacturing method for ultrathin semiconductor device |
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| CN1358325A (en) * | 1999-06-28 | 2002-07-10 | 拉姆研究公司 | Method and apparatus for side wall passivation for organic etch |
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102983096B (en) * | 2012-11-29 | 2015-01-28 | 上海华力微电子有限公司 | Method for optimizing shallow slot isolating etching process |
| CN102983096A (en) * | 2012-11-29 | 2013-03-20 | 上海华力微电子有限公司 | Method for optimizing shallow slot isolating etching process |
| CN103072939A (en) * | 2013-01-10 | 2013-05-01 | 林红 | Temperature-controlled deep silicon etching method |
| CN103072939B (en) * | 2013-01-10 | 2016-08-03 | 北京金盛微纳科技有限公司 | A kind of Temperature-controlldeep deep silicon etching method |
| WO2014161462A1 (en) * | 2013-04-02 | 2014-10-09 | 无锡华润上华半导体有限公司 | Method for reinforcing micro-electro-mechanical systems device in manufacturing process |
| CN103400800B (en) * | 2013-08-14 | 2015-09-30 | 中微半导体设备(上海)有限公司 | Bosch lithographic method |
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| CN104617033A (en) * | 2013-11-05 | 2015-05-13 | 中芯国际集成电路制造(上海)有限公司 | Wafer level packaging method |
| CN104617033B (en) * | 2013-11-05 | 2018-09-14 | 中芯国际集成电路制造(上海)有限公司 | Wafer-level packaging method |
| CN103950887B (en) * | 2014-04-09 | 2016-01-20 | 华中科技大学 | A kind of dark silicon etching method |
| CN103950887A (en) * | 2014-04-09 | 2014-07-30 | 华中科技大学 | Deep silicon etching method |
| CN113800466A (en) * | 2021-09-23 | 2021-12-17 | 华东光电集成器件研究所 | Deep silicon etching method for MEMS suspension structure |
| CN113800466B (en) * | 2021-09-23 | 2023-08-29 | 华东光电集成器件研究所 | Deep silicon etching method of MEMS suspension structure |
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Application publication date: 20120502 |