CN102411535A - Navigating-SoC (System On Chip) simulating, verifying and debugging platform - Google Patents
Navigating-SoC (System On Chip) simulating, verifying and debugging platform Download PDFInfo
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Abstract
The invention discloses a navigating-SoC (System On Chip) simulating, verifying and debugging platform, which comprises a navigating-SoC verifying plate and a PC (Personal Computer) host-computer environment, wherein an RISC (Reduced Instruction Set Computer) processor and an FPGA (Field-Programmable Gate Array) are integrated onto the navigating-SoC verifying plate, and the PC host-computer environment is used for assisting the debugging and the analysis of a designer. A navigating IP (Internet Protocol) is realized on the FPGA, and the support for a hanging/operating mode is added. According to a hardware-hanging/operating state, a navigation-interrupting program is divided into a hardware-hanging period and a hardware-operating period, the introduction of intermediate-frequency data into the SoC verifying plate is finished through a UDP (User Datagram Protocol)/USB (Universal Serial Bus) protocol by a PC host computer at the hanging period, and debugging information is sequentially transmitted to the PC host computer by the SoC verifying plate. In the invention, the operating time of a code on the RISC processor is also accurately analyzed by utilizing a timer resource on the SoC verifying plate, and the real-time property of software and hardware can be analyzed. A PC host-computer end comprises a GUI (Graphical User Interface), a UDP/USB communication thread and a background database, so that a perfect verifying environment is provided for the designer.
Description
Technical field
The present invention relates to SoC (System On Chi, SOC(system on a chip)) verifying and debugging field, particularly a kind of apparatus platform of can be used for navigating SoC chip emulation, checking and debugging.
Background technology
Global navigational satellite positioning system (GNSS) has obtained using widely in every field between decades in the past.GNSS has comprised GPS of USA, Muscovite GLONASS, the Compass (Big Dipper) of China and the Galileo system of European Union at present.At civil area, most mobile device all possesses navigation feature, for people's trip provides great convenience.Many vehicles have been equipped with GPS navigation equipment, have simplified the management of communications greatly.In military field, navigational system is the most important thing of modernized war especially, the chip and the core of these equipment is navigated exactly.In navigation chip design field, the advanced level of home and overseas has a certain distance, and chip such as Sirf, u-blox and corresponding solution have all reached high level at power consumption, degree of ripeness, reliability and cost.
Progressively perfect along with the Big Dipper two generations satellite navigation system; The design of navigation chip and research and development become the focus of academia and industry again; In order not to be limited by external chip supplier; The SoC solution that contains navigation IP (Intellectual Property, ip module) and RSIC processor (Reduced Instruction Set Computer, Reduced Instruction Set Computer) of independent intellectual property right is badly in need of developing to have in China.
The hardware-accelerated unit of so-called navigation is called for short navigation IP, refers to solid nuclear that provides with the net table or the soft nuclear that provides with HDL (Hardware Description Language, hardware description language) code.Navigation algorithm relates to a large amount of mathematical operations and matrix operation, adopts hardware to realize that difficulty is excessive fully, is difficult to make amendment, and extendability can be restricted, and simultaneously, navigation algorithm also is in the process of continuous evolution, and the dirigibility of hardware can't meet the demands.On the other hand, though pure software realizes it being the focus that academia pays close attention to always, processing power, power consumption requirement balance with present RISC can't meet the demands.Therefore, the scheme that hardware accelerator (IP promptly navigates) becomes main flow is closed in the risc processor caryogamy, and such navigation chip solution is called for short navigation SoC (System-on-a-Chip, i.e. SOC(system on a chip)).What make up such SoC system is checking and debugging part a big difficult point, and this also is a longest part consuming time, directly has influence on Time To Market.
The operation and the checking of navigation SoC chip have following characteristics:
1. navigation IP needs the cooperation of processor, and operating software can improve the dirigibility of design on processor.Therefore, we want simulating, verifying to as if the system of a software-hardware synergism.In the different debugging schemes, algorithm software both may operate on the PC main frame, also may operate on the risc processor of Target Board, and the behavior of the latter and actual chips more conforms to.
2. navigation SoC chip must be paid close attention to real-time, and navigation algorithm is handled navigation intermediate frequency data stream, and these algorithms all are that the real-time requirement is arranged.How provide real-time information accurately and complete Debugging message to become the basic problem of navigation SoC checking to the designer.
3. the checking of navigation IP and SoC system has very high requirement to simulation velocity.The sampling rate scope 4MHz ~ 17MHz of navigation intermediate frequency data; Navigation IP operates in 30MHz ~ 100MHz; The data of processor processes 1s need up to ten million clock period, and the data that navigation algorithm is often wanted a minute just can calculate the result, if simulate some special scenes; The data that need dozens of minutes adopt the HDL emulator to go emulation length that will be very consuming time fully.
4. the memory space of navigation intermediate frequency data is very big, is example with the sampling rate 2bit precision of 5.714MHz, and 1 minute data just need the data of 85.71MB; If desired the flow processs such as catching, follow the tracks of and resolve under the different scenes is carried out emulation; Often needed 5 minutes even the longer time; Data volume will reach MB more than 400, and therefore data storage, importing and playback mechanism also are the problems that debug platform must solve efficiently.The importing of data also will guarantee temporal accuracy, and the sampled point that staggers all can influence the accuracy of total system operation.
5. Fig. 1 is the SoC program run flow process of typically navigating, and timer triggers processor at set intervals and once interrupts, and the typical case is spaced apart 520us.And the navigation IP with the sampling interval time import intermediate frequency data, typical sampling rate is 40/7MHz or 16.368MHz.After interrupt function returns,, can call principal function termly according to the result of zone bit.(navigation IP) carries out mutual main the and hardware-accelerated unit of interrupt service routine.Program execution flow as shown in the figure is the main flow mode of operation of navigation chip.
Fig. 1 is the typical flowchart of navigation SoC running software, and the emulation field in navigation algorithm and hardware accelerator system mainly contains three kinds of schemes at present:
Scheme one is described total system with hardware description language (HDL), comprises that processor core and navigation IP all adopt HDL to describe, and what processor core moved is the binary executable code that compiling is accomplished;
Scheme two; Adopt isa simulator to carry out the emulation of navigation algorithm software; And the hardware-accelerated unit that navigates is through the emulation of HDL emulator; The two carries out alternately through DPI mechanism (Direct Programming Interface, SystemVerilog and the mutual mechanism of C/C++ language) or operating system inter-process communication mechanisms;
Scheme three, the scheme of employing software-hardware synergism, the FPGA on Target Board (field programmable gate array) realizes navigation IP, operation navigation operations program on the X86 main frame, PC main frame and FPGA communicate through pci interface;
Scheme one can obtain the most accurate simulation result, and debugs through the HDL emulator, and shortcoming is very slow, and the result that the HDL emulator obtains is not directly perceived yet, only can debug in the pin signal rank of low level very.The logic of processor core (can be comprehensive) is very complicated, and the complicacy of navigation IP itself, often several days time of needs could emulation the data in several seconds.Simultaneously, the expense of processor core mandate is very high, and cost is too high, and general company and R&D institution of school can't afford.
Scheme two has been accelerated the simulation velocity of processor part, but bulk velocity still is subject to the simulation performance of the hardware-accelerated unit R TL of navigation.Because software module is through the isa simulator operation, the behavior of Cache (buffer memory) and the sequential of bus have no idea accurately to simulate, and can't truly reflect the behavior of SoC chip, seriously disturb the assessment of designer to real-time.
Scheme three need not moved the HDL emulator, and bottleneck is transferred on the communication efficiency of PC main frame and FPGA.But will be appreciated that; It is often different with the operation result that risc processor obtains that software code operates on the X86 main frame resulting result; X 86 processor and risc processor on framework (such as instruction set, Cache, memory management unit MMU and floating-point coprocessor) are widely different; Cause on the operational efficiency different with the operation result precision, also can't assess the software real-time.The pci interface agreement is very complicated, often needs a special main frame to move total system.
On the playback scheme of intermediate frequency data, traditional method has two kinds:
Method one: carry out real-time simulation truly, the navigation IP that is implemented on the FPGA directly is connected with the intermediate frequency data output port of sampling A;
Method two: support intermediate frequency data to be imported to the playback of data among the FPGA according to certain sequential through PCI-E interface or USB interface;
Method one is not supported the playback of data.But reproducing characteristic is the basic demand in SoC checking field always.In the middle of extraneous scene often is in and constantly changes, the time of occurrence of problem often at random, this just brings very big difficulty to debugging.Therefore support that the playback of data is prerequisites of navigation debug function, it makes the designer to carry out omnibearing analysis to same batch data and same problem repeatedly, thereby finds the defective in the system.Get rid of the interference that extraneous factors such as weather, place are brought, separately these two steps of the debugging of the collection of data and SoC system checking.
Though the agreement more complicated that method two is used; And all be the software section that moves navigation algorithm with the x86 processor on the PC main frame; Although can analyze to the real-time of hardware; But can't carry out the analysis of accurate quantification, and the real-time of software is only the difficult point in the navigation algorithm design to the real-time of software.
Retrieval through to the prior art document is found; Application number is " 200610012061.5 "; Name is called " system for processing navigational satellite signal ", and this patent provides a kind of Navsat disposal system, can gather navigation satellite signal in real time, continuously, for a long time; Be sent to computing machine, and through high-speed interface such as USB with the sampled data playback.This platform is only paid close attention to playback function, and unpromising debugging provides solution.
Also find in the retrieval; Granted publication number is CN 100526910C; Name is called " plateform system that is used for researching and developing satellite navigation receiver "; Plateform system in this patent is divided into hardware components and software section with navigation neceiver, and software section runs on the computing machine, and hardware components is connected in said computing machine through computer interface through computer interface.Because running software is on the x86 computing machine, the analysis of software real-time just can't be carried out, because x86 processor core flush bonding processor exists very big difference.Therefore, there is big-difference very in the ruuning situation of the operation of this platform and navigation SoC real chip, and a lot of exclusive problems of embedded system all can't come out.
Present existing scheme is all just paid close attention to the hardware-software partition of navigation algorithm itself; Only hardware accelerator is verified with FPGA; Not paying close attention to and the risc processor and the mutual sequential between the hardware cell of navigating, is that SoC and chip design provide debugging and verification mechanism.These existing schemes can't be assessed the real-time of navigation algorithm at true risc processor, the real-time of especially interrupting.As everyone knows, Interrupt Process is to influence very The key factor of system stability and operational efficiency.The given software code of these existing schemes the leak of debugging can occur being difficult to when the later stage downloads to risc processor, have a strong impact on design schedule.
Summary of the invention
To the technical matters that exists in the prior art, the present invention provide a kind of high efficiency, can be to navigation SoC chip emulation, checking and debug platform based on the UDP/USB agreement quantitative test of software and hardware real-time, that the signal system is irrelevant.
For realizing above-mentioned purpose, the technical scheme that the present invention adopts is following:The present invention is navigation chip design exploitation service, concern be the checking and the debugging of SOC(system on a chip).At first customize a SoC system verification plate, have risc processor and FPGA on the plate, be equipped with Ethernet interface or USB interface.Different with existing most of PC/FPGA collaborative simulation mechanism is that Navigator operates on the risc processor in this platform.Be that hardware adds Suspend Mode, will navigate accelerator hardware and Abort Timer hang-up of certain stage in interrupt routine.Hang up stage PC main frame at hardware intermediate frequency data is imported to the FIFO (First Input First Output) among the FPGA through udp protocol or usb protocol, and accomplish the collection of Debugging message, the IP that navigates afterwards resumes operation.In order to support the accurate assessment of real-time, all these network service codes, Debugging message are collected the zone that code all is placed on Non-Cacheable (can not buffer memory), reduce the interference to original system.Main frame is set up perfect debugging gui program and background data base, lets the designer can utilize these Debugging message that navigation SoC chip is analyzed, and further improves existed algorithms framework and hardware designs.
The present invention provides a kind of navigation SoC chip emulation, checking and debug platform; This platform specifically comprises PC main frame and SoC system verification plate; Communication between them is carried out through UDP (User Datagram Protocol) or USB (USB) agreement; Said PC main frame passes through UDP or usb protocol and handshake mechanism and accomplishes the importing of intermediate frequency data to SoC system verification plate, and SoC system verification plate is gathered Debugging message and also returned to the PC main frame.
Comprise risc processor and fpga chip on the said SoC system verification plate, wherein FPGA and risc processor communicate with the interface of bus mode or short time delay.Navigation IP provides with the RTL form, comprehensively is implemented on the FPGA.Realize having the navigation IP of Suspend Mode on the FPGA hardware, move navigation algorithm on the risc processor, in the auxiliary positioning calculation function of accomplishing down of navigation IP.
Said risc processor is realized memory-mapped and Cache management through memory management unit MMU; The peripheral hardware resource that risc processor can be controlled will have ethernet controller or USB controller at least, and is connected with the PC main frame; All C/C++ programs of navigating all operate on the risc processor, are divided into master routine and interrupt service routine on the main body; Interrupt service routine is responsible for carrying out alternately with navigation IP, and typical interrupt is spaced apart 520 ~ 800us; The information that master routine utilizes interrupt service routine to return calculates coordinate, these two program flows completion satnav of working in coordination.
For real-time is assessed; Risc processor should have access to three timer resources; One of them timer is accomplished the time-delay of set time, and another timer is accomplished down trigger, and the 3rd timer accomplished the measurement of working time of a plurality of program segment.These timer resources both can be distributed on the FPGA, also can be in risc chip inside.
Said risc processor can conduct interviews and reads and writes the hardware-accelerated unit that navigates, and must configure pin among the FPGA according to the situation of development board and connect.The most natural form is that FPGA and risc processor connect through on-chip bus (with ARM is example, is exactly the AMBA bus) or PCI-E bus.
Must add support (mode that enables with the clk_enable clock realizes) in the RTL code of the hardware-accelerated unit of said navigation (being called for short navigation IP) to Suspend Mode; Ppu can change operation/suspended state of navigation IP through the mode of register read-write; Make its time-out, continue then to carry out.
The interrupt function that moves on the said risc processor is divided into the hardware operation phase and hardware is hung up the stage.Hardware is hung up stage PC main frame and is imported navigation data through Ethernet/USB interface in batches into to FPGA; FPGA is last to have corresponding FIFO to store these data; The collection of Debugging message and to return also be to accomplish in this in stage.
Said PC end storage navigation intermediate frequency data, the PC main frame is shaken hands and is communicated by letter through UDP or usb protocol with the SoC witness plate.The PC main frame should have network interface or USB interface.
Said PC main frame is divided into four threads, is respectively GUI graphical interfaces thread, debug system master control thread, database thread and UDP/USB communication thread.The master control thread is responsible for the distribution of resource between other three threads, the stamping-out of communication.The UDP/USB communication thread is responsible for communicating with the SoC witness plate.The Debugging message that database thread is come to communications carries out classification and storage, and supports that the user retrieves these information, and database thread also is responsible for calling in of intermediate frequency data data source.Graphical interfaces lets the designer check the operation of Debugging message and real-time information, drawing waveforms and receiver control with mode intuitively.
Among the present invention, hang up the stage, be sent to the FIFO (First Input First Output) among the FPGA with the controlled pattern intermediate frequency data that will navigate at the hardware of interrupt service routine.FIFO is encapsulated as the peripheral hardware of processor place bus, is mapped to one section zone in the internal memory, and processor writes data with the mode of memory read-write to FIFO in batches, is that Hardware I P module provides data in one period of future.
The residue of RISC/FPGA witness plate inspection intermediate frequency data FIFO is initiated request of data to the PC end in each interrupt function, the PC end is followed the handshake mechanism intermediate frequency data that will navigate and returned to SoC system verification plate.The Debugging message collection procedure of risc processor end with receiver state, Debugging message, resolve the logical PC end that is sent to of relevant informations such as result and real-time analysis and further analyze.These Debugging message will be filled whole Ethernet data bag with the form of parcel; And then the PC host side is accomplished the fractionation and the parsing of these packets; Insert the database on backstage subsequently, gui interface will be accomplished the retrieval to database according to operation of designer; Take out these information and represent these information, carry out the debugging that time precision is an interrupt levels with the form of waveform or form.
The extracode of these UDP/USB communications is through the setting of link script and MMU (memory management unit); Be positioned over the zone of Non-Cacheable; The Cache of risc processor (cache memory) will receive minimum interference, so just can estimate accurately the real-time of original navigation algorithm software.And; Through the mode that sequential logic enables, the navigation IP that makes FPGA go up operation supports Suspend Mode, under the control of risc processor; To be in Suspend Mode at network service stage (promptly moving the stage of extracode) navigation IP and timer; This moment, the software and hardware logic of navigation algorithm itself did not all have operation, and the designer can fully add the Debugging message code, and Debugging message can be collected fully; And can not be subject to the performance of risc processor, can not have influence on the measurement of real-time yet.
These extracodes are that the form at Non-Cacheable lets the risc processor operation, so performance of processors is high more, the bus communication bandwidth is high more, the simulation performance of whole flat is just high more.This scheme is a protocol-independent, the USB2.0 of compatible main flow and UDP communication protocol.
Technique effect of the present invention is following:
Navigation SoC chip emulation of the present invention, checking and debug platform; Cooperatively interact to descend to carry out emulation with the speed of 1:7 than to navigation neceiver at X86 main frame and ARM RealView Emulation Board platform (risc processor has been selected the most general arm processor of industry); And the collection of completion Debugging message, the designer can be the operation that base unit is controlled whole receiver with the interruption.Whole flat can be worked on high efficient and reliable ground, considerably beyond HDL emulator RTL simulation speed, and supports the embedded system real-time is analyzed.The designer can be through the operation of gui interface control navigation SoC witness plate software and hardware part; Retrieval Debugging message and real-time information from database; Debugging message and real-time data are analyzed the bottleneck of total system better; Improve navigation SoC chip architecture, adjustment algorithm and optimize codes are for the later stage chip realizes carrying out sufficient preparation.
Description of drawings
Fig. 1 is the typical flowchart of navigation SoC running software;
Fig. 2 is the system construction drawing of navigation SoC chip;
Fig. 3 is the Typical Disposition figure that adds the navigation SoC witness plate of intermediate frequency data playback mechanism in the embodiment of the invention;
Fig. 4 is the present invention adds the SoC system verification plate of hardware Suspend Mode on the basis of Fig. 3 a structured flowchart;
Fig. 5 adds intermediate frequency data playback and Debugging message interruptions in transmissions function processing flow chart in the embodiment of the invention;
Fig. 6 is this pairing MMU configuration and memory-mapped block diagram of embodiment of the invention medium chain pin;
Fig. 7 is the truck synoptic diagram of PC mainframe program overall framework and navigation SoC system verification plate in the embodiment of the invention.
Embodiment
Below technical scheme of the present invention is further described, following explanation is merely the usefulness of understanding technical scheme of the present invention, is not used in the scope of the present invention that limits, protection scope of the present invention is as the criterion with claims.
Below in conjunction with accompanying drawing navigation SoC chip emulation of the present invention, checking and debug platform are described in further detail, below describing is example with arm processor and ahb bus all, if other risc processor or other bus form are please suitably revised.
Step 1, customizing navigation SoC chip checking plate.Like Fig. 2 is the system construction drawing of navigation SoC chip; It directly obtains intermediate frequency data from radio-frequency front-end; These data get into hardware-accelerated IP and handle, and risc processor or DSP accomplish the location of coordinate under the assistance of hardware accelerator, do not need the support of radio-frequency front-end in the present embodiment.Have arm processor and FPGA on the SoC witness plate that is customized, communicate through UDP or usb protocol with main frame.
Step 2, the support of adding data readback.Shown in way 3, be the Typical Disposition figure that adds the navigation SoC witness plate of intermediate frequency data playback mechanism in the embodiment of the invention.Exampleization fifo module among the FPGA is not because we can carry out read-write operation to FIFO simultaneously, so the FIFO of synchronized model or asynchronous type all meets the demands.FIFO corresponding to two addresses of bus is respectively:
L address 0 data write register, write with the 32bit data width of present main flow;
1 FIFO effective location register in l address returns the quantity of spare word among the current FIFO, and the navigation interrupt routine needs this register to obtain the information of FIFO, to confirm should ask how many data to the PC end next time;
Fifo module among FPGAs realizes all that with the navigation IP kernel ARM can control it through bus.
Step 3 is the support of navigation IP adding hardware Suspend Mode.Navigation IP provides with the form of RTL, different according to processor and FPGA type of attachment, and this navigation IP skin will possess different EBIs.With ARM RealView Emulation Board is example, and arm processor externally is the AHB interface, and therefore this navigation correlator IP must carry the AHB interface.If otherwise connect, navigation IP must carry different interface logics.For example, if the or1200 microprocessor, the wishbone interface of then can arranging in pairs or groups.
Fig. 4 is the present invention adds the SoC system verification plate of hardware Suspend Mode on the basis of Fig. 3 a structured flowchart.Adding for RTL (register transfer level) code explains as follows the support method of Suspend Mode; In general the code of Hardware I P nuclear all is based on all synchro style description; With Verilog is example, and each module generally comprises the synchronous sequential logic statement (seeing left hurdle) of the description of following style:
Amended code adds `define SUSPEND_SUPPORT at top layer precompile file shown in right hurdle, and in all comprise the module port of synchronous sequential logic, adds pd_n port (see figure 3).So long as complete describe synchronously can be comprehensive hardware module can be transformed into the module of supporting Suspend Mode in such a manner.
Corresponding to Suspend Mode and operational mode, need to add two registers, processor is to the mode of operation that just can switch Hardware I P that writes of these two registers.The pd_n port of these two register controlled IP kernels, suspend_reg writes to register, and pd_n is changed to low level, makes navigation IP get into Suspend Mode; Wakeup_reg writes to register, and pd_n is changed to high level, and navigation IP continues operation.
Step 4 is for verifying this configuration timer resource.Need three timer resource A, B, C on the plate, these three resources are all wanted and can be narrated as follows by the arm processor utilization:
L timer A: support the time-delay of set time, accomplish the time-delay of delicate level and Millisecond such as the function distribution of delayus () and delayms ();
L timer B: supporting the measurement of real-time, below is program runtime interval measurement code example, in order to measuring (timer is counted) working time of one section code downwards:
T_start=timerB_cnt (); // initial
codeA?to_measure…
CodeA_duration=timerB_cnt () – t_start; // finish
CodeA_duration is exactly the time that the codeA code is moved, and its precision is relevant with the minimum resolution of timer B, and representative value is 1us.
L timer C: the look-at-me timer in the running software flow process like Fig. 1, needs look-at-me to trigger processor and gets into Interrupt Service Routine;
Step 5, the support of real-time assessment is paid attention in the planning of software flow on the risc processor especially.Program on the arm processor is divided into navigation algorithm software and two parts of network communication software.Wherein comprise the Interrupt Process function in the navigation algorithm software, our network communication software just operates in the hardware of Interrupt Process function and hangs up the stage.Like Fig. 5 is to add intermediate frequency data playback and Debugging message interruptions in transmissions function processing flow chart in the embodiment of the invention.Network communication software is accomplished the playback of intermediate frequency data and the statistics of Debugging message, and these codes belong to extracode for navigation algorithm software.If not special processing, these codes can disturb the content of Cache, and under worst condition, processor Cache can replace to the content of extracode fully along with the operation of extracode.When carrying out navigation algorithm software again next time, processor have to from external RAM, read in again code and data, the situation of this and chip actual motion does not meet, and can disturb the assessment of real-time.
For real-time is correctly assessed, get rid of the uncertainty of Cache that extracode is introduced.In this sets of plan, need dispose the Cache support of different region of memorys by means of MMU page management mechanism.According to the difference of system board interconnection mode, MMU also has the various configurations pattern.But basic ideas (embody at chained file) as follows:
But the l memory headroom in MMU, be divided into Cache with can not two zones of Cache;
The stack space of l extracode is used few more well more, perhaps storehouse also point to can not Cache the zone;
The l extracode is mapped to the Non-Cacheable zone, and corresponding to Fig. 5, promptly networkProcess.cpp and dataCollect.cpp compilation unit are placed into the zone of Non-Cacheable.
Its workflow such as Fig. 5, explain below:
Timer triggers the interrupt service routine that once navigates at set intervals, and the interrupt service routine first step is suspended correlator and Abort Timer exactly.It should be noted that this moment delay timer and real-time measurement timer still in operation, promptly the mechanism of delay function Delayus () and code measurement working time still is supported.In the present embodiment, can insert the time interval measurement code in the various piece of interrupt function and master routine.
Step 6, the assessment to former navigation SoC chip system real-time is not disturbed in the support that Debugging message is collected.Increase unified Debugging message data pool, concentrate on same compilation unit dataCollect.It quotes the data of other unit through the mode of extern, need not revise the code of other compilation unit, and the data of collecting will pass to main frame.
In order better in the link script, memory headroom to be divided, make the whole flat scheme have versatility.The programming of this end of RISC should be done following agreement.The content of handling network service (only the break in service at the SoC witness plate takes place) like Fig. 5: networdProcess includes:
L navigation SoC witness plate is to the PC request msg;
L PC navigation SoC chip board transmits the navigation intermediate frequency data, to support data readback;
L navigation SoC witness plate sends Debugging message to PC;
Being collected in the dataCollect.cpp module of Debugging message content carried out, and after the populated content, the networkProcess.cpp module can further be handled the content in the data pool and send to main frame in data pool.Fig. 6 is this pairing MMU configuration and memory-mapped block diagram of embodiment of the invention medium chain pin; Wherein the content of networkProcess.cpp module and dataCollect.cpp module all is the region of memory that is placed on Non-Cahceable, and navigation algorithm interrupt function (except the network service part) and algorithm master routine all are Cacheable.
Cache switch through MMU Single Component Management memory pages.UDP/USB communication extracode drops to minimum to the interference of primal system, can not go to take the Cache space, and the operation of total system will be in close proximity to the ruuning situation of the inner SoC of actual chips system.
Step 6, the PC main frame is set up perfect debugging enironment, cooperates with navigation SoC chip checking plate.Fig. 7 is the truck synoptic diagram of PC mainframe program overall framework and navigation SoC system verification plate in the embodiment of the invention., the simulating, verifying debug platform must provide abundant information to supply the designer to check, so gui interface is essential.PC end debug platform is divided into four threads:
Thread one: the UDP/USB thread, be responsible for transmitting the navigation intermediate frequency data and receiving Debugging message to the SoC system board;
Thread two: database thread, the Debugging message that navigation SoC chip checking plate is sent is stored in the database, to make things convenient for the commissioning staff data is carried out search operaqtion and accessing operation;
Thread three: the graphical interfaces thread, the designer can watch the distribution of satellite, the state and the real-time information of receiver, and the commissioning staff can selectively check, filter information and draw out waveform;
Thread four: debug system master control thread, be used for distributing the distribution of other three thread resources, and the arbitration of communicating by letter between them;
So far, navigation SoC chip emulation, checking and debug platform are built completion.
Whole flat is for the design services of navigation neceiver chip, no matter is the checking of algorithm or the debugging of hardware, and the information that the designer can therefrom obtain enriching is improved original design to revise.One spotlight of this platform is to have added the debugging to real-time; The setting that is configured to MMU from timer; And link writing of script, and all make great efforts for accurately obtaining real-time, make every effort to reduce the interference of debug system itself to original system (SoC itself promptly navigates); Can truly reflect operation result and the real-time information of SoC system in the navigation chip, for next step post-simulation and even flow checking are got ready.
Utilize platform of the present invention can the navigation intermediate frequency data that be stored on the PC main frame be input among the navigation IP through Ethernet or USB interface in an orderly manner; And the commissioning staff can be least unit is controlled total system with the mode of single-step (single step execution) or free-running (free-running operation) operation with the interruption; And can from the feedback result of this system, obtain about the state of software and hardware real-time, each passage of navigation neceiver and the information of navigation calculation various aspects; All these information are sent on the PC from SoC mini system witness plate through UDP or usb protocol; Be stored in background data base subsequently, so that the designer retrieves, reads, shows these information through gui interface (graphic user interface) from database.The navigation algorithm running software is on risc processor, and navigation IP is implemented on the FPGA, and the whole flat operation result approaches the operation result of SoC system in the actual navigation chip as far as possible.Simultaneously; Let the hardware-accelerated IP of navigation support hang-up/execution mechanism through a kind of mechanism; The extracode that this debug platform added does not all have influence to Cache, the interruption real-time of original system, under these measures, can assess the real-time of software and hardware more exactly.
To sum up; The hardware model compatibility of platform of the present invention is by the risc processor of main flows such as ARM, MIPS and the SoC system verification plate of FPGA structures such as Xilinx, Altera; With communicating by letter of PC based on udp protocol or usb protocol; Design and commissioning staff can carry out the control of interrupt levels and the collection of Debugging message, the real-time of accurate assessment software and hardware, compatible multiple navigational system to the operation of navigation SoC system through the PC main frame; Comprising GPS, Galileo, the Big Dipper and GLONASS system, is navigation chip design checking field strong tool.
The above is merely preferred embodiment of the present invention, is not technical scope of the present invention is done any restriction, and all any modifications of within spirit of the present invention and principle, making are equal to replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (10)
1. a navigation SoC chip emulation, checking and debug platform is characterized in that comprising: PC main frame and SoC system verification plate, and the communication between them is carried out through UDP or usb protocol; Said PC main frame passes through UDP or usb protocol and handshake mechanism and accomplishes the importing of intermediate frequency data to SoC system verification plate, and SoC system verification plate is gathered Debugging message and also returned to the PC main frame; Wherein:
Comprise risc processor and fpga chip on the said SoC system verification plate, said fpga chip and risc processor communicate with the interface of bus mode or short time delay, and navigation IP provides with the RTL form, comprehensively is implemented on the FPGA; Realize having the navigation IP of Suspend Mode on the FPGA hardware, move navigation algorithm on the risc processor, in the auxiliary positioning calculation function of accomplishing down of navigation IP.
2. navigation SoC chip emulation according to claim 1, checking and debug platform is characterized in that: said risc processor is realized memory-mapped and Cache management through the MMU memory management unit; The peripheral hardware resource that said risc processor can be controlled will have ethernet controller or USB controller at least, and is connected with the PC main frame; All C/C++ programs of navigating all operate on the risc processor, are divided into master routine and interrupt service routine on the main body; Interrupt service routine is responsible for carrying out alternately with navigation IP, and the information that master routine utilizes interrupt service routine to return calculates coordinate, these two program flows completion satnav of working in coordination.
3. navigation SoC chip emulation according to claim 1 and 2, checking and debug platform; It is characterized in that: said risc processor is supported interrupt mechanism, and the timer resource more than three is arranged, and one of them timer is accomplished the time-delay of set time; Another timer is accomplished and is interrupted setting out; The 3rd timer accomplished the measurement of working time of a plurality of program segment, and these timer resource distributions or are in risc chip inside on FPGA.
4. navigation SoC chip emulation according to claim 1 and 2, checking and debug platform; It is characterized in that: said risc processor can conduct interviews and reads and writes the hardware-accelerated unit that navigates, and FPGA is connected through sheet external bus or PCI-E bus with risc processor.
5. navigation SoC chip emulation according to claim 1 and 2, checking and debug platform; It is characterized in that: said PC main frame is deposited the navigation intermediate frequency data; The PC main frame is shaken hands and is communicated by letter through UDP or usb protocol with the SoC verification system, and the PC main frame has network interface or USB interface.
6. navigation SoC chip emulation, checking and the debug platform narrated according to claim 1 or 2; It is characterized in that: add support in the RTL code of said navigation IP Suspend Mode; The mode that enables with the clk_enable clock realizes; Ppu can change operation/suspended state of navigation IP through the mode of register read-write, makes its time-out, continues then to carry out.
7. navigation SoC chip emulation according to claim 1 and 2, checking and debug platform; It is characterized in that: the interrupt service routine that moves on the said risc processor is divided into the hardware operation phase and hardware is hung up the stage, and hardware is hung up stage PC main frame and imported navigation data through Ethernet/USB interface in batches into to FPGA; FPGA is last to have corresponding FIFO to store these data; The collection of Debugging message and to return also be to accomplish in this in stage.
8. navigation SoC chip emulation according to claim 7, checking and debug platform; It is characterized in that: the hardware at interrupt service routine is hung up the stage; Be sent to the FIFO among the FPGA with the controlled pattern intermediate frequency data that will navigate, FIFO is encapsulated as the peripheral hardware of processor place bus, is mapped to one section zone in the internal memory; Processor writes data with the mode of memory read-write to FIFO in batches, for Hardware I P module provides data; The residue of systems inspection intermediate frequency data FIFO is initiated request of data to PC end in each interrupt function, the PC end is followed the handshake mechanism intermediate frequency data that will navigate and returned to SoC system verification plate; The Debugging message collection procedure of risc processor end with receiver state, Debugging message, resolve result and real-time analytical information and be sent to the PC end and further analyze; These information will be filled whole Ethernet data bag with the form of parcel; The PC host side is accomplished the fractionation and the parsing of these packets more then; Insert the database on backstage subsequently; Gui interface is accomplished the retrieval to database according to operation of designer, takes out these information and represents these information with the form of waveform or form, carries out the debugging that time precision is an interrupt levels; The extracode of these UDP/USB communications is positioned over the zone of Non-Cacheable through the setting of link script and memory management unit MMU.
9. navigation SoC chip emulation according to claim 1 and 2, checking and debug platform; It is characterized in that: said risc processor is through the operation real-time quantification of timer to software and hardware; Accurately the working time of Survey Software code, debug information collection that this platform is introduced and intermediate frequency data playback extracode are through memory-mapped and Cache administrative mechanism; Noiseless basically to the navigation original program, the real-time analysis result is accurate.
10. navigation SoC chip emulation according to claim 1 and 2, checking and debug platform; It is characterized in that: said PC main frame is divided into four threads; Be respectively GUI graphical interfaces thread, debug system master control thread, database thread and UDP/USB communication thread, wherein: the master control thread is responsible for the distribution of resource between other three threads, the arbitration of communication; The UDP/USB communication thread is responsible for communicating with the SoC witness plate; The Debugging message that database thread is come to communications carries out classification and storage, and supports that the user retrieves these information, and database thread also is responsible for calling in of intermediate frequency data data source; Graphical interfaces lets the designer check the operation of Debugging message and real-time information, drawing waveforms and receiver control with mode intuitively.
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