CN102386235B - Thin film transistor (TFT) and manufacture method thereof and utilize the display device of this thin film transistor (TFT) - Google Patents
Thin film transistor (TFT) and manufacture method thereof and utilize the display device of this thin film transistor (TFT) Download PDFInfo
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- CN102386235B CN102386235B CN201110259212.8A CN201110259212A CN102386235B CN 102386235 B CN102386235 B CN 102386235B CN 201110259212 A CN201110259212 A CN 201110259212A CN 102386235 B CN102386235 B CN 102386235B
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- 239000010409 thin film Substances 0.000 title claims abstract description 95
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 30
- 239000004065 semiconductor Substances 0.000 claims abstract description 192
- 239000003863 metallic catalyst Substances 0.000 claims abstract description 138
- 238000005247 gettering Methods 0.000 claims abstract description 119
- 238000009792 diffusion process Methods 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 19
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 19
- 239000010410 layer Substances 0.000 claims description 554
- 229910052751 metal Inorganic materials 0.000 claims description 78
- 239000002184 metal Substances 0.000 claims description 78
- 238000009413 insulation Methods 0.000 claims description 62
- 239000010408 film Substances 0.000 claims description 51
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 47
- 150000002739 metals Chemical class 0.000 claims description 47
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 47
- 229920005591 polysilicon Polymers 0.000 claims description 47
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 44
- 239000011229 interlayer Substances 0.000 claims description 39
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 26
- 125000004429 atoms Chemical group 0.000 claims description 24
- 239000010936 titanium Substances 0.000 claims description 24
- 238000010438 heat treatment Methods 0.000 claims description 21
- 239000010931 gold Substances 0.000 claims description 17
- 229910052759 nickel Inorganic materials 0.000 claims description 17
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 15
- 239000011651 chromium Substances 0.000 claims description 14
- 239000004973 liquid crystal related substance Substances 0.000 claims description 13
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 12
- 229910052737 gold Inorganic materials 0.000 claims description 12
- ZOKXTWBITQBERF-UHFFFAOYSA-N molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 12
- 229910052750 molybdenum Inorganic materials 0.000 claims description 12
- 239000011733 molybdenum Substances 0.000 claims description 12
- RTAQQCXQSZGOHL-UHFFFAOYSA-N titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 12
- 229910052719 titanium Inorganic materials 0.000 claims description 12
- 239000005092 Ruthenium Substances 0.000 claims description 10
- MZLGASXMSKOWSE-UHFFFAOYSA-N Tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 10
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 10
- 229910052803 cobalt Inorganic materials 0.000 claims description 10
- 239000010941 cobalt Substances 0.000 claims description 10
- 239000004020 conductor Substances 0.000 claims description 10
- 239000010949 copper Substances 0.000 claims description 10
- 239000011572 manganese Substances 0.000 claims description 10
- 239000010955 niobium Substances 0.000 claims description 10
- 229910052697 platinum Inorganic materials 0.000 claims description 10
- 239000010948 rhodium Substances 0.000 claims description 10
- KJTLSVCANCCWHF-UHFFFAOYSA-N ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 claims description 10
- 229910052707 ruthenium Inorganic materials 0.000 claims description 10
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminum Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- VYZAMTAEIAYCRO-UHFFFAOYSA-N chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 7
- 229910052804 chromium Inorganic materials 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 7
- 238000007254 oxidation reaction Methods 0.000 claims description 7
- BQCADISMDOOEFD-UHFFFAOYSA-N silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 7
- 229910052709 silver Inorganic materials 0.000 claims description 7
- 239000004332 silver Substances 0.000 claims description 7
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 claims description 7
- 229910052715 tantalum Inorganic materials 0.000 claims description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 7
- 229910052721 tungsten Inorganic materials 0.000 claims description 7
- 239000010937 tungsten Substances 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 230000000875 corresponding Effects 0.000 claims description 6
- 238000005755 formation reaction Methods 0.000 claims description 6
- 229910052692 Dysprosium Inorganic materials 0.000 claims description 5
- VBJZVLUMGGDVMO-UHFFFAOYSA-N Hafnium Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052689 Holmium Inorganic materials 0.000 claims description 5
- QEFYFXOXNSNQGX-UHFFFAOYSA-N Neodymium Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 claims description 5
- 229910052779 Neodymium Inorganic materials 0.000 claims description 5
- 229910052777 Praseodymium Inorganic materials 0.000 claims description 5
- WUAPFZMCVAUBPE-UHFFFAOYSA-N Rhenium Chemical compound [Re] WUAPFZMCVAUBPE-UHFFFAOYSA-N 0.000 claims description 5
- 229910052771 Terbium Inorganic materials 0.000 claims description 5
- 229910045601 alloy Inorganic materials 0.000 claims description 5
- 239000000956 alloy Substances 0.000 claims description 5
- REDXJYDRNCIFBQ-UHFFFAOYSA-N aluminium(3+) Chemical class [Al+3] REDXJYDRNCIFBQ-UHFFFAOYSA-N 0.000 claims description 5
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 5
- 229910052787 antimony Inorganic materials 0.000 claims description 5
- BDOSMKKIYDKNTQ-UHFFFAOYSA-N cadmium Chemical compound [Cd] BDOSMKKIYDKNTQ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052793 cadmium Inorganic materials 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 5
- 229910052802 copper Inorganic materials 0.000 claims description 5
- KBQHZAAAGSGFKK-UHFFFAOYSA-N dysprosium Chemical compound [Dy] KBQHZAAAGSGFKK-UHFFFAOYSA-N 0.000 claims description 5
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 5
- 229910052732 germanium Inorganic materials 0.000 claims description 5
- 229910052735 hafnium Inorganic materials 0.000 claims description 5
- KJZYNXUDTRRSPN-UHFFFAOYSA-N holmium Chemical compound [Ho] KJZYNXUDTRRSPN-UHFFFAOYSA-N 0.000 claims description 5
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052741 iridium Inorganic materials 0.000 claims description 5
- FZLIPJUXYLNCLC-UHFFFAOYSA-N lanthanum Chemical compound [La] FZLIPJUXYLNCLC-UHFFFAOYSA-N 0.000 claims description 5
- 229910052746 lanthanum Inorganic materials 0.000 claims description 5
- PWHULOQIROXLJO-UHFFFAOYSA-N manganese Chemical compound [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 claims description 5
- 229910052748 manganese Inorganic materials 0.000 claims description 5
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 claims description 5
- 229910052758 niobium Inorganic materials 0.000 claims description 5
- SYQBFIAQOQZEGI-UHFFFAOYSA-N osmium Chemical compound [Os] SYQBFIAQOQZEGI-UHFFFAOYSA-N 0.000 claims description 5
- 229910052762 osmium Inorganic materials 0.000 claims description 5
- 229910052763 palladium Inorganic materials 0.000 claims description 5
- PUDIUYLPXJFUGB-UHFFFAOYSA-N praseodymium Chemical compound [Pr] PUDIUYLPXJFUGB-UHFFFAOYSA-N 0.000 claims description 5
- 229910052702 rhenium Inorganic materials 0.000 claims description 5
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 claims description 5
- 229910052703 rhodium Inorganic materials 0.000 claims description 5
- SIXSYDAISGFNSX-UHFFFAOYSA-N scandium Chemical compound [Sc] SIXSYDAISGFNSX-UHFFFAOYSA-N 0.000 claims description 5
- 229910052706 scandium Inorganic materials 0.000 claims description 5
- 229910021332 silicide Inorganic materials 0.000 claims description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 5
- GZCRRIHWUXGPOV-UHFFFAOYSA-N terbium Chemical compound [Tb] GZCRRIHWUXGPOV-UHFFFAOYSA-N 0.000 claims description 5
- ATJFFYVFTNAWJD-UHFFFAOYSA-N tin hydride Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 5
- 229910052720 vanadium Inorganic materials 0.000 claims description 5
- LEONUFNNVUYDNQ-UHFFFAOYSA-N vanadium(0) Chemical compound [V] LEONUFNNVUYDNQ-UHFFFAOYSA-N 0.000 claims description 5
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 claims description 5
- 229910052727 yttrium Inorganic materials 0.000 claims description 5
- QCWXUUIWCKQGHC-UHFFFAOYSA-N zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 claims description 5
- 229910052726 zirconium Inorganic materials 0.000 claims description 5
- 238000000059 patterning Methods 0.000 claims description 3
- 238000002425 crystallisation Methods 0.000 description 40
- 230000005712 crystallization Effects 0.000 description 27
- 239000003990 capacitor Substances 0.000 description 11
- 239000003054 catalyst Substances 0.000 description 8
- 239000003795 chemical substances by application Substances 0.000 description 7
- 239000007789 gas Substances 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 230000003197 catalytic Effects 0.000 description 5
- 239000012212 insulator Substances 0.000 description 5
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- 230000003321 amplification Effects 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N Silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910004205 SiNX Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000007792 gaseous phase Substances 0.000 description 2
- 230000001939 inductive effect Effects 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N oxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000004033 plastic Substances 0.000 description 2
- 229920003023 plastic Polymers 0.000 description 2
- 239000007790 solid phase Substances 0.000 description 2
- 238000003892 spreading Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 229910005883 NiSi Inorganic materials 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 230000003139 buffering Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000007715 excimer laser crystallization Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000005984 hydrogenation reaction Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910052904 quartz Inorganic materials 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
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Abstract
The invention discloses a kind of thin film transistor (TFT) and manufacture method thereof and utilize the display device of this thin film transistor (TFT).This thin film transistor (TFT) includes: substrate, offer are on the substrate and by utilizing the crystallized semiconductor layer of metallic catalyst and described semiconductor layer insulate and are arranged on the gate electrode on described semiconductor layer and are arranged on the gettering layer between described semiconductor layer and described gate electrode, described gettering layer utilizes the metal-oxide with the diffusion coefficient less than the diffusion coefficient of the metallic catalyst in described semiconductor layer to be formed.
Description
Technical field
Described technology generally relates to thin film transistor (TFT) and manufacture method thereof and has this thin film transistor (TFT)
Display device.More specifically, described technology generally relates to include by utilizing metallic catalyst
The thin film transistor (TFT) of crystallized polysilicon layer and manufacture method thereof and there is the display of this thin film transistor (TFT)
Equipment.
Background technology
Most of flat panel display equipments, such as Organic Light Emitting Diode (OLED) display, liquid crystal
Show device (LCD) etc., including thin film transistor (TFT).Especially, there is the low temperature of good carrier mobility
Polycrystalline SiTFT (LTPS TFT) can apply to high-speed cruising circuit, and can be used for CMOS
Circuit, therefore LTPS TFT has been commonly used.
LTPS TFT includes the polysilicon film formed by amorphous silicon film is carried out crystallization.
It is only used for strengthening the reason to described technical background in the information above disclosed in this background section
Solving, therefore it can comprise and not be formed in the prior art that this country has been known to those of ordinary skill in the art
Information.
Summary of the invention
Exemplary embodiment provides a kind of thin film transistor (TFT), including: substrate, be positioned on described substrate and
By utilizing the crystallized semiconductor layer of metallic catalyst insulate with described semiconductor layer and be set
Gate electrode on described semiconductor layer and being arranged between described semiconductor layer and described gate electrode
Gettering layer, the utilization of described gettering layer has less than the diffusion coefficient of the metallic catalyst in described semiconductor layer
The metal-oxide of diffusion coefficient is formed.
The diffusion coefficient of described gettering layer can be more than 0 and less than the diffusion coefficient of described metallic catalyst
1/100。
Described thin film transistor (TFT) may further include: is arranged between described substrate and described semiconductor layer
Cushion.Described metallic catalyst can be with from 1.0e12 atom/cm2To 1.0e15 atom/cm2In the range of
Area density is disperseed between described cushion and described semiconductor layer.
Described metallic catalyst can be with from 1.0e12 atom/cm2To 1.0e15 atom/cm2In the range of surface
Density is disperseed on described semiconductor layer.
Described metallic catalyst can include nickel (Ni), palladium (Pd), titanium (Ti), silver (Ag), gold (Au),
Stannum (Sn), antimony (Sb), copper (Cu), cobalt (Co), molybdenum (Mo), terbium (Tb), ruthenium (Ru), cadmium (Cd)
At least one of platinum (Pt).
Described gettering layer can include scandium (Sc), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium
(Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), manganese (Mn), rhenium (Re), ruthenium (Ru),
Osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), platinum (Pt), yttrium (Y), lanthanum (La), germanium (Ge),
Praseodymium (Pr), neodymium (Nd), dysprosium (Dy), holmium (Ho), aluminum (Al), titanium nitride (TiN) and tantalum nitride (TaN),
At least one of its alloy or its silicide.
Described thin film transistor (TFT) may further include: is arranged between described gettering layer and described semiconductor layer
Gate insulation layer.
Described thin film transistor (TFT) may further include: covers the interlayer insulating film of described gate electrode, be formed at institute
State the source electrode on interlayer insulating film and be formed on described interlayer insulating film and and described source electrode be spaced
The drain electrode opened.
Multiple contact holes can extend through described interlayer insulating film, described gettering layer and described gate insulation layer with dew
Go out the appropriate section of described semiconductor layer, and described source electrode and described drain electrode are connect by corresponding contact hole
Touch the described appropriate section of described semiconductor layer.
Described thin film transistor (TFT) may further include: is arranged between described gettering layer and described semiconductor layer
Gate insulation layer, described gate insulation layer utilizes described semiconductor layer to be patterned, and described gettering layer is permissible
Contact the side of described semiconductor layer.
Described thin film transistor (TFT) may further include: is arranged between described gettering layer and described gate electrode
Gate insulation layer.Described gettering layer can contact described semiconductor layer, and described gettering layer and described quasiconductor
Layer can have identical pattern.
Exemplary embodiment provides a kind of method manufacturing thin film transistor (TFT), including: substrate is provided；At described base
Amorphous silicon layer is formed on plate；By utilizing metallic catalyst that described amorphous silicon layerization is formed polysilicon layer；
Forming semiconductor layer by described polysilicon layer carries out patterning, described semiconductor layer includes the gold of residual volume
Metal catalyst；Described semiconductor layer is formed gate insulation layer；Described gate insulation layer is formed multiple air-breathing
Hole；Described gate insulation layer forms getter metals layer to contact described quasiconductor by the plurality of suction hole
Layer；And while described getter metals layer being aoxidized by heat treatment process, form gettering layer, and
And reduce the density of the metallic catalyst being included in described semiconductor layer.
Described method may further include: forms gate electrode on described gettering layer so that quasiconductor described in imbrication
The region of layer；Form interlayer insulating film to cover described gate electrode；Form multiple contact hole to penetrate described layer
Between insulating barrier, described gettering layer and described gate insulation layer and expose source part and the leakage part of described semiconductor layer；
And on described interlayer insulating film, form source electrode and drain electrode, with by the plurality of contact holes contact institute
State semiconductor layer.
The plurality of contact hole can be with the plurality of suction hole of imbrication.
When forming the plurality of contact hole, being contacted by the plurality of suction hole of described gettering layer can be eliminated
The part of described semiconductor layer.
Exemplary embodiment provides a kind of method manufacturing thin film transistor (TFT), including: substrate is provided；At described base
Amorphous silicon layer is formed on plate；By utilizing metallic catalyst that described amorphous silicon layer is formed polysilicon
Layer；Described polysilicon layer coats insulant；By to described polysilicon layer and described insulant figure
Case forms semiconductor layer and gate insulation layer with identical patterns；Described gate insulation layer is formed getter metals layer
To contact the side of described semiconductor layer；And by heat treatment process, the oxidation of described getter metals layer is formed
Gettering layer, and reduce the density of the metallic catalyst being included in described semiconductor layer.
Exemplary embodiment provides a kind of method manufacturing thin film transistor (TFT), including: substrate is provided；At described base
Amorphous silicon layer is formed on plate；By utilizing metallic catalyst that described amorphous silicon layerization is formed polysilicon layer；
Described polysilicon layer is formed getter metals layer；By heat treatment process, described getter metals layer is carried out oxygen
Change, and reduce the density of the metallic catalyst being included in described semiconductor layer；By to described polysilicon
Getter metals pattern layers after layer and described oxidation forms semiconductor layer and gettering layer with identical patterns；And
Described gettering layer is formed gate insulation layer.
Described gettering layer can utilize have less than the diffusion coefficient of the metallic catalyst in described semiconductor layer
The metal-oxide of diffusion coefficient is formed.
The diffusion coefficient of described gettering layer can be more than 0 and less than the diffusion coefficient of described metallic catalyst
1/100。
Described method may further include: forms cushion between described substrate and described amorphous silicon layer.Institute
Stating metallic catalyst can be with from 1.0e12 atom/cm2To 1.0e15 atom/cm2In the range of area density exist
Disperse between described cushion and described amorphous silicon layer.
Described metallic catalyst can be with from 1.0e12 atom/cm2To 1.0e15 atom/cm2In the range of surface
Density is disperseed on described amorphous silicon layer.
Described metallic catalyst can include nickel (Ni), palladium (Pd), titanium (Ti), silver (Ag), gold (Au),
Stannum (Sn), antimony (Sb), copper (Cu), cobalt (Co), molybdenum (Mo), terbium (Tb), ruthenium (Ru), cadmium (Cd)
At least one of platinum (Pt).
Described gettering layer can include scandium (Sc), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium
(Nb), tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), manganese (Mn), rhenium (Re), ruthenium (Ru),
Osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), platinum (Pt), yttrium (Y), lanthanum (La), germanium (Ge),
Praseodymium (Pr), neodymium (Nd), dysprosium (Dy), holmium (Ho), aluminum (Al), titanium nitride (TiN) and tantalum nitride
(TaN), at least one of its alloy or its silicide.
Described heat treatment process can be performed at a temperature of 400 to 993 degrees Celsius.
Exemplary embodiment provides a kind of display device, including: substrate, is positioned on described substrate and by profit
Insulate with the crystallized semiconductor layer of metallic catalyst and described semiconductor layer and be arranged on described half
Gate electrode on conductor layer, the gettering layer being arranged between described semiconductor layer and described gate electrode, described
Gettering layer utilizes the gold with the diffusion coefficient less than the diffusion coefficient of the metallic catalyst in described semiconductor layer
Genus oxide formation, the source region contacting described semiconductor layer and the source electrode spaced apart with described gate electrode,
And contact the drain region of described semiconductor layer and the electric leakage spaced apart with described gate electrode and described source electrode
Pole.
Described display device may further include: is arranged between described gettering layer and described semiconductor layer
Gate insulation layer.
Described display device may further include: covers the interlayer insulating film of described gate electrode, wherein said source
Electrode is formed on described interlayer insulating film, and described drain electrode is formed on described interlayer insulating film and with
Described source electrode is spaced apart.
Multiple contact holes can extend through described interlayer insulating film, described gettering layer and described gate insulation layer with dew
Go out the part of described semiconductor layer.Described source electrode and described drain electrode can be by described contact holes contact institutes
State the described part of semiconductor layer.
Described display device may further include: is arranged between described gettering layer and described semiconductor layer
Gate insulation layer, described gate insulation layer is patterned with the pattern identical with described semiconductor layer.Described gettering layer
The side of described semiconductor layer can be contacted.
Described display device may further include: is arranged on the grid between described gettering layer and described gate electrode
Insulating barrier.Described gettering layer can contact described semiconductor layer, and described gettering layer and described semiconductor layer
Can have identical pattern.
Described display device may further include: is connected to the Organic Light Emitting Diode of described drain electrode.
Described display device may further include: be connected to described drain electrode pixel electrode, be formed at described
Liquid crystal layer on pixel electrode and formation public electrode on the liquid crystal layer.
Accompanying drawing explanation
Describing exemplary embodiment in detail by referring to accompanying drawing, above and other feature and advantage are for ability
Will be apparent from for the ordinary skill of territory, in the accompanying drawings:
Fig. 1 illustrates the top view of the display device with thin film transistor (TFT) according to exemplary embodiment.
Fig. 2 illustrates the circuit diagram of the image element circuit of display device shown in Fig. 1.
Fig. 3 illustrates the amplification sectional view of the thin film transistor (TFT) according to this exemplary embodiment.
Fig. 4 to Fig. 8 illustrates the sequential cross-sectional views of the manufacture process of thin film transistor (TFT) as shown in Figure 3.
Fig. 9 illustrates the amplification sectional view of the thin film transistor (TFT) according to another exemplary embodiment.
Figure 10 to Figure 12 illustrates the sequential cross-sectional views of the manufacture process of thin film transistor (TFT) as shown in Figure 9.
Figure 13 illustrates according to the amplification sectional view of the thin film transistor (TFT) of exemplary embodiment after improving.
Figure 14 illustrates the amplification sectional view of the thin film transistor (TFT) according to another exemplary embodiment.
Figure 15 and Figure 16 illustrates the sequential cross-sectional views of the manufacture process of thin film transistor (TFT) as shown in figure 14.
Figure 17 illustrates the equivalent circuit of the image element circuit of the display device according to another exemplary embodiment.
Detailed description of the invention
Hereinafter with reference to accompanying drawing, example embodiment is more fully described now, but, these
Embodiment can the most specifically embody, and should not be construed as limited to presented herein
Embodiment.But, these embodiments are provided to present disclosure in detail with complete, and to ability
Field technique personnel fully pass on the scope of the present invention.
In the accompanying drawings, layer and region size perhaps to diagram clear for the sake of be exaggerated.Also should manage
Solve, when one layer or element be mentioned another layer or substrate " on " time, it can be directly at this another layer
Or on substrate, or intermediate layer can also be there is.Further, it should be understood that when one layer is mentioned separately
Time one layer " below ", it can be directly below, and can also there is one or more intermediate layer.Separately
Outward, it is also understood that when one layer be mentioned two-layer " between " time, it can be between this two-layer
Sole layer, or one or more intermediate layer can also be there is.Identical reference represents identical all the time
Element.
It addition, for the sake of clearly describing each aspect of the present invention, be omitted with describing incoherent part.
And, the exemplary embodiment in some exemplary embodiments, in addition to the first exemplary embodiment
Can be described only for the parts different from the parts of the first exemplary embodiment.
Describe the thin film transistor (TFT) 11 according to exemplary embodiment now with reference to Fig. 1 to Fig. 3 and have
The display device 101 of this thin film transistor (TFT).
As it is shown in figure 1, display device 101 can include being divided into viewing area (DA) and non-display
The substrate 111 in region (NA).Multiple pixel regions (PE) can be formed at viewing area (DA)
Middle display image, and drive circuit 910 and 920 can be formed in non-display area (NA).Pixel
Region (PE) represents the region being formed with the pixel for showing image.But, as described above that
Sample, drive circuit 910 and 920 neither of which needs to be formed in non-display area (NA), and it
One or two in can be omitted.
As in figure 2 it is shown, display device 101 can represent the organic light-emitting diodes with 2Tr-1Cap configuration
Pipe (OLED) display, this configuration pin includes Organic Light Emitting Diode to each pixel region (PE)
70, thin film transistor (TFT) (TFT) 11 and 21 and capacitor 80.But, display device is not limited to
Configuration described above.Therefore, display device 101 can represent that each pixel region (PE) includes
Organic Light Emitting Diode (OLED) display of three or more thin film transistor (TFT) and at least two capacitor
Device.Further, display device 101 can be formed as having the other configuration with extra wiring.Cause
This, at least one thin film transistor (TFT) being additionally formed and capacitor can configure compensation circuit.
Compensating circuit can be by improving the Organic Light Emitting Diode formed in each pixel region (PE)
The uniformity of 70 suppresses the generation of picture quality deviation.It is said that in general, compensate circuit can include that 2 arrive
8 thin film transistor (TFT)s.
And, the drive circuit 910 formed in the non-display area (NA) of substrate 111 shown in Fig. 1
Other thin film transistor (TFT) can be included with 920.
Organic Light Emitting Diode 70 can include the anode electrode as hole injecting electrode, as electronics
The cathode electrode of injecting electrode and be arranged on the organic emission layer between described anode and described negative electrode.
In detail, for each pixel region (PE), display device 101 can include that the first film is brilliant
Body pipe 11 and the second thin film transistor (TFT) 21.The first film transistor 11 and the second thin film transistor (TFT) 21 can
To include gate electrode, active layer, source electrode and drain electrode respectively.
Gate line (GL), data wire (DL) and public power wire (VDD) are together with capacitor line (CL)
It is illustrated in fig. 2 together, but the invention is not restricted to this.Therefore, capacitor line (CL) can depend on
It is omitted according to situation.
Data wire (DL) can be connected to the source electrode of the second thin film transistor (TFT) 21, and gate line (GL)
The gate electrode of the second thin film transistor (TFT) 21 can be connected to.The drain electrode of the second thin film transistor (TFT) 21 is permissible
It is connected to capacitor line (CL) by capacitor 80.Node can be formed at the second thin film transistor (TFT) 21
Drain electrode and capacitor 80 between, and the gate electrode of the first film transistor 11 can be connected to.
The drain electrode of the first film transistor 11 can be connected to public power wire (VDD), and the first film
The source electrode of transistor 11 can be connected to the anode of Organic Light Emitting Diode 70.
Second thin film transistor (TFT) 21 can serve as switching for selecting pixel region (PE) next luminous.
When the second thin film transistor (TFT) 21 turns on, capacitor 80 is electrically charged, and charge volume in this case
Can be proportional to the voltage potential supplied from data wire (DL).End at the second thin film transistor (TFT) 21
While, when the signal with the voltage being increased for every frame is input to capacitor line (CL),
The gate potential of the first film transistor 11 can pass through electric capacity according to based on gesture charged in capacitor 80
Voltage level that device line (CL) applies and increase.The first film transistor 11 exceeds threshold value at gate potential
Turn on during voltage.The voltage being applied to public power wire VDD can pass through the first film transistor 11 quilt
It is applied to Organic Light Emitting Diode 70, and Organic Light Emitting Diode 70 is luminous.
The configuration of pixel region (PE) is not limited to above description, but can be by those skilled in the art at this
Change in every way in the range of inventive embodiment.
Referring now to Fig. 3, the configuration of the thin film transistor (TFT) 11 according to exemplary embodiment is described.
Thin film transistor (TFT) 11 can represent the first film transistor shown in Fig. 2.The second thin film shown in Fig. 2 is brilliant
Body pipe 21 can have the configuration identical with thin film transistor (TFT) 11, or can have different configurations.
Substrate 111 can utilize the transparent insulation substrate of glass, quartz, pottery or plastics to be formed.But,
Substrate 111 is not limited to this, but substrate 111 can also be formed as stainless metal basal board.And,
When substrate 111 is made of plastics, it can be formed as flexible base board.
Cushion 120 can be formed on substrate 111.Cushion 120 can be by utilizing chemical gaseous phase
Deposition or physical vapour deposition (PVD) are formed as monolayer or include at least one of silicon oxide layer and silicon nitride layer
Multilamellar.
Cushion 120 can be by preventing dampness produced by substrate 111 or the diffusion of impurity or logical
Cross and control the transfer rate of heat during crystallization, and contribute to the crystallization of amorphous silicon layer.
By utilizing the semiconductor layer 131 of metallic catalyst and crystallization can be formed at cushion 120
On.Semiconductor layer 131 can be by being formed the amorphous silicon layer formed on cushion 120
Polysilicon layer, then patterns this polysilicon layer and is formed.Metallic catalyst is for non-crystalline silicon
Layer crystallization, and the metallic catalyst of residual volume can stay in the semiconductor layer 131 after crystallization.
In the present example embodiment, super grain silicon (SGS) crystallization method can be used.SGS
Crystallization method, will by the concentration of the metallic catalyst spreading to amorphous silicon layer being controlled to low concentration
The size of crystal grain control from several μm to hundreds of μm.Metallic catalyst scatter with low concentration, thus will
The concentration of the metallic catalyst spreading to amorphous silicon layer controls to low concentration.
SGS crystallization method can at low temperatures within the relatively short time to amorphous silicon layer.Example
As, for by utilizing nickel (Ni) as the metallic catalyst process to amorphous silicon layer, nickel (Ni)
Can combine with the silicon (Si) in amorphous silicon layer to become nickel disilicide (NiSi2).Nickel disilicide (NiSi2)
The seed cultivating crystal can be served as.
Therefore, by metallic catalyst the polysilicon layer of crystallization can to have the crystal grain of tens μm big
Little, this can be more than the grain size of solid phase crystallization (SPC) polysilicon layer.
And, in the case of the polysilicon layer formed by SGS crystallization method, many sub-crystal grain limits
Boundary may reside in single grain boundary, thus minimize the uniformity caused due to grain boundary and deteriorate.
Further, the thin film transistor (TFT) 11 of the polysilicon layer that utilization is formed by SGS crystallization method can
To have relatively high current d pivability energy, namely electron mobility, but it is likely to be due to remain in
Metallic catalyst in semiconductor layer 131 and there is relatively high leakage current.But, according to this example
Property embodiment, leakage current can remain in the amount of metallic catalyst in semiconductor layer 131 by reduction
And be inhibited.
In detail, before amorphous silicon layer is formed on cushion 120, metallic catalyst can with from
1.0e12 atom/cm2To 1.0e15 atom/cm2In the range of area density be dispersed on cushion 120.
Metallic catalyst can occur between cushion 120 and amorphous silicon layer.Less amount of metallic catalyst can
To be dispersed on cushion 120 as molecule.It is formed to be less than 1.0e12 atom at metallic catalyst
/cm2Area density time, the core of the quantity of seed, i.e. crystallization can be less, and is likely difficult to root
According to SGS crystallization method, amorphous silicon layer sufficient crystallising is become polysilicon layer.On the other hand, at metal catalytic
Agent is formed to be larger than 1.0e15 atom/cm2Area density time, spread to the metal catalytic of amorphous silicon layer
The gold that the quantity of agent may be increased to reduce the crystal grain of polysilicon layer and increase remains in polysilicon layer
The quantity of metal catalyst.Therefore, the semiconductor layer 131 formed by polysilicon layer is patterned
Characteristic may be degraded.
This exemplary embodiment is not limited to foregoing description.Crystallization inducing metal (MIC) method or metal
Induced lateral crystallization (MILC) method can be used for utilizing the crystallization method of metallic catalyst.
Metallic catalyst can not be dispersed between cushion 120 and amorphous silicon layer, but is dispersed in
On the top of amorphous silicon layer.But, it is arranged under amorphous silicon layer at metallic catalyst to cultivate crystal
Time, be arranged on metallic catalyst on amorphous silicon layer with cultivate crystal situation compared with, grain boundary
May become more to obscure, and the defect in crystal grain may be further reduced.
Metallic catalyst can include nickel (Ni), palladium (Pd), titanium (Ti), silver (Ag), gold (Au),
Stannum (Sn), antimony (Sb), copper (Cu), cobalt (Co), molybdenum (Mo), terbium (Tb), ruthenium (Ru),
At least one of cadmium (Cd) and platinum (Pt).Such as, nickel (Ni) can serve as metallic catalyst.Logical
Cross the nickel disilicide (NiSi that the combination of nickel (Ni) and silicon (Si) produces2) crystal can be effectively facilitated
Long.
Gate insulation layer 140 can be formed on semiconductor layer 131.Gate insulation layer 140 can be formed as covering
Semiconductor layer 131 on lid cushion 120.Gate insulation layer 140 can include such as tetraethyl orthosilicate
(TEOS), silicon nitride (SiNX) or silicon oxide (SiO2) at least one insulant.
Gettering layer (getter layer) 135 can be formed on gate insulation layer 140.Gettering layer 135 is permissible
Utilize the metal oxygen with the diffusion coefficient lower than the diffusion coefficient of the metallic catalyst in semiconductor layer 131
Compound is formed.In detail, the diffusion coefficient of gettering layer 135 can be more than 0 and less than metal catalytic
The 1/100 of the diffusion coefficient of agent.
When the diffusion coefficient of gettering layer 135 equals to or less than the 1/100 of metallic catalyst, gettering layer 135
Can effectively absorb the metallic catalyst in semiconductor layer 131.
Nickel as metallic catalyst has 10 in semiconductor layer 131-5cm2The diffusion system of/s or less
Number.Therefore, in the case of nickel (Ni) is used for metallic catalyst, gettering layer 135 has more than 0
And less than 10-7cm2The diffusion coefficient of/s is probably effectively.For forming the getter metals of gettering layer 135
Can be scandium (Sc), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb),
Tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), manganese (Mn), rhenium (Re), ruthenium (Ru),
At least one of osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir) and platinum (Pt).It also may be used
To be yttrium (Y), lanthanum (La), germanium (Ge), praseodymium (Pr), neodymium (Nd), dysprosium (Dy), holmium
(Ho), at least one of aluminum (Al), titanium nitride (TiN) and tantalum nitride (TaN).And,
Alloy or their silicide of metal described above can be used for getter metals.
Gettering layer 135 can form getter metals layer and to this getter metals layer by utilizing getter metals
Heat treatment is applied to be formed.This heat treatment process is performing at a temperature of 400 to 993 degrees Celsius.
When getter metals layer is heated, getter metals layer can be oxidized to become gettering layer 135.And,
During heat treatment process, the metallic catalyst in semiconductor layer 131 at least partly can pass through air-breathing
Layer 135 is removed.
For the process for eliminating the metallic catalyst in semiconductor layer 131, as heat treatment process
As a result, remain in the metallic catalyst in semiconductor layer 131 at least partly can move to semiconductor layer
The part of the contact getter metals layer of 131.In this case, metallic catalyst can be deposited in suction
On gas metal level, and can no longer migrate, this is because keep and air-breathing for metallic catalyst
Metal level contact gear ratio is stayed in semiconductor layer 131 thermodynamically more stable.Therefore, remain in and partly lead
At least partly can being removed of metallic catalyst in body layer 131.
The place that gettering layer 135 engages semiconductor layer 131 is not shown in FIG. 3, this is because gettering layer
This part of 135 is eliminated during forming the process of contact hole 166 and 167 to describe.
It is removed owing to gettering layer 135 contacts the part of semiconductor layer 131, the therefore characteristic of thin film transistor (TFT) 11
Deteriorate due to remained less metallic catalyst and by more stable suppression.
The gettering layer 135 utilizing metal-oxide to be formed can have in the range of several nm to tens nm
Thickness.Gettering layer 135 can serve as insulator with supply gate insulating barrier 140.Have at gettering layer 135
When having the thickness less than several nm, effectively remove metallic catalyst and may become highly difficult.On the other hand,
When gettering layer 135 has the thickness more than tens nm, thermal stress may be produced in heat treatment process.
Gate electrode 151 can be formed on gettering layer 135.Gate electrode 151 can be configured to imbrication half
The region of conductor layer 131.Gate electrode 151 can include molybdenum (Mo), chromium (Cr), aluminum (Al),
At least one of silver (Ag), titanium (Ti), tantalum (Ta) and tungsten (W).
Interlayer insulating film 160 can be formed at gate electrode 151.Interlayer insulating film 160 can be in air-breathing
Covering grid electrode 151 above layer 135.Interlayer insulating film 160 can be similar with gate insulation layer 140 by
Tetraethyl orthosilicate (TEOS), silicon nitride (SiNX) or silicon oxide (SiO2) formed, but do not limit
In this.
Contact hole 166 and 167 can extend through interlayer insulating film 160, gettering layer 135 and gate insulation
Layer 140 is to expose the appropriate section of semiconductor layer 131.
Source electrode 176 and the drain electrode 177 of contact semiconductor layer 131 can pass through corresponding contact hole 166
It is formed on interlayer insulating film 160 with 167.Source electrode 176 can be spaced apart with drain electrode 177.With
Gate electrode 151 similarly, source electrode 176 and drain electrode 177 can include molybdenum (Mo), chromium (Cr),
At least one of aluminum (Al), silver (Ag), titanium (Ti), tantalum (Ta) and tungsten (W).
According to configuration as above, thin film transistor (TFT) 11 can have by utilizing metallic catalyst to exist
Crystallized semiconductor layer 131 at low temperatures and in the short time, and this semiconductor layer 131 remains
The amount of metallic catalyst can effectively be reduced.
And, display device 101 can have the thin film transistor (TFT) 11 with semiconductor layer 131, at this
In semiconductor layer 131, the amount of metallic catalyst may the most effectively be reduced.
Describe now with reference to Fig. 4 to Figure 10 and manufacture thin film transistor (TFT) 11 according to exemplary embodiment
Method.
First, as shown in Figure 4, cushion 120 can be formed on substrate 111.Cushion 120 can
With by utilizing chemical gaseous phase deposition or physical vapour deposition (PVD) are formed as monolayer or include silicon oxide layer and nitridation
Multilamellar at least one of silicon layer.
Metallic catalyst can be with from 1.0e12 atom/cm2To 1.0e15 atom/cm2In the range of surface close
Degree is dispersed on cushion 120.Lesser amount of metallic catalyst can be dispersed in cushion as molecule
On 120.Such as, nickel can serve as metallic catalyst.
Amorphous silicon layer can be formed on cushion 120.And, when amorphous silicon layer is formed or form it
After, can perform the concentration for reducing hydrogen removes hydrogenation process.Amorphous silicon layer can being crystallized with shape
Become polysilicon layer.When amorphous silicon layer is heated, the metallic catalyst (MC) being dispersed on cushion 120
The growth of crystal can be promoted.Metallic catalyst can control amorphous silicon layer within the relatively short time and
Being crystallized under low temperature.
This exemplary embodiment is not limited to above description.Therefore, metallic catalyst can be directly dispersing in
On amorphous silicon layer rather than be dispersed on cushion 120.
Semiconductor layer 131 can be formed by patterning the polysilicon layer after crystallization.?
In this case, the metallic catalyst for crystallization can be stayed in semiconductor layer 131.
As shown in Figure 5, gate insulation layer 140 can be formed on semiconductor layer 131.Gate insulation layer 140
Multiple suction holes 146 and 147 of part for exposing semiconductor layer 131 can be patterned to form.
As shown in Figure 6, getter metals layer can be formed on gate insulation layer 140.Getter metals layer can
To contact semiconductor layer 131 with 147 by multiple suction holes 146.
Getter metals layer can be less than the diffusion coefficient of the metallic catalyst in semiconductor layer 131 by having
The metal of diffusion coefficient is formed.In detail, the diffusion coefficient at getter metals layer equals to or less than gold
The diffusion coefficient of metal catalyst 1/100 time, the metallic catalyst in semiconductor layer 131 can be by effectively
Remove.
Gettering layer 135 can be formed by aoxidizing getter metals layer via heat treatment process.Inhale
Gas-bearing formation 135 can utilize has the diffusion less than the diffusion coefficient of the metallic catalyst in semiconductor layer 131
The metal-oxide of coefficient is formed.
While forming gettering layer 135 by heat treatment process, it is included in the gold in semiconductor layer 131
The density of metal catalyst can be reduced.Remain at least some metallic catalyst in semiconductor layer 131
Can be eliminated.During heating treatment, at least some metallic catalyst in semiconductor layer 131 is remained in
Move to the part touching getter metals layer of semiconductor layer.Have moved the metal catalytic of getter metals layer
Agent can be deposited on getter metals layer, and can no longer spread, this is because for metallic catalyst
For contact getter metals layer rather than occur in and semiconductor layer 131 be probably more stable.It is included in
The amount of the metallic catalyst in semiconductor layer 131 may be reduced.
And, gettering layer 135 can utilize the thickness from several nm to tens nm to be formed.
As shown in Figure 7, gate electrode 151 can be formed on gettering layer 135.Gettering layer 135 is permissible
As insulator, this is to be formed by metal-oxide due to it.Gettering layer 135 can be exhausted with supply gate
Edge layer 140.
As shown in Figure 8, the interlayer insulating film 160 of covering grid electrode 151 can be formed.Across-layer
Between insulating barrier 160, gettering layer 135 and gate insulation layer 140 expose the appropriate section of semiconductor layer 131
Contact hole 166 and 167 can be formed.
Contact hole 166 and 167 can be formed at the air-breathing in gate insulation layer 140 as shown in Figure 6 with imbrication
Hole 146 and 147.When contact hole 166 and 167 is formed, gettering layer 135 by suction hole 146
The part contacting semiconductor layer 131 with 147 can be eliminated.
As shown in Figure 3, source electrode 176 and drain electrode 177 can be formed with gap between which.
By manufacture method described above, the thin film transistor (TFT) 11 according to this exemplary embodiment can
To be produced.It is to say, the metallic catalyst being included in semiconductor layer 131 can effectively be inhaled
Gas.
Now with reference to Fig. 9, the thin film transistor (TFT) 12 according to another exemplary embodiment is described.
As shown in Figure 9, cushion 120 can be formed on substrate 111, and by utilizing metal
The crystallized semiconductor layer of catalyst 131 can be formed on cushion 120.Metallic catalyst is permissible
For to semiconductor layer 131 crystallization, and its part can be stayed in the semiconductor layer after crystallization.
The gate insulation layer 240 utilizing semiconductor layer 131 to pattern can be formed on semiconductor layer 131.
Gate insulation layer 240 can be formed, except be described below with the pattern identical with semiconductor layer 131
Outside contact hole 166 and 167.It is to say, in the present example embodiment, gate insulation layer 240 is not
It is directly formed on cushion 120.
Gettering layer 235 can be formed on gate insulation layer 240.Gettering layer 235 can utilize has ratio half
The metal-oxide of the diffusion coefficient that the diffusion coefficient of the metallic catalyst in conductor layer 131 is little is formed.
In the present example embodiment, gettering layer 235 can be formed as covering semiconductor layer 131 and gate insulation layer
240, and cushion 120 can be contacted.In this case, gettering layer 235 can be formed as contact
The side of semiconductor layer 131.Staying the metallic catalyst in semiconductor layer 131 can be at gettering layer 235
The place of contact semiconductor layer 131 is eliminated.
And, the gettering layer 235 being made up of metal-oxide can have from several nm to tens nm's
Thickness, and can serve as insulator to support gate insulation layer 240.
Gate electrode 151 can be formed on gettering layer 235.Gate electrode 151 can be configured to imbrication half
The region of conductor layer 131.
Interlayer insulating film 160 can be formed on gate electrode 151.It is to say, interlayer insulating film 160
Can on gettering layer 235 covering grid electrode 151.
Contact hole 166 and 167 can extend through interlayer insulating film 160, gettering layer 235 and gate insulation
Layer 240 is to expose the appropriate section of semiconductor layer 131.
Source electrode 176 and the drain electrode 177 of contact semiconductor layer 131 can pass interlayer insulating film 160
On contact hole 166 and 167 and formed.Source electrode 176 can be spaced apart with drain electrode 177.
By configuration described above, can have according to the thin film transistor (TFT) 12 of this exemplary embodiment
By utilizing metallic catalyst at low temperatures by the semiconductor layer 131 of fast crystallization, and from this partly
The amount of the metallic catalyst of conductor layer 131 is effectively reduced.
Now with reference to Figure 10 to Figure 12 to the manufacture thin film transistor (TFT) 12 according to this exemplary embodiment
Method be described.
Cushion 120 can be formed on substrate 111, and metallic catalyst can be with former from 1.0e12
Son/cm2To 1.0e15 atom/cm2In the range of area density be dispersed on cushion 120.Such as,
Nickel may be used for metallic catalyst.
Amorphous silicon layer can be formed on cushion 120, and polysilicon layer can be urged by utilizing metal
Amorphous silicon layer is formed by agent.Insulant can be deposited on the polysilicon layer, and such as
Shown in Figure 10, polysilicon layer and insulant can be patterned to form semiconductor layer 131 and grid are exhausted
Edge layer 240.Semiconductor layer 131 and gate insulation layer 240 can be formed with identical pattern.With
Metallic catalyst in crystallization can remain in semiconductor layer 131.
But, it is not limited to this according to the method manufacturing thin film transistor (TFT) 12 of this exemplary embodiment.Absolutely
Edge material can be deposited on amorphous silicon layer, and while insulant is deposited, amorphous silicon layer
Can being crystallized.In this case, metallic catalyst can move to insulant to reduce residual
Metallic catalyst in semiconductor layer 131.
As shown in Figure 11, getter metals layer can be formed above gate insulation layer 240 from buffering
Layer 120 extends.Getter metals layer can contact the side of semiconductor layer 131.Getter metals layer can be in order to
Shape is carried out with the metal with the diffusion coefficient less than the diffusion coefficient of the metallic catalyst in semiconductor layer 131
Become.
Gettering layer 235 can be formed by aoxidizing getter metals layer via heat treatment process.Inhale
Gas-bearing formation 235 can utilize has the diffusion less than the diffusion coefficient of the metallic catalyst in semiconductor layer 131
The metal-oxide of coefficient is formed.
While gettering layer 235 is formed by heat treatment process, it is included in semiconductor layer 131
The density of metallic catalyst can be reduced.At least partly may be used of metallic catalyst in semiconductor layer 131
To be eliminated.Remain in metallic catalyst in semiconductor layer 131 at least partly can be heat treated
The region of the contact getter metals layer of semiconductor layer 131 is moved to during journey.Have moved getter metals layer
Metallic catalyst can be deposited in getter metals layer, and can no longer migrate.Therefore, remain in
At least partly can being eliminated of metallic catalyst in semiconductor layer 131.
Further, gettering layer 235 can be formed with the thickness from several nm to tens nm.
As shown in Figure 12, gate electrode 151 can be formed on gettering layer 235.Gettering layer 235 can
For use as insulator, this is owing to it can utilize metal-oxide to be formed.Gettering layer 235 supply gate
Insulating barrier 240.
As shown in Figure 9, the interlayer insulating film 160 of covering grid electrode 151 can be formed.Source electrode
176 and drain electrode 177 can be formed on interlayer insulating film 160.Source electrode 176 and drain electrode 177
Can be spaced apart from each other, and semiconductor layer 131 can be contacted with 167 by contact hole 166.
By manufacture method described above, the thin film transistor (TFT) 12 according to the second exemplary embodiment can
To be produced.It is to say, the metallic catalyst being included in semiconductor layer 131 can effectively be inhaled
Gas.
Figure 13 illustrates according to the thin film transistor (TFT) 12 of exemplary embodiment after improving.
As shown in Figure 13, thin film transistor (TFT) 12 can be further at gettering layer 235 and gate electrode 151
Between include other gate insulation layer 245.Owing to gettering layer 235 can utilize the metal after oxidation to be formed,
Therefore metal by insufficient oxidation and gettering layer 235 when there is electric conductivity contingent problem can lead to
Cross the gate insulation layer 234 providing other and be prevented from.
Now with reference to Figure 14, the thin film transistor (TFT) 13 according to another exemplary embodiment is described.
As shown in Figure 14, cushion 120 can be formed on substrate 111, and by utilizing gold
The crystallized semiconductor layer of metal catalyst 131 can be formed on cushion 120.Metallic catalyst
May be used for semiconductor layer 131 crystallization, and after some metallic catalysts can remain in crystallization
Semiconductor layer 131 in.
The gettering layer 335 utilizing semiconductor layer 131 to pattern can be formed on semiconductor layer 131.Inhale
Gas-bearing formation 335 can utilize the pattern identical with semiconductor layer 131 to be formed, except explained below connects
Outside contact hole 166 and 167.Gettering layer 335 may be formed so that gettering layer 335 is not direct shape
Become on cushion 120.Gettering layer 335 can contact semiconductor layer 131.
Gettering layer 335 can utilize have less than the diffusion coefficient of the metallic catalyst in semiconductor layer 131
The metal-oxide of diffusion coefficient formed.Gettering layer 335 can eliminate and remain in semiconductor layer 131
In at least some metallic catalyst.Further, the gettering layer 335 utilizing metal-oxide to be formed is permissible
There is the thickness from several nm to tens nm, and can serve as the grid that insulator will describe with support
Insulating barrier 340.
Gate insulation layer 340 can be formed on gettering layer 335.In the present example embodiment, gate insulation
Layer 340 can be formed as covering semiconductor layer 131 and gettering layer 335 on cushion 120.
Gate electrode 151 can be formed on gate insulation layer 340.Gate electrode 151 can be configured to imbrication
The region of semiconductor layer 131.
Interlayer insulating film 160 can be formed on gate electrode 151.Interlayer insulating film 160 can be in air-breathing
Covering grid electrode 151 on layer 335.
Contact hole 166 and 167 extends through interlayer insulating film 160, gettering layer 335 and gate insulation layer 340
To expose the appropriate section of semiconductor layer 131.
Source electrode 176 and the drain electrode 177 of contact semiconductor layer 131 can pass through contact hole 166 and 167
And be formed on interlayer insulating film 160.Source electrode 176 and drain electrode 177 can be spaced apart from each other.
By configuration described above, can have by profit according to the thin film transistor (TFT) 13 of the present embodiment
With metallic catalyst at low temperatures by the semiconductor layer 131 of fast crystallization, and the metal catalytic remained
The amount of agent is the most effectively reduced.
Thin film transistor (TFT) 13 is manufactured to according to this exemplary embodiment referring now to Figure 15 and Figure 16
Method is described.
Cushion 120 can be formed on substrate 111, and metallic catalyst can be with former from 1.0e12
Son/cm2To 1.0e15 atom/cm2In the range of area density be dispersed on cushion 120.Such as,
Nickel may be used for metallic catalyst.
Amorphous silicon layer can be formed on cushion 120, and polysilicon layer can be urged by utilizing metal
Amorphous silicon layer is formed by agent.Metallic catalyst for crystallization can remain in crystallization
After polysilicon layer in.
Getter metals layer can be formed on the polysilicon layer to contact polysilicon layer.Getter metals layer can be in order to
Formed with the metal with the diffusion coefficient less than the diffusion coefficient of the metallic catalyst in polysilicon layer.
Getter metals layer can be oxidized by heat treatment process, and the metal being included in polysilicon layer
The density of catalyst can be reduced.At least part of metallic catalyst in polysilicon layer can be removed.
Remain at least part of metallic catalyst in polysilicon layer and can move to polysilicon layer due to heat treatment
Touch getter metals layer region.The metallic catalyst of getter metals layer of having moved can be deposited in suction
In gas metal level, and can no longer migrate.Therefore, remaining in the metallic catalyst in polysilicon layer can
To be absorbed.
Getter metals layer can be formed with the thickness from several nm to tens nm.Have at getter metals layer
When having the thickness of little a few nm, it may be difficult to remove metallic catalyst.On the other hand, at getter metals layer
When there is the thickness more than tens nm, thermal stress may occur during heat treatment process.
As shown in Figure 15, polysilicon layer with oxidation after getter metals layer can by together with pattern,
To form semiconductor layer 131 and gettering layer 335 by identical pattern.
As shown in Figure 16, gate insulation layer 340 can be formed on gettering layer 335.Gate insulation layer 340
Can be formed as covering semiconductor layer 131 and gettering layer 335 on cushion 120.Gate electrode 151 can
To be formed on gate insulation layer 340.
As shown in Figure 14, the interlayer insulating film 160 of covering grid electrode 151 can be formed.Source electricity
Pole 176 and drain electrode 177 can be formed on interlayer insulating film 160.Source electrode 176 and drain electrode 177
Can be spaced apart from each other, and contact semiconductor layer 131 with 167 by contact hole 166.
By manufacture method described above, according to thin film transistor (TFT) 13 quilt of this exemplary embodiment
Produce.It is to say, the metallic catalyst being included in semiconductor layer 131 can more effectively be inhaled
Remove.
Now with reference to Figure 17, another exemplary embodiment is described.
As shown in Figure 17, liquid crystal layer 300 can be included according to the display device of this exemplary embodiment,
Rather than the Organic Light Emitting Diode 70 shown in Fig. 2.In detail, display device can include connecting
To the pixel electrode 310 of drain electrode of thin film transistor (TFT) 11, the liquid crystal layer that is formed on pixel electrode 310
300, and the public electrode 320 being formed on liquid crystal layer 300.
Thin film transistor (TFT) can have and the thin film transistor (TFT) 11,12 of exemplary embodiment in accordance with the above
The configuration identical with at least one of 13.
Liquid crystal layer 300 can include various types of liquid crystal.
And, display device may further include be arranged to relative with substrate 111 in the face of substrate
211, and liquid crystal layer 300 is between which.Public electrode 320 can be formed in the face of substrate 211
On.
Display device may further include and is attached to substrate 111 and the polarization plates in the face of substrate 211
(not shown).
Further, liquid crystal layer 300 and be not limited to the configuration shown in Figure 17 in the face of substrate 211.Liquid
Crystal layer 300 and in the face of substrate 211 can have in the range of those skilled in the art are readily modified each
Plant configuration.
As summing up and looking back, for permissible with the method forming LTPS TFT to amorphous silicon film crystallization
Including solid phase crystallization method, excimer laser crystallization method and the knot utilizing metallic catalyst
Crystallization method.And, utilize the crystallization method of metal can include crystallization inducing metal (MIC)
Method, metal induced lateral crystallization (MILC) method and super grain silicon (SGS) crystallization method.
Among them, the crystallization method utilizing metallic catalyst has the advantage of fast crystallization at low temperatures.
These embodiments can be avoided owing to remaining in half in the crystallization method utilize metallic catalyst
Metallic catalyst in conductor layer and the element characteristic of thin film transistor (TFT) that causes deteriorates.Therefore, at amorphous
When silicon layer is by utilizing being crystallized of metallic catalyst, it is desirable to for eliminating effective absorption of metallic catalyst
Process.
These embodiments can provide the gold remained in the semiconductor layer after crystallization with reduction amount
The thin film transistor (TFT) of metal catalyst.
Described embodiment can provide the metallic catalyst that wherein remains in the semiconductor layer can be by
The method for fabricating thin film transistor effectively absorbed.
Although present disclosure is retouched already in connection with the exemplary embodiment being presently considered to put into practice
State, it should be appreciated that, the present invention is not limited to the disclosed embodiments, but on the contrary, is intended to contain
Cover various amendments included in the spirit and scope of the appended claims and equivalent arrangements.
Claims (30)
1. a thin film transistor (TFT), including:
Substrate；
Semiconductor layer, is provided on the substrate and by utilizing being crystallized of metallic catalyst；
Gate electrode, insulate with described semiconductor layer and is arranged on described semiconductor layer；
Gettering layer, is arranged between described semiconductor layer and described gate electrode, and utilization has ratio described half
The metal-oxide of the diffusion coefficient that the diffusion coefficient of the metallic catalyst in conductor layer is little is formed；
Gate insulation layer, is arranged between described gettering layer and described semiconductor layer；And
Multiple contact holes, extend through described gettering layer and described gate insulation layer to expose the phase of described semiconductor layer
Should part；
Wherein said gettering layer covers whole described semiconductor layers part in addition to described contact hole.
Thin film transistor (TFT) the most according to claim 1, wherein
The 1/100 of the diffusion coefficient of the described gettering layer diffusion coefficient more than 0 and less than described metallic catalyst.
Thin film transistor (TFT) the most according to claim 1, farther includes:
It is arranged on the cushion between described substrate and described semiconductor layer, wherein
Described metallic catalyst is with from 1.0e12 atom/cm2To 1.0e15 atom/cm2In the range of area density
Disperse between described cushion and described semiconductor layer.
Thin film transistor (TFT) the most according to claim 1, wherein
Described metallic catalyst is with from 1.0e12 atom/cm2To 1.0e15 atom/cm2In the range of area density
Described semiconductor layer disperses.
Thin film transistor (TFT) the most according to claim 1, wherein
Described metallic catalyst includes nickel (Ni), palladium (Pd), titanium (Ti), silver (Ag), gold (Au), stannum
(Sn), antimony (Sb), copper (Cu), cobalt (Co), molybdenum (Mo), terbium (Tb), ruthenium (Ru), cadmium (Cd)
At least one of platinum (Pt).
Thin film transistor (TFT) the most according to claim 1, wherein
Described metal-oxide by scandium (Sc), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb),
Tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), manganese (Mn), rhenium (Re), ruthenium (Ru), osmium (Os),
Cobalt (Co), rhodium (Rh), iridium (Ir), platinum (Pt), yttrium (Y), lanthanum (La), germanium (Ge), praseodymium (Pr),
Neodymium (Nd), dysprosium (Dy), holmium (Ho), aluminum (Al), titanium nitride (TiN) and tantalum nitride (TaN),
Formed at least one of its alloy or its silicide.
Thin film transistor (TFT) the most according to claim 1, farther includes:
Cover the interlayer insulating film of described gate electrode, the source electrode being formed on described interlayer insulating film and formation
On described interlayer insulating film and the drain electrode spaced apart with described source electrode.
Thin film transistor (TFT) the most according to claim 7, wherein
The plurality of contact hole extends through described interlayer insulating film, and described source electrode and described drain electrode lead to
Cross corresponding contact hole and contact the described appropriate section of described semiconductor layer.
Thin film transistor (TFT) the most according to claim 1, wherein:
Described gate insulation layer utilizes described semiconductor layer to be patterned, and
Wherein said gettering layer contacts the side of described semiconductor layer.
10. a thin film transistor (TFT), including:
Substrate；
Semiconductor layer, is provided on the substrate and by utilizing being crystallized of metallic catalyst；
Gate electrode, insulate with described semiconductor layer and is arranged on described semiconductor layer；
Gettering layer, is arranged between described semiconductor layer and described gate electrode, and utilization has ratio described half
The metal-oxide of the diffusion coefficient that the diffusion coefficient of the metallic catalyst in conductor layer is little is formed；And
Gate insulation layer, is arranged between described gettering layer and described gate electrode, and
Wherein said gettering layer contacts described semiconductor layer, and described gettering layer and described semiconductor layer are except connecing
There is outside contact hole identical pattern.
11. 1 kinds of methods manufacturing thin film transistor (TFT), including:
Substrate is provided；
Form amorphous silicon layer on the substrate；
By utilizing metallic catalyst that described amorphous silicon layer is formed polysilicon layer；
Semiconductor layer is formed by described polysilicon layer is carried out patterning；
Described semiconductor layer is formed gate insulation layer；
Described gate insulation layer is formed multiple suction hole；
Described gate insulation layer forms getter metals layer, to contact described quasiconductor by the plurality of suction hole
Layer also covers whole described semiconductor layers；And
While described getter metals layer being aoxidized by heat treatment process, form gettering layer, and reduce
The density of the metallic catalyst being included in described semiconductor layer.
The method of 12. manufacture thin film transistor (TFT)s according to claim 11, farther includes:
Described gettering layer forms gate electrode so that the region of semiconductor layer described in imbrication；
Form the interlayer insulating film covering described gate electrode；
Form multiple contact hole to penetrate described interlayer insulating film, described gettering layer and described gate insulation layer and to expose
The source part of described semiconductor layer and leakage part；And
Described interlayer insulating film forms source electrode and drain electrode, with by the plurality of contact hole connects accordingly
Contact hole contacts described semiconductor layer.
The method of 13. manufacture thin film transistor (TFT)s according to claim 12, wherein
The plurality of the plurality of suction hole of contact hole imbrication.
The method of 14. manufacture thin film transistor (TFT)s according to claim 13, wherein
When forming the plurality of contact hole, eliminate the described by the contact of the plurality of suction hole of described gettering layer
The part of semiconductor layer.
The method of 15. manufacture thin film transistor (TFT)s according to claim 11, wherein
Described gettering layer utilizes has the diffusion less than the diffusion coefficient of the metallic catalyst in described semiconductor layer
The metal-oxide of coefficient is formed.
The method of 16. manufacture thin film transistor (TFT)s according to claim 15, wherein
The 1/100 of the diffusion coefficient of the described gettering layer diffusion coefficient more than 0 and less than described metallic catalyst.
The method of 17. manufacture thin film transistor (TFT)s according to claim 15, farther includes:
Cushion is formed, wherein between described substrate and described amorphous silicon layer
Described metallic catalyst is with from 1.0e12 atom/cm2To 1.0e15 atom/cm2In the range of area density
Disperse between described cushion and described amorphous silicon layer.
The method of 18. manufacture thin film transistor (TFT)s according to claim 15, wherein
Described metallic catalyst is with from 1.0e12 atom/cm2To 1.0e15 atom/cm2In the range of area density
Described amorphous silicon layer disperses.
The method of 19. manufacture thin film transistor (TFT)s according to claim 15, wherein
Described metallic catalyst includes nickel (Ni), palladium (Pd), titanium (Ti), silver (Ag), gold (Au), stannum
(Sn), antimony (Sb), copper (Cu), cobalt (Co), molybdenum (Mo), terbium (Tb), ruthenium (Ru), cadmium (Cd)
At least one of platinum (Pt).
The method of 20. manufacture thin film transistor (TFT)s according to claim 15, wherein
Described metal-oxide by scandium (Sc), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb),
Tantalum (Ta), chromium (Cr), molybdenum (Mo), tungsten (W), manganese (Mn), rhenium (Re), ruthenium (Ru), osmium (Os),
Cobalt (Co), rhodium (Rh), iridium (Ir), platinum (Pt), yttrium (Y), lanthanum (La), germanium (Ge), praseodymium (Pr),
Neodymium (Nd), dysprosium (Dy), holmium (Ho), aluminum (Al), titanium nitride (TiN) and tantalum nitride (TaN),
Formed at least one of its alloy or its silicide.
The method of 21. manufacture thin film transistor (TFT)s according to claim 15, wherein
Described heat treatment process is performing at a temperature of 400 to 993 degrees Celsius.
22. 1 kinds of methods manufacturing thin film transistor (TFT), including:
Substrate is provided；
Form amorphous silicon layer on the substrate；
By utilizing metallic catalyst that described amorphous silicon layer is formed polysilicon layer；
Described polysilicon layer coats insulant；
By described polysilicon layer and described insulant are patterned, form semiconductor layer with identical patterns
And gate insulation layer；
Described gate insulation layer forms getter metals layer to contact the side of described semiconductor layer and to cover all
Described semiconductor layer；And
By heat treatment process, described getter metals layer is carried out oxidation and form gettering layer, and minimizing is included in
The density of the metallic catalyst in described semiconductor layer.
23. 1 kinds of methods manufacturing thin film transistor (TFT), including:
Substrate is provided；
Form amorphous silicon layer on the substrate；
By utilizing metallic catalyst that described amorphous silicon layer is formed polysilicon layer, described polysilicon layer
Metallic catalyst including residual volume；
Described polysilicon layer forms getter metals layer to cover whole described polysilicon layers；
By heat treatment process, described getter metals layer is aoxidized, and reduction is included in described polysilicon layer
In the density of metallic catalyst；
By the getter metals layer after described polysilicon layer and described oxidation is patterned, with identical patterns shape
Become semiconductor layer and gettering layer；And
Described gettering layer is formed gate insulation layer.
24. 1 kinds of display devices, including:
Substrate；
Semiconductor layer, it is provided that on the substrate and by utilizing being crystallized of metallic catalyst；
Gate electrode, insulate with described semiconductor layer and is arranged on described semiconductor layer；
Gettering layer, is arranged between described semiconductor layer and described gate electrode, and utilization has ratio described half
The metal-oxide of the diffusion coefficient that the diffusion coefficient of the metallic catalyst in conductor layer is little is formed；
Gate insulation layer, is arranged between described gettering layer and described semiconductor layer；
Multiple contact holes, extend through described gettering layer and described gate insulation layer to expose the phase of described semiconductor layer
Should part；Source electrode, contacts the source region of described semiconductor layer and spaced apart with described gate electrode；And
Drain electrode, contacts the drain region of described semiconductor layer and spaced apart with described gate electrode and described source electrode；
Wherein said source electrode and described drain electrode contact the described phase of described semiconductor layer by corresponding contact hole
Should part, and
Wherein said gettering layer covers whole described semiconductor layers part in addition to described contact hole.
25., according to display device described in claim 24, farther include:
Covering the interlayer insulating film of described gate electrode, wherein said source electrode is formed on described interlayer insulating film,
And described drain electrode is formed on described interlayer insulating film and spaced apart with described source electrode.
26. display devices according to claim 25, wherein
Multiple contact holes extend through described interlayer insulating film and described gettering layer to expose described semiconductor layer
Part, and
Described source electrode and described drain electrode contact the described part of described semiconductor layer by corresponding contact hole.
27. display devices according to claim 24, wherein:
In addition to contact hole, described gate insulation layer is patterned with the pattern identical with described semiconductor layer,
Wherein said gettering layer contacts the side of described semiconductor layer.
28. 1 kinds of display devices, including:
Substrate；
Semiconductor layer, it is provided that on the substrate and by utilizing being crystallized of metallic catalyst；
Gate electrode, insulate with described semiconductor layer and is arranged on described semiconductor layer；
Gettering layer, is arranged between described semiconductor layer and described gate electrode, and utilization has ratio described half
The metal-oxide of the diffusion coefficient that the diffusion coefficient of the metallic catalyst in conductor layer is little is formed；
Gate insulation layer, is arranged between described gettering layer and described gate electrode；
Multiple contact holes, extend through described gettering layer and described gate insulation layer to expose the phase of described semiconductor layer
Should part；
Source electrode, contacts the source region of described semiconductor layer and spaced apart with described gate electrode；And
Drain electrode, contacts the drain region of described semiconductor layer and spaced apart with described gate electrode and described source electrode；
Wherein said gettering layer contacts described semiconductor layer, and described gettering layer and described semiconductor layer are except connecing
There is outside contact hole identical pattern, and
Wherein said source electrode and described drain electrode contact the described phase of described semiconductor layer by corresponding contact hole
Should part.
29. display devices according to claim 24, farther include:
It is connected to the Organic Light Emitting Diode of described drain electrode.
30. display devices according to claim 24, farther include:
It is connected to the pixel electrode of described drain electrode, the liquid crystal layer being formed on described pixel electrode and is formed at
Public electrode on described liquid crystal layer.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020100086577A KR101733196B1 (en) | 2010-09-03 | 2010-09-03 | Thin film transistor and method for manufacturing the same and display divce using the same |
| KR10-2010-0086577 | 2010-09-03 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102386235A CN102386235A (en) | 2012-03-21 |
| CN102386235B true CN102386235B (en) | 2016-12-14 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5985740A (en) * | 1996-01-19 | 1999-11-16 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device including reduction of a catalyst |
| CN101315883A (en) * | 2007-05-31 | 2008-12-03 | 三星Sdi株式会社 | Method of fabricating polycrystalline silicon layer, TFT fabricated using the same, method of fabricating TFT, and organic light emitting diode display device having the same |
| CN101373793A (en) * | 2007-08-23 | 2009-02-25 | 三星Sdi株式会社 | Thin film transistor, method of fabricating the same, and organic light emitting diode display device |
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5985740A (en) * | 1996-01-19 | 1999-11-16 | Semiconductor Energy Laboratory Co., Ltd. | Method of manufacturing a semiconductor device including reduction of a catalyst |
| CN101315883A (en) * | 2007-05-31 | 2008-12-03 | 三星Sdi株式会社 | Method of fabricating polycrystalline silicon layer, TFT fabricated using the same, method of fabricating TFT, and organic light emitting diode display device having the same |
| CN101373793A (en) * | 2007-08-23 | 2009-02-25 | 三星Sdi株式会社 | Thin film transistor, method of fabricating the same, and organic light emitting diode display device |
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