CN102378431B - Driving circuit of light-emitting diode, decoding circuit and decoding method - Google Patents
Driving circuit of light-emitting diode, decoding circuit and decoding method Download PDFInfo
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- CN102378431B CN102378431B CN201010253384.XA CN201010253384A CN102378431B CN 102378431 B CN102378431 B CN 102378431B CN 201010253384 A CN201010253384 A CN 201010253384A CN 102378431 B CN102378431 B CN 102378431B
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Abstract
The invention provides a driving circuit of a light-emitting diode (LED), a decoding circuit and a decoding method. The decoding circuit comprises an oscillator and a decoder, wherein the decoder comprises a frequency judgment unit and a decoding unit, the frequency judgment unit receives a clock pulse signal and a data signal corresponding to a DMX512 protocol, samples one time slot of the data signal according to the clock pulse signal so as to generate a sampling number corresponding to the time slot cycle, and then outputs a reference signal corresponding to the frequency of the clock pulse signal according to the sampling number; the decoding unit samples the data signal according to the clock pulse signal and the reference signal so as to decode data carried by the data signal. The decoding circuit provided by the invention can accurately sample the data signal without an external frequency adjusting element for adjusting the frequency of the oscillator.
Description
Technical field
The present invention relates to the decoding circuit of a kind of DMX512, and be particularly related to a kind of drive circuit, decoding circuit and its coding/decoding method of light-emitting diode.
Background technology
DMX512 is a kind of standard of Interface for digital communication, is mainly used in the communication protocol between light units, and its content comprises the data format of transfer of data, the electrical characteristic of equipment and connector type.DMX512 agreement at first Shi You U.S. theater technological associations (Engineering Commission of United States Institute for Theatre Technology, USITT) develops formulation.Before DMX512 agreement is worked out, just have a lot of light control protocols to be applied on light units, but along with system is more and more complicated, the mutual capacitive demand between different product is just more and more high, DMX512 be in this case in response to and give birth to.
DMX512 data are to adopt asynchronous serial data transmission mode (asynchronous serial format) to transmit, each data packet comprises an initial code (START CODE) and maximum 512 channel datas, wherein the 1st time slot (slot 0) is used for transmitting initial code, and the 2nd time slot (slot 1) thereafter to the 512nd time slot (slot 512) is for Transfer pipe data.
The world, domestic Computer lamp generally adopt DMX512 data format Draw up Procedure Files at present.The speed of DMX512 data flow is 250K, 4 microseconds (us) that each bit is full-length, and the bit length that meets agreement is between 3.92us～4.08us.DMX512 data-signal is the host-host protocol that utilizes the high electronegative potential of Perfect Time width to combine, and therefore need to sample accurately reference frequency just can be correctly decoded 8 bit data in DMX512 data-signal.But the variation that general chip is limited to technique and design cost also cannot directly directly arrange accurately oscillator to meet the requirement of DMX512 decoder in chip.So in known technology, DMX512 decoder need to configure that external element (as electric capacity) is adjusted the frequency of oscillation of internal clock pulse signal or directly external oscillator accurately solves this problem conventionally.But such design not only designs comparatively complicated, and cost is also higher.
Summary of the invention
The invention provides a kind of decoding circuit and drive circuit, it has the inner function that detects clock pulse signal frequency, can according to the frequency of clock pulse signal, adjust sampling frequency with decoding DMX512 data-signal voluntarily.
The invention provides a kind of coding/decoding method, utilize DMX512 data-signal to carry out the frequency of the clock pulse signal of estimation chip inside, and then according to the correct sampling reference frequency DMX512 data-signal of decoding.
The present invention proposes a kind of decoding circuit, comprises an oscillator and a decoder, and decoder comprises a frequency judging unit and a decoding unit.Oscillator is exported a clock pulse signal, decoder is coupled to oscillator receive clock pulse signal and a data-signal, data-signal comprises a plurality of time slots, described in each, time slot has a time slot cycle, wherein decoder samples one of described a plurality of time slots to produce corresponding to a number of samples in time slot cycle and according to the frequency of number of samples calculating clock pulse signal, then according to the data of the frequency decoding data signal institute appendix of clock pulse signal according to clock pulse signal.
Wherein, frequency judging unit is coupled to oscillator receive clock pulse signal and data-signal, and frequency judging unit samples one of described a plurality of time slots to produce corresponding to this number of samples in this time slot cycle and to export the reference signal corresponding to the frequency of clock pulse signal according to number of samples according to clock pulse signal.Decoding unit is coupled to frequency judging unit and this oscillator, and decoding unit is the data with decoding data signal institute appendix according to clock pulse signal and reference signal sampled data signal.
In an embodiment of the present invention, the corresponding DMX512 agreement of the form of above-mentioned data-signal, one first time slot in the described a plurality of time slots of frequency judging unit sampling is to produce number of samples.Wherein the first time slot has an initial code (start code) or a code presupposition.
In an embodiment of the present invention, said frequencies judging unit according at least one bit in one first time slot in the described a plurality of time slots of clock pulse signal sampling to produce above-mentioned number of samples.
The another drive circuit that proposes a kind of light-emitting diode of the present invention, comprises above-mentioned decoding circuit and driver element, and wherein driver element is coupled to decoding circuit, exports a light-emitting diode drive signal according to the data of data-signal institute appendix.
The present invention proposes again a kind of coding/decoding method be applicable to decode data-signal of corresponding DMX512 agreement, first this coding/decoding method comprises the following steps:, receive a clock pulse signal and a data-signal, this data-signal comprises a plurality of time slots, and described in each, time slot has a time slot cycle; Then, according to this clock pulse signal, sample one of described a plurality of time slots to produce the number of samples corresponding to this time slot cycle; A reference signal according to this number of samples output corresponding to the frequency of this clock pulse signal; And sample this data-signal with the data of this data-signal institute appendix of decoding according to this clock pulse signal and this reference signal.All the other implementation details of this coding/decoding method please refer to the explanation of above-mentioned decoding circuit, at this, do not add tired stating.
Comprehensively above-mentioned, decoding circuit proposed by the invention, drive circuit and its coding/decoding method have the function of the frequency that detects voluntarily internal oscillator, can adjust voluntarily sampling rate correctly to sample the data-signal of DMX512 according to different frequencies of oscillation.By framework of the present invention, decoding circuit and drive circuit do not need additionally to arrange external frequency adjustment element, decoding circuit and drive circuit can sample with the clock pulse signal of different frequency, can overcome whereby oscillator because of technique or design bad caused frequency drift problem.
For above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and coordinate accompanying drawing, be described in detail below.
Accompanying drawing explanation
Fig. 1 is the frequence estimation mode schematic diagram according to the clock pulse signal of first embodiment of the invention.
Fig. 2 is the drive circuit figure according to the light-emitting diode of first embodiment of the invention.
Fig. 3 is the coding/decoding method flow chart according to second embodiment of the invention.
Description of reference numerals in above-mentioned accompanying drawing is as follows:
119: the interchannel time
200: drive circuit
210: transducer
220: decoding circuit
221: decoder
222: frequency judging unit
224: oscillator
226: decoding unit
230: driver element
B1～B11: 1st～11 bits
BREAK: interrupt
MAB: in have no progeny the time
MBB: time before interrupting
DMXIN: data-signal
CLK: clock pulse signal
DMXIN: data-signal
RES: reference signal
DD: driving data
0: the 1 time slot of slot
S310～S340: step
Embodiment
(the first embodiment)
Fig. 1 is the frequence estimation mode schematic diagram according to the clock pulse signal of first embodiment of the invention.The data format of DMX512 signal comprise interruption " BREAK ", in have no progeny the time " Mark time after BREAK; MAB ", initial code (start code, be arranged in the 1st time slot slot 0), channel data (is positioned at the 2nd time slot slot 1 to the 513rd time slot slot 512, the 2nd time slot slot 1 is after the 513rd time slot slot 512 is positioned at the 1st time slot slot 0, Fig. 1 is not shown), the interchannel time 11 (Mark time between slots) with interrupt before the time " Mark time before BREAK, MBB ".BREAK is the beginning of DMX512 data packet, is the electronegative potential output of 88 microseconds; After MAB is positioned at BREAK, be the high potential output of 8 microseconds or the pulse of 24 microseconds.Initial code (start code is called for short SC) is the data that data flow starts, and has the form identical with channel data, generally includes 11 bits or 44 microseconds.In the agreement of DMX512, the full-length of each bit of channel data is 4 microseconds, and the critical field of protocol requirement is between 3.92 microsecond to 4.08 microseconds.
As above-mentioned, the time slot cycle of each time slot (slot 0～slot 512) is 44 microseconds, comprises 11 bits, and its data format is identical.The 1st time slot slot 0 of take is example, and its 1st bit B1 is initial bit (start bit), is electronegative potential; 2nd～9 bit B2～B9 are data bit element (data bits), and 10th～11 bit B10, B11, for finishing bit (stop bits), are high potential.The form of 2nd～513 time slot slot 1～slot 512 is identical with the 1st time slot slot 0, at this, is not repeated.The interchannel time 119 that is spaced apart between time slot and time slot (Mark time between slots), between 0～1 second; The time span of MAB is between between 8 microseconds to 1 second; The time span of MBB is between 0～1 second.All the other specifications in Fig. 1 please refer to the agreement of DMX512, at this, do not add tired stating.
Known in above-mentioned specification, in the data packet of DMX512, only have the time slot cycle to fix, remaining cycle changes larger.Therefore, the time slot cycle can be used for oppositely reasoning out the frequency of sampled signal (being the clock pulse signal in chip internal oscillator).Please refer to Fig. 1, wherein clock pulse signal 1～clock pulse signal 3 has different sampling frequencies, while sampling with 1st～2 bit B1, B2 in 1 couple of the 1st time slot slot 0 of clock pulse signal, two bit cycle (8 microseconds, i.e. 2/11 time slot cycle) in, its number of samples is 8, namely 8 pulses.The frequency that can estimate whereby clock pulse signal 1 is about 500KHz.Same mode also can be used for estimating the frequency of clock pulse signal 2,3, and during with clock pulse signal 2 samplings 1st～2 bit B1, B2, the number of samples that corresponds to is 6, and its frequency estimating is about 300KHz.During with clock pulse signal 3 samplings 1st～2 bit B1, B2, the number of samples that corresponds to is 10, and its frequency estimating is about 625KHz.
From the above, as long as utilize the mode of oppositely calculating just can utilize fixing characteristic estimation of time slot cycle to go out the frequency of the clock pulse signal using at present, then utilize estimation result to sample and decoding follow-up time slot.It should be noted that, in order to allow system can correctly obtain the interval of 1st～2 bit B1, B2, the 3rd bit B3 can be set as to high potential, such 1st～2 bit B1, B2 will form continuous electronegative potential output, and system can more easily be judged between the location of 1～2 bit B1, B2.In practical application, designer can set required waveform in the 1st time slot slot 0, set required data form or code presupposition, 00000000 data for example, the length that such waveform can be used whole time slot is the frequency with judgement clock pulse signal 1～3 as sampling range.
In addition, also can use any bit in the 1st time slot slot 0 to be used as sampling standard to calculate the frequency of clock pulse signal 1～3, or use arbitrary time slot slot 1～slot 512 to be used as sampling standard to calculate the frequency of clock pulse signal 1～3.Because the cycle of each bit is fixed, as long as therefore know sampled siding-to-siding block length, just can oppositely know the frequency of adopted clock pulse signal by inference.After the explanation via above-described embodiment, the art those of ordinary skill should be known other execution modes by inference, at this, does not add tired stating.
After the frequency of clock pulse signal that obtains chip internal, the sampling frequency that system can be decided required use in its sole discretion why, as shown in the sampling clock pulse in Fig. 1, as long as its sampling point is can obtain correct data in the middle of being positioned at cycle of each bit.Aforesaid way can directly be applied on the drive circuit of DMX512 decoding circuit and light-emitting diode, please refer to Fig. 2, and Fig. 2 is the drive circuit figure according to the light-emitting diode of first embodiment of the invention.Drive circuit 200 mainly comprises decoding circuit 220 and driver element 230, and decoding circuit 220 comprises decoder 221 and oscillator 224.Decoder 221 comprises frequency judging unit 222 and decoding unit 226.Decoder 221 is coupled to oscillator 224 receive clock pulse signal CLK and data-signal DMXIN.Decoder 221 can reach the time slot in sample data-signal DMXIN with clock pulse signal CLK, and utilizes the frequency of number of samples and known time slot computation of Period clock pulse signal CLK.And then according to the frequency information of clock pulse signal CLK, with clock pulse signal CLK, go the data of institute's appendix in all the other time slots of decoding data signal DMXIN.
The circuit structure of decoding circuit 220 and action further illustrate as follows, frequency judging unit 222, oscillator 224 and decoding unit 226.Decoding unit 226 is coupled between frequency judging unit 222 and driver element 230, and oscillator 224 is coupled to frequency judging unit 222 and decoding unit 226.Transducer 210 is coupled to frequency judging unit 222, is used for receiving outside differential wave, and is converted into the data-signal DMXIN that meets DMX512 agreement.Transducer 210 is for example RS485 transducer.
The use that oscillator 224 output clock pulse signal CLK are usingd as sample of signal to frequency judging unit 222 and decoding unit 226.Frequency judging unit 222 receives data-signal DMXIN, and according to one of the time slot in clock pulse signal CLK sampled data signal DMXIN (for example slot 0) with produce corresponding to a number of samples in time slot cycle and according to this number of samples output the reference signal RES corresponding to the frequency of clock pulse signal CLK.The mode of the frequency of frequency judging unit 222 estimation clock pulse signal CLK, as the explanation of above-mentioned Fig. 1, does not add tired stating at this.
After estimating the frequency of clock pulse signal CLK, decoding unit 226 is the driving data DD with decoding data signal DMXIN institute appendix according to clock pulse signal CLK and reference signal RES sampled data signal DMXIN, then driving data DD is exported to driver element 230 to drive light-emitting diode (not shown).Decoding unit 226 can determine that suitable sampling rate is with sampled data signal DMXIN according to the frequency of clock pulse signal CLK.By such circuit framework, drive circuit 200 can move adaptive adjustment to overcome oscillator 224 because of technique or to design the bad frequency drift problem that caused certainly according to the frequency of oscillator 224.So the discrete elements that utilizes the DMX512 of the framework of drive circuit 200 to drive chip or decoding chip not to need impressed frequency to adjust, as electric capacity, adjusts the frequency of internal oscillator 224.Drive circuit 200 and the decoding circuit 220 of the present embodiment not only can be simplified circuit framework and can improve the stability of system.In addition, it should be noted that above-mentioned decoding circuit 220 can be incorporated in identical chip with driver element 230.
In addition, in another embodiment of the present invention, frequency judging unit 222 can directly produce sampling clock pulse as shown in Figure 1 to decoding unit 226, decoding unit 226 can directly with sampling clock pulse, to data-signal DMXIN, be sampled and the data of its appendix of decoding.Certainly, decoder 221 also can directly produce sampling clock pulse according to the frequency information of obtained clock pulse signal CLK.Circuit framework in Fig. 2 is only one embodiment of the invention, and circuit framework of the present invention is not limited to this.
In addition, it should be noted that the drive circuit 200 of the present embodiment goes for the data-signal of various DMX512 agreements, for example the DMX512 agreement of standard and the DMX512 agreement of 2 speeds or the DMX512 agreement of 4 speeds.The DMX512 agreement of so-called 2 speeds refers to 1/2 of DMX512 agreement that the standard time shorten of its signal format is standard, can within the identical time, transmit the data volume of 2 times like this.In like manner, the DMX512 agreement of 4 speeds be the DMX512 agreement that is standard by standard time shorten 1/4 to improve volume of transmitted data.Because the time slot in various DMX512 agreements all has the fixing time slot cycle, this time slot cycle just can be used for the anti-frequency that pushes away clock pulse signal CLK.After the explanation via above-described embodiment, the art those of ordinary skill should be known all the other implementation details of this coding/decoding method by inference, at this, does not add tired stating.
(the second embodiment)
From another perspective, above-mentioned Fig. 1, Fig. 2 embodiment can summarize a kind of coding/decoding method, please refer to Fig. 3, and Fig. 3 is the coding/decoding method flow chart according to second embodiment of the invention.This coding/decoding method be applicable to decode data-signal of corresponding DMX512 agreement, first this coding/decoding method comprises the following steps:, receives a clock pulse signal and a data-signal, and data-signal comprises a plurality of time slots, described in each, time slot has a time slot cycle, as shown in Figure 1 (step S310).Then, according to clock pulse signal, sample one of described a plurality of time slots to produce the number of samples (step S320) corresponding to the time slot cycle.Next, the reference signal (step S330) corresponding to the frequency of clock pulse signal according to number of samples output.Then, the data (step S340) with decoding data signal institute appendix according to clock pulse signal and reference signal sampled data signal.After the explanation via above-described embodiment, the art those of ordinary skill should be known all the other implementation details of this coding/decoding method by inference, at this, does not add tired stating.
In sum, the present invention utilizes the characteristics of signals of DMX512, estimates that the frequency of internal oscillator is to determine suitable sampling frequency with its time slot cycle.Such circuit framework and coding/decoding method can overcome the problem of oscillator drift, and the outside of drive circuit does not need to arrange frequency adjustment element also can correctly sample the data-signal of DMX512.The present invention has advantages of the stability of simplifying circuit framework and improving system.
Although preferred embodiment of the present invention has disclosed as above; yet the present invention is not limited to above-described embodiment; those of ordinary skill in technical field under any; within not departing from disclosed scope; when doing a little change and adjustment, so protection scope of the present invention should be as the criterion with the appended scope that claim was defined.
Claims (18)
1. a decoding circuit, is characterized in that this decoding circuit comprises:
One oscillator, output one clock pulse signal; And
One decoder, be coupled to this oscillator and receive this clock pulse signal and a data-signal, this data-signal comprises a plurality of time slots, described in each, time slot has fixing time slot cycle, wherein this decoder according to one of described a plurality of time slots of this clock pulse signal sampling with produce corresponding to this fixedly the time slot cycle a number of samples and according to this number of samples, calculate the frequency of this clock pulse signal, and according to the decode data of this data-signal institute appendix of the frequency of this clock pulse signal.
2. decoding circuit as claimed in claim 1, is characterized in that this decoder comprises:
One frequency judging unit, be coupled to this oscillator and receive this clock pulse signal and this data-signal, this frequency judging unit according to one of described a plurality of time slots of this clock pulse signal sampling with produce corresponding to this fixedly the time slot cycle this number of samples and according to this number of samples output the reference signal corresponding to the frequency of this clock pulse signal; And
One decoding unit, is coupled to this frequency judging unit and this oscillator, and this decoding unit samples this data-signal with the data of this data-signal institute appendix of decoding according to this clock pulse signal and this reference signal.
3. decoding circuit as claimed in claim 1, is characterized in that the corresponding DMX512 agreement of form of this data-signal, and one first time slot in the described a plurality of time slots of this frequency judging unit sampling is to produce this number of samples.
4. decoding circuit as claimed in claim 3, is characterized in that this first time slot has an initial code.
5. decoding circuit as claimed in claim 2, it is characterized in that this frequency judging unit according at least one bit in one first time slot in the described a plurality of time slots of this clock pulse signal sampling to produce this number of samples.
6. decoding circuit as claimed in claim 5, is characterized in that this first time slot has a code presupposition.
7. decoding circuit as claimed in claim 2, is characterized in that this oscillator, this frequency judging unit and this decoding unit are integrated in same chip.
8. a drive circuit for light-emitting diode, is characterized in that this drive circuit comprises:
One decoding circuit, comprising:
One oscillator, output one clock pulse signal; And
One decoder, be coupled to this oscillator and receive this clock pulse signal and a data-signal, this data-signal comprises a plurality of time slots, described in each, time slot has fixing time slot cycle, wherein this decoder according to one of described a plurality of time slots of this clock pulse signal sampling with produce corresponding to this fixedly the time slot cycle a number of samples and according to this number of samples, calculate the frequency of this clock pulse signal, and according to the decode data of this data-signal institute appendix of the frequency of this clock pulse signal; And
One driver element, is coupled to this decoding circuit, exports a light-emitting diode drive signal according to the data of this data-signal institute appendix.
9. the drive circuit of light-emitting diode as claimed in claim 8, is characterized in that this decoder comprises:
One frequency judging unit, be coupled to this oscillator and receive this clock pulse signal and this data-signal, this frequency judging unit according to one of described a plurality of time slots of this clock pulse signal sampling with produce corresponding to this fixedly the time slot cycle this number of samples and according to this number of samples output the reference signal corresponding to the frequency of this clock pulse signal; And
One decoding unit, is coupled to this frequency judging unit and this oscillator, and this decoding unit samples this data-signal with the data of this data-signal institute appendix of decoding according to this clock pulse signal and this reference signal.
10. the drive circuit of light-emitting diode as claimed in claim 8, is characterized in that the corresponding DMX512 agreement of form of this data-signal, and one first time slot in the described a plurality of time slots of this frequency judging unit sampling is to produce this number of samples.
The drive circuit of 11. light-emitting diodes as claimed in claim 10, is characterized in that this first time slot has an initial code.
The drive circuit of 12. light-emitting diodes as claimed in claim 9, it is characterized in that this frequency judging unit according at least one bit in one first time slot in the described a plurality of time slots of this clock pulse signal sampling to produce this number of samples.
The drive circuit of 13. light-emitting diodes as claimed in claim 12, is characterized in that this first time slot has a code presupposition.
The drive circuit of 14. light-emitting diodes as claimed in claim 9, is characterized in that this oscillator, this frequency judging unit, this decoding unit and this driver element are integrated in same chip.
15. 1 kinds of coding/decoding methods, a data-signal of the corresponding DMX512 agreement that is applicable to decode, is characterized in that this coding/decoding method comprises:
Receive a clock pulse signal and a data-signal, this data-signal comprises a plurality of time slots, and described in each, time slot has fixing time slot cycle;
According to one of described a plurality of time slots of this clock pulse signal sampling to produce corresponding to this fixing number of samples in time slot cycle;
A reference signal according to this number of samples output corresponding to the frequency of this clock pulse signal; And
According to this clock pulse signal and this reference signal, sample this data-signal with the data of this data-signal institute appendix of decoding.
16. coding/decoding methods as claimed in claim 15, is characterized in that the form of this data-signal meets DMX512 agreement.
17. coding/decoding methods as claimed in claim 15, is characterized in that fixedly also comprising that one first time slot in the described a plurality of time slots of sampling is to produce this number of samples in the step of this number of samples in time slot cycle producing corresponding to this, this first time slot has an initial code.
18. coding/decoding methods as claimed in claim 15, is characterized in that fixedly also comprising that one first time slot in the described a plurality of time slots of sampling is to produce this number of samples in the step of this number of samples in time slot cycle producing corresponding to this, this first time slot has a code presupposition.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US20020019952A1 (en) * | 2000-08-09 | 2002-02-14 | Fujitsu Limited | Method of determining data transfer speed in data transfer apparatus |
| US20020047628A1 (en) * | 1997-08-26 | 2002-04-25 | Frederick Morgan | Methods and apparatus for controlling devices in a networked lighting system |
| US7598684B2 (en) * | 2001-05-30 | 2009-10-06 | Philips Solid-State Lighting Solutions, Inc. | Methods and apparatus for controlling devices in a networked lighting system |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020047628A1 (en) * | 1997-08-26 | 2002-04-25 | Frederick Morgan | Methods and apparatus for controlling devices in a networked lighting system |
| US20020019952A1 (en) * | 2000-08-09 | 2002-02-14 | Fujitsu Limited | Method of determining data transfer speed in data transfer apparatus |
| US7598684B2 (en) * | 2001-05-30 | 2009-10-06 | Philips Solid-State Lighting Solutions, Inc. | Methods and apparatus for controlling devices in a networked lighting system |
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