CN102376631B - Method for producing dual damascene structure - Google Patents
Method for producing dual damascene structure Download PDFInfo
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- CN102376631B CN102376631B CN 201010262784 CN201010262784A CN102376631B CN 102376631 B CN102376631 B CN 102376631B CN 201010262784 CN201010262784 CN 201010262784 CN 201010262784 A CN201010262784 A CN 201010262784A CN 102376631 B CN102376631 B CN 102376631B
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Abstract
The invention discloses a method for producing a dual damascene structure. The method comprises the following steps of: depositing a part of silicon-containing coating in a through hole; then depositing a bottom antireflective coating; carrying out interconnected groove etching; and when the silicon-containing coating is exposed, introducing CF4, N2 and Ar and continuously etching, or introducing CF4, N2 and Ar for etching and then introducing CF4, N2, Ar and C4F8 and continuously etching. In the environment of the CF4, the N2 and the Ar, the ratio of the etching rate of the silicon-containing coating to the etching rate of a dielectric layer with a low dielectric constant can reach 1.1; in the environment of the CF4, the N2, the Ar and the C4F8, the ratio of the etching rate of the silicon-containing coating to the etching rate of the dielectric layer with the low dielectric constant can reach 3, thereby over etching of the silicon-containing coating is extremely realized when the interconnected groove etching is carried out. Therefore, the method is beneficial to enabling the top of a through hole and the bottom of the interconnected groove to form a circular corner, avoids the damage to the side of the interconnected groove and enables the interconnected groove to keep vertical.
Description
Technical field
The present invention relates to technical field of semiconductor device, relate in particular to a kind of method for preparing double damask structure.
Background technology
Along with the continuous development of ic manufacturing technology, the characteristic line breadth of semiconductor chip constantly dwindles; Simultaneously, along with the number of transistors in the chip constantly increases, function is more and more stronger, and the metal connecting line of chip is in more and more thinner, and level is more and more.This just makes by the RC delay of dielectric layer electric capacity generation between connection resistances and line increasing to the influence of chip speed, even has surpassed the grid delay that determines the speed of transistor own.Therefore manage to reduce connection resistances and reduce electric capacity between line, become the key of further raising chip speed.
In order to solve the problem that resistance-capacitance postpones (RC delay), the measure of taking in the industry is: (1) uses the dielectric materials (dielectric constant is 0.2 to 0.4) that meets IC technology, make the permittivity ratio silicon of the dielectric layer between the multi-metal intra-connection lower, thereby reduce parasitic capacitance; (2) adopt copper to replace aluminium as the electric conducting material of interconnection line in the semiconductor element, reduce resistance; Compare with aluminium, the resistance coefficient of copper is little, the fusing point height, and anti-electromigration ability is strong, and can carry higher current density, and because copper can be done carefullyyer, therefore adopts copper wiring can also reduce electric capacity and power consumption, can improve the packaging density of element simultaneously.
Because copper is difficult to be etched, the lithographic technique that therefore is used to form the aluminum metal wiring traditionally is inapplicable for copper.For this reason, a kind of new wire laying mode that is called as dual damascene (Dual Damascene) structure is developed.The wire laying mode of so-called double damask structure refers to: leave earlier interconnection channel and through hole in dielectric layer, by electroplating or electroless copper cement copper in interconnection channel and through hole, recycling chemico-mechanical polishing (CMP) grinds off crossing the copper of filling out then.
More than adopt back end of line (BEOL, the Back End Of Line) technology of dielectric materials and copper-connection to be commonly referred to high-end back end of line technology, high-end back end of line technology need satisfy following two requirements usually:
(1) please refer to Figure 1A, in double damask structure, radiused corners (shown in circle identification division among Figure 1A) need be formed on the bottom of the top of through hole 102 and interconnection channel 101, the current density that prevents corner is excessive and cause adjacent area to produce electromigration (electro migration), can pass through electro-migration testing;
(2) please refer to Figure 1B, in double damask structure, the side of interconnection channel 101 (shown in circle identification division among Figure 1B) needs vertical, generally require the side of interconnection channel 101 and the angle of horizontal plane to spend greater than 86, prevent from diminishing because of the distance that interconnection channel 101 tilts to cause to link to each other between two metals in the same metal level, cause that puncture voltage (VBD, Voltage Break Down) reduces; Can test by puncture voltage.
Traditional preparation method of double damask structure please refer to Fig. 2 and Fig. 3 A to Fig. 3 H, wherein, Fig. 2 is traditional preparation method's flow chart of steps of double damask structure, Fig. 3 A to Fig. 3 H is the cross-sectional view of the device of each step correspondence among traditional preparation method of double damask structure, shown in Fig. 2 and Fig. 3 A to Fig. 3 H, traditional preparation method of double damask structure comprises the steps:
S101, provide Semiconductor substrate 101, wherein, required semiconductor device and the first metal layer have been prepared on the described Semiconductor substrate 101, described the first metal layer comprises intermetallic dielectric layer (IMD, Inter-Metal Dielectric) 102 and the metal 103 that is arranged in described intermetallic dielectric layer 102;
S102, on described ground floor metal level deposit etching barrier layer 104, first dielectric layer 105, second dielectric layer 106 and photoresistance 107 successively, and described photoresistance 107 is graphical, the definition via hole image, as shown in Figure 3A;
S103, be mask with described patterned photoresistance 107, described first dielectric layer 105 and second dielectric layer 106 are carried out etching, form through hole 108, and remove described patterned photoresistance 107, shown in Fig. 3 B;
S104, deposit bottom antireflective coating (BARC, Bottom Anti Reflective Coating) the 109, the 3rd dielectric layer 110 and photoresistance 111 successively, described bottom antireflective coating 109 fills up described through hole 108, and covers described second dielectric layer 106;
S105, described photoresistance 111 is graphical, definition interconnection channel figure is shown in Fig. 3 C;
S106, be mask with described patterned photoresistance 111, described the 3rd dielectric layer 110 is carried out etching, expose described bottom antireflective coating 109, shown in Fig. 3 D; And remove described graphical photoresistance 111;
S107, be mask with the 3rd dielectric layer 110 after the described etching, described bottom antireflective coating 109 and described second dielectric layer 106 are carried out etching, expose described first dielectric layer 105, afterwards described bottom antireflective coating 109 is returned etching, make its height that highly is lower than described first dielectric layer 105, shown in Fig. 3 E; And remove described the 3rd dielectric layer 110;
S108, be mask with second dielectric layer 106 after the described etching, described first dielectric layer 105 and described bottom antireflective coating 109 are carried out etching, form interconnection channel 112, shown in Fig. 3 F;
S109, the remaining bottom antireflective coating 109 of removal are shown in Fig. 3 G; And
S110, remove the etching barrier layer 104 under the described through hole, described through hole is contacted, with metal 103 in the described the first metal layer shown in Fig. 3 H.
Utilize the double damask structure of above-mentioned conventional method preparation, though can satisfy this requirement of lateral vertical of interconnection channel, can not satisfy the top of through hole and the bottom of interconnection channel and need form this requirement of radiused corners; Therefore, be easy to generate electromigration.
For radiused corners is formed on the bottom of the top that makes through hole and interconnection channel, the another kind of method for preparing double damask structure has been proposed, please refer to Fig. 4 and Fig. 5 A to Fig. 5 J, wherein Fig. 4 is existing second kind of preparation method's flow chart of steps of double damask structure, Fig. 5 A to Fig. 5 J is the cross-sectional view of the device of each step correspondence among existing second kind of preparation method of double damask structure, shown in Fig. 4 and Fig. 5 A to Fig. 5 J, existing second kind of preparation method of double damask structure comprises the steps:
S201, provide Semiconductor substrate 201, wherein, required semiconductor device and the first metal layer have been prepared on the described Semiconductor substrate 201, described the first metal layer comprises intermetallic dielectric layer (IMD, Inter-Metal Dielectric) 202 and the metal 203 that is arranged in described intermetallic dielectric layer 202;
S202, on described ground floor metal level deposit etching barrier layer 204, first dielectric layer 205, second dielectric layer 206 and photoresistance 207 successively, and described photoresistance 207 is graphical, the definition via hole image is shown in Fig. 5 A;
S203, be mask with described patterned photoresistance 207, described first dielectric layer 205 and second dielectric layer 206 are carried out etching, form through hole 208, and remove described patterned photoresistance 207, shown in Fig. 5 B;
S204, deposit bottom antireflective coating (BARC, Bottom Anti Reflective Coating) the 209, the 3rd dielectric layer 210 and photoresistance 211 successively, described bottom antireflective coating 209 fills up described through hole 208, and covers described second dielectric layer 206;
S205, described photoresistance 211 is graphical, definition interconnection channel figure is shown in Fig. 5 C;
S206, be mask with described patterned photoresistance 211, described the 3rd dielectric layer 210 is carried out etching, expose described bottom antireflective coating 209, shown in Fig. 5 D; And remove described graphical photoresistance 211;
S207, be mask with the 3rd dielectric layer 210 after the described etching, described bottom antireflective coating 209 and described second dielectric layer 206 are carried out etching, expose described first dielectric layer 205, afterwards described bottom antireflective coating 209 is returned etching, make its height that highly is lower than described first dielectric layer 205, shown in Fig. 5 E; And remove described the 3rd dielectric layer 210;
S208, be mask with second dielectric layer 206 after the described etching, described first dielectric layer 205 and described bottom antireflective coating 209 are carried out etching, the height of described bottom antireflective coating 209 is identical with the height of described first dielectric layer 205, forms interconnection channel 212, shown in Fig. 5 F;
S209, described bottom antireflective coating 209 is carried out over etching, make the height of described bottom antireflective coating 209 be lower than the height of described first dielectric layer 205, shown in Fig. 5 G;
S210, described bottom anti-reflection layer 209 and described first dielectric layer 205 are carried out etching, make the bottom of interconnection channel 212 and the top formation radiused corners of through hole, shown in Fig. 5 H;
S211, the remaining bottom antireflective coating 209 of removal are shown in Fig. 5 I; And
S212, remove the etching barrier layer 204 under the described through hole, described through hole is contacted, with metal 203 in the described the first metal layer shown in Fig. 5 J.
Utilize the double damask structure of above-mentioned existing second method preparation, need form this requirement of radiused corners though can satisfy the top of through hole and the bottom of interconnection channel, but can not satisfy this requirement of lateral vertical of interconnection channel, this is because in step S210, the side of interconnection channel 212 is further etched, thereby forms incline structure.
Therefore, utilize existing method to be difficult to satisfy simultaneously the top of through hole and the bottom formation radiused corners of interconnection channel, and these two requirements of the lateral vertical of interconnection channel.
Summary of the invention
The object of the present invention is to provide a kind of method for preparing double damask structure, can not satisfy the top of through hole and the bottom formation radiused corners of interconnection channel simultaneously with the method that solves the existing preparation dual damascene, and the problem of these two requirements of the lateral vertical of interconnection channel.
For addressing the above problem, the present invention proposes a kind of method for preparing double damask structure, and this method comprises the steps:
Semiconductor substrate is provided, wherein, has prepared required semiconductor device and the first metal layer on the described Semiconductor substrate;
Deposit etching barrier layer, first dielectric layer, second dielectric layer and photoresistance successively on described ground floor metal level, and described photoresistance is graphical, the definition via hole image;
Be mask with described patterned photoresistance, described first dielectric layer and second dielectric layer are carried out etching, form through hole, and remove described patterned photoresistance;
Depositing silicon coating in described through hole, the described silicon coating that contains does not fill up described through hole, and the described thickness of silicon coating in described through hole that contains is first thickness;
Deposit bottom antireflective coating, the 3rd dielectric layer and photoresistance successively, described bottom antireflective coating fills up and is not contained the part that silicon coating is filled in the described through hole, and covers described second dielectric layer;
Described photoresistance is graphical, definition interconnection channel figure;
Be mask with described patterned photoresistance, described the 3rd dielectric layer is carried out etching, until exposing described bottom antireflective coating, and remove patterned photoresistance;
Be mask with the 3rd dielectric layer after the described etching, described bottom antireflective coating and second dielectric layer are carried out etching, until exposing described first dielectric layer, and remove the 3rd dielectric layer after the described etching;
Be mask with second dielectric layer after the described etching and the bottom antireflective coating that is positioned on described second dielectric layer, bottom antireflective coating in described first dielectric layer and the through hole is carried out etching, until exposing the described silicon coating that contains, at this moment, be coated with remaining bottom antireflective coating on second dielectric layer after the described etching;
Be mask with second dielectric layer after the described etching and bottom antireflective coating, feeding CF
4, N
2And under the condition of Ar to described first dielectric layer and contain silicon coating and carry out etching; Perhaps formerly feed CF
4, N
2And under the condition of Ar to described first dielectric layer and after containing silicon coating etching a period of time, feeding CF again
4, N
2, Ar and C
4F
8Condition under to described first dielectric layer and contain silicon coating and carry out etching, form interconnection channel, at this moment, described through hole contains residue and contains silicon coating;
Remove remaining bottom anti-reflection layer and the remaining silicon coating that contains; And
Remove the etching barrier layer under the described through hole, described through hole is contacted with described the first metal layer.
Optionally, the described silicon coating that contains is that deep UV absorbs oxide or siliceous bottom antireflective coating.
Optionally, the scope of described first thickness is 500～2000 dusts.
Optionally, described CF
4Flow be 50～500sccm, N
2Flow be 100～500sccm, the flow of Ar is 100～500sccm.
Optionally, described CF
4Flow be 50～500sccm, N
2Flow be 100～500sccm, the flow of Ar is 100～500sccm, C
4F
8Flow be 10～50sccm.
Optionally, the described remaining silicon coating that contains is removed by wet etching.
Optionally, described graphically is to realize by the immersion lithography technology with photoresistance.
Optionally, described etching barrier layer is the carborundum that silicon nitride or nitrogen mix.
Optionally, described first dielectric layer is low dielectric coefficient medium layer.
Optionally, described low dielectric coefficient medium layer be carbon dope silicon dioxide or cellular silicon dioxide.
Optionally, described second dielectric layer is hard mask layer, and its material is tetraethyl orthosilicate (TEOS).
Optionally, described the 3rd dielectric layer is cap rock, and its material is silicon dioxide or silicon nitride.
Compared with prior art, the method for preparing double damask structure provided by the invention by in through hole earlier a deposition part contain silicon coating, deposit bottom antireflective coating again, carry out the interconnection channel etching afterwards, described when containing silicon coating when exposing, feed CF
4, N
2Reach Ar and continue etching, perhaps feed CF earlier
4, N
2Reach Ar and carry out etching, feed CF again
4, N
2, Ar and C
4F
8Continue etching; Because at CF
4, N
2And under the environment of Ar, the etching rate that contains silicon coating can reach 1.1 with the ratio of the etching rate of low dielectric coefficient medium layer, at CF
4, N
2, Ar and C
4F
8Environment under, the etching rate that contains silicon coating can reach 3 with the ratio of the etching rate of low dielectric coefficient medium layer, thereby when carrying out the interconnection channel etching, can very easily realize containing the over etching of silicon coating, thereby be conducive to make the top of through hole and the bottom of interconnection channel to form radiused corners, and because the described required etch period weak point of over etching that contains silicon coating, thereby avoid damage is caused in the side of interconnection channel, make the side of interconnection channel keep vertical.
Figure 1A to Figure 1B is the double damask structure schematic diagram;
Fig. 2 is traditional preparation method's flow chart of steps of double damask structure;
Fig. 3 A to Fig. 3 H is the cross-sectional view of the device of each step correspondence among traditional preparation method of double damask structure;
Fig. 4 is existing second kind of preparation method's flow chart of steps of double damask structure;
Fig. 5 A to Fig. 5 J is the cross-sectional view of the device of each step correspondence among existing second kind of preparation method of double damask structure;
Description of drawings
Figure 1A to Figure 1B is the double damask structure schematic diagram;
Fig. 2 is traditional preparation method's flow chart of steps of double damask structure;
Fig. 3 A to Fig. 3 H is the cross-sectional view of the device of each step correspondence among traditional preparation method of double damask structure;
Fig. 4 is existing second kind of preparation method's flow chart of steps of double damask structure;
Fig. 5 A to Fig. 5 J is the cross-sectional view of the device of each step correspondence among existing second kind of preparation method of double damask structure;
The method step flow chart of the preparation double damask structure that Fig. 6 provides for the embodiment of the invention;
The cross-sectional view of the device of each step correspondence in the method for preparing double damask structure that Fig. 7 A to Fig. 7 J provides for the embodiment of the invention;
The shape of double damask structure after electro-coppering that the method that Fig. 8 provides for the employing embodiment of the invention prepares.
Embodiment
Below in conjunction with the drawings and specific embodiments the method for preparing double damask structure that the present invention proposes is described in further detail.According to the following describes and claims, advantages and features of the invention will be clearer.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only be used for convenient, the purpose of the aid illustration embodiment of the invention lucidly.
Core concept of the present invention is, a kind of method for preparing double damask structure is provided, and this method contains silicon coating by deposit a part earlier in through hole, deposit bottom antireflective coating again, carry out the interconnection channel etching afterwards, described when containing silicon coating when exposing, feed CF
4, N
2Reach Ar and continue etching, perhaps feed CF earlier
4, N
2Reach Ar and carry out etching, feed CF again
4, N
2, Ar and C
4F
8Continue etching; Because at CF
4, N
2And under the environment of Ar, the etching rate that contains silicon coating can reach 1.1 with the ratio of the etching rate of low dielectric coefficient medium layer, at CF
4, N
2, Ar and C
4F
8Environment under, the etching rate that contains silicon coating can reach 3 with the ratio of the etching rate of low dielectric coefficient medium layer, thereby when carrying out the interconnection channel etching, can very easily realize containing the over etching of silicon coating, thereby be conducive to make the top of through hole and the bottom of interconnection channel to form radiused corners, and because the described required etch period weak point of over etching that contains silicon coating, thereby avoid damage is caused in the side of interconnection channel, make the side of interconnection channel keep vertical.
Please refer to Fig. 6, and Fig. 7 A to Fig. 7 J, wherein, the method step flow chart of the preparation double damask structure that Fig. 6 provides for the embodiment of the invention, the cross-sectional view of the device of each step correspondence in the method for preparing double damask structure that Fig. 7 A to Fig. 7 J provides for the embodiment of the invention, shown in Fig. 6 and Fig. 7 A to Fig. 7 J, the method for preparing double damask structure that the embodiment of the invention provides comprises the steps:
S301, provide Semiconductor substrate 301, wherein, prepared required semiconductor device and the first metal layer on the described Semiconductor substrate 301; Concrete, described the first metal layer comprises intermetallic dielectric layer (IMD, Inter-Metal Dielectric) 302 and the metal 303 that is arranged in described intermetallic dielectric layer 302;
S302, on described ground floor metal level deposit etching barrier layer 304, first dielectric layer 305, second dielectric layer 306 and photoresistance 307 successively, and described photoresistance 307 is graphical, the definition via hole image is shown in Fig. 7 A;
S303, be mask with described patterned photoresistance 307, described first dielectric layer 305 and second dielectric layer 306 are carried out etching, form through hole 308, and remove described patterned photoresistance 307, shown in Fig. 7 B;
S304, in described through hole 308 depositing silicon coating 309, the described silicon coating 309 that contains does not fill up described through hole 308, and described to contain the thickness of silicon coating 309 in described through hole 308 be first thickness, shown in Fig. 7 C;
S305, deposit bottom antireflective coating 310, the 3rd dielectric layer 311 and photoresistance 312 successively, described bottom antireflective coating 310 fills up and is not contained the part that silicon coating 309 is filled in the described through hole, and covers described second dielectric layer 306;
S306, described photoresistance 312 is graphical, definition interconnection channel figure is shown in Fig. 7 D;
S307, be mask with described patterned photoresistance 312, described the 3rd dielectric layer 311 carried out etching, until exposing described bottom antireflective coating 310, shown in Fig. 7 E; And remove patterned photoresistance 312;
S308, be mask with the 3rd dielectric layer 311 after the described etching, described bottom antireflective coating 310 and second dielectric layer 306 carried out etching, until exposing described first dielectric layer 305, shown in Fig. 7 F; And remove the 3rd dielectric layer 311 after the described etching;
S309, be mask with second dielectric layer 306 after the described etching and the bottom antireflective coating 310 that is positioned on described second dielectric layer 306, bottom antireflective coating 310 in described first dielectric layer 305 and the through hole is carried out etching, until exposing the described silicon coating 309 that contains, at this moment, be coated with remaining bottom antireflective coating 310 on second dielectric layer 306 after the described etching, shown in Fig. 7 G;
S310, be mask with second dielectric layer 306 after the described etching and bottom antireflective coating 310, feeding CF
4, N
2And under the condition of Ar to described first dielectric layer 305 and contain silicon coating 309 and carry out etching; Perhaps formerly feed CF
4, N
2And under the condition of Ar to described first dielectric layer 305 and contain silicon coating 309 etchings after a period of time, feeding CF again
4, N
2, Ar and C
4F
8Condition under to described first dielectric layer 305 and contain silicon coating 309 and carry out etching, form interconnection channel 301, at this moment, described through hole contains residue and contains silicon coating 309, shown in Fig. 7 H;
S311, the remaining bottom antireflective coating 310 of removal and the remaining silicon coating 309 that contains are shown in Fig. 7 I; And
S312, remove the etching barrier layer 304 under the described through hole, described through hole is contacted with described the first metal layer, concrete, described through hole is contacted, shown in Fig. 7 J with metal 303 in the described the first metal layer.
Further, the described silicon coating 309 that contains absorbs oxide or siliceous bottom antireflective coating for deep UV, thereby makes it at CF
4, N
2And can have high etching selection ratio under the condition of Ar.
Further, the scope of described first thickness is 500～2000 dusts, thereby makes the described silicon coating 309 that contains still have residue after forming interconnection channel.
Further, described CF
4Flow be 50～500sccm, N
2Flow be 100～500sccm, the flow of Ar is 100～500sccm.
Further, described CF
4Flow be 50～500sccm, N
2Flow be 100～500sccm, the flow of Ar is 100～500sccm, C
4F
8Flow be 10～50sccm.
Further, the described remaining silicon coating that contains is removed by wet etching.
Further, described graphically is to realize by the immersion lithography technology with photoresistance.
Further, described etching barrier layer is the carborundum that silicon nitride or nitrogen mix.
Further, described first dielectric layer is low dielectric coefficient medium layer.
Further, described low dielectric coefficient medium layer is silicon dioxide or the cellular silicon dioxide of carbon dope.
Further, described second dielectric layer is hard mask layer, and its material is tetraethyl orthosilicate (TEOS), and it act as after electro-coppering, copper is carried out shield in the process of CMP, prevents from damaging first dielectric layer.
Further, described the 3rd dielectric layer is cap rock, and its material is silicon dioxide or silicon nitride.
Please continue with reference to figure 8, the shape of double damask structure after electro-coppering that the method that Fig. 8 provides for the employing embodiment of the invention prepares, as shown in Figure 8, after the electro-coppering, semicircular structure is formed on the interconnection channel bottom of this damascene structure, bottom to the ratio of the distance y of via top and the width x of interconnection channel bottom that is interconnection channel is 1, and wherein x is 200 dusts; And the angle of interconnection channel side and bottom is 88 degree.Thereby the top of satisfying through hole keeps vertical these two requirements with the side that radiused corners and interconnection channel are formed on the bottom of interconnection channel.
In a specific embodiment of the present invention, the flow of described Ar is 100～500sccm, yet should be realized that, because Ar mainly shields, its range of flow is wider, according to actual conditions, can also get other flow.
In sum, the invention provides a kind of method for preparing double damask structure, this method by in through hole earlier a deposition part contain silicon coating, deposit bottom antireflective coating again, carry out the interconnection channel etching afterwards, described when containing silicon coating when exposing, feed CF
4, N
2Reach Ar and continue etching, perhaps feed CF earlier
4, N
2Reach Ar and carry out etching, feed CF again
4, N
2, Ar and C
4F
8Continue etching; Because at CF
4, N
2And under the environment of Ar, the etching rate that contains silicon coating can reach 1.1 with the ratio of the etching rate of low dielectric coefficient medium layer, at CF
4, N
2, Ar and C
4F
8Environment under, the etching rate that contains silicon coating can reach 3 with the ratio of the etching rate of low dielectric coefficient medium layer, thereby when carrying out the interconnection channel etching, can very easily realize containing the over etching of silicon coating, thereby be conducive to make the top of through hole and the bottom of interconnection channel to form radiused corners, and because the described required etch period weak point of over etching that contains silicon coating, thereby avoid damage is caused in the side of interconnection channel, make the side of interconnection channel keep vertical.
Obviously, those skilled in the art can carry out various changes and modification to invention and not break away from the spirit and scope of the present invention.Like this, if of the present invention these are revised and modification belongs within the scope of claim of the present invention and equivalent technologies thereof, then the present invention also is intended to comprise these changes and modification interior.
Claims (12)
1. a method for preparing double damask structure is characterized in that, this method comprises the steps:
Semiconductor substrate is provided, wherein, has prepared required semiconductor device and the first metal layer on the described Semiconductor substrate;
Deposit etching barrier layer, first dielectric layer, second dielectric layer and photoresistance successively on described ground floor metal level, and described photoresistance is graphical, the definition via hole image;
Be mask with described patterned photoresistance, described first dielectric layer and second dielectric layer are carried out etching, form through hole, and remove described patterned photoresistance;
Depositing silicon coating in described through hole, the described silicon coating that contains does not fill up described through hole, and the described thickness of silicon coating in described through hole that contains is first thickness;
Deposit bottom antireflective coating, the 3rd dielectric layer and photoresistance successively, described bottom antireflective coating fills up and is not contained the part that silicon coating is filled in the described through hole, and covers described second dielectric layer;
Described photoresistance is graphical, definition interconnection channel figure;
Be mask with described patterned photoresistance, described the 3rd dielectric layer is carried out etching, until exposing described bottom antireflective coating, and remove patterned photoresistance;
Be mask with the 3rd dielectric layer after the described etching, described bottom antireflective coating and second dielectric layer are carried out etching, until exposing described first dielectric layer, and remove the 3rd dielectric layer after the described etching;
Be mask with second dielectric layer after the described etching and the bottom antireflective coating that is positioned on described second dielectric layer, bottom antireflective coating in described first dielectric layer and the through hole is carried out etching, until exposing the described silicon coating that contains, at this moment, be coated with remaining bottom antireflective coating on second dielectric layer after the described etching;
Be mask with second dielectric layer after the described etching and bottom antireflective coating, feeding CF
4, N
2And under the condition of Ar to described first dielectric layer and contain silicon coating and carry out etching; Perhaps formerly feed CF
4, N
2And under the condition of Ar to described first dielectric layer and after containing silicon coating etching a period of time, feeding CF again
4, N
2, Ar and C
4F
8Condition under to described first dielectric layer and contain silicon coating and carry out etching, form interconnection channel, at this moment, described through hole contains residue and contains silicon coating;
Remove remaining bottom antireflective coating and the remaining silicon coating that contains; And
Remove the etching barrier layer under the described through hole, described through hole is contacted with described the first metal layer.
2. the method for preparing double damask structure as claimed in claim 1 is characterized in that, the described silicon coating that contains is that deep UV absorbs oxide or siliceous bottom antireflective coating.
3. the method for preparing double damask structure as claimed in claim 1 is characterized in that, the scope of described first thickness is 500～2000 dusts.
4. the method for preparing double damask structure as claimed in claim 1 is characterized in that, described CF
4Flow be 50～500sccm, N
2Flow be 100～500sccm, the flow of Ar is 100～500sccm.
5. the method for preparing double damask structure as claimed in claim 1 is characterized in that, described CF
4Flow be 50～500sccm, N
2Flow be 100～500sccm, the flow of Ar is 100～500sccm, C
4F
8Flow be 10～50sccm.
6. the method for preparing double damask structure as claimed in claim 1 is characterized in that, the described remaining silicon coating that contains is removed by wet etching.
7. the method for preparing double damask structure as claimed in claim 1 is characterized in that, described graphically is to realize by the immersion lithography technology with photoresistance.
8. the method for preparing double damask structure as claimed in claim 1 is characterized in that, described etching barrier layer is the carborundum that silicon nitride or nitrogen mix.
9. the method for preparing double damask structure as claimed in claim 1 is characterized in that, described first dielectric layer is low dielectric coefficient medium layer.
10. the method for preparing double damask structure as claimed in claim 9 is characterized in that, described low dielectric coefficient medium layer is silicon dioxide or the cellular silicon dioxide of carbon dope.
11. the method for preparing double damask structure as claimed in claim 1 is characterized in that, described second dielectric layer is hard mask layer, and its material is tetraethyl orthosilicate (TEOS).
12. the method for preparing double damask structure as claimed in claim 1 is characterized in that, described the 3rd dielectric layer is cap rock, and its material is silicon dioxide or silicon nitride.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201010262784 CN102376631B (en) | 2010-08-24 | 2010-08-24 | Method for producing dual damascene structure |
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|---|---|---|---|
| CN 201010262784 CN102376631B (en) | 2010-08-24 | 2010-08-24 | Method for producing dual damascene structure |
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| Publication Number | Publication Date |
|---|---|
| CN102376631A CN102376631A (en) | 2012-03-14 |
| CN102376631B true CN102376631B (en) | 2013-08-14 |
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| US6645851B1 (en) * | 2002-09-17 | 2003-11-11 | Taiwan Semiconductor Manufacturing Company | Method of forming planarized coatings on contact hole patterns of various duty ratios |
| CN101154584A (en) * | 2006-09-30 | 2008-04-02 | 中芯国际集成电路制造(上海)有限公司 | Method for forming medium layer |
| CN101355034A (en) * | 2007-07-27 | 2009-01-28 | 中芯国际集成电路制造(上海)有限公司 | Method for forming photoetch pattern and method for manufacturing dual-damascene structure |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6645851B1 (en) * | 2002-09-17 | 2003-11-11 | Taiwan Semiconductor Manufacturing Company | Method of forming planarized coatings on contact hole patterns of various duty ratios |
| CN101154584A (en) * | 2006-09-30 | 2008-04-02 | 中芯国际集成电路制造(上海)有限公司 | Method for forming medium layer |
| CN101355034A (en) * | 2007-07-27 | 2009-01-28 | 中芯国际集成电路制造(上海)有限公司 | Method for forming photoetch pattern and method for manufacturing dual-damascene structure |
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