CN102376631A - Method for producing dual damascene structure - Google Patents

Method for producing dual damascene structure Download PDF

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Publication number
CN102376631A
CN102376631A CN2010102627847A CN201010262784A CN102376631A CN 102376631 A CN102376631 A CN 102376631A CN 2010102627847 A CN2010102627847 A CN 2010102627847A CN 201010262784 A CN201010262784 A CN 201010262784A CN 102376631 A CN102376631 A CN 102376631A
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dielectric layer
etching
coating
hole
silicon
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CN102376631B (en
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沈满华
张海洋
周俊卿
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
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Abstract

The invention discloses a method for producing a dual damascene structure. The method comprises the following steps of: depositing a part of silicon-containing coating in a through hole; then depositing a bottom antireflective coating; carrying out interconnected groove etching; and when the silicon-containing coating is exposed, introducing CF4, N2 and Ar and continuously etching, or introducing CF4, N2 and Ar for etching and then introducing CF4, N2, Ar and C4F8 and continuously etching. In the environment of the CF4, the N2 and the Ar, the ratio of the etching rate of the silicon-containing coating to the etching rate of a dielectric layer with a low dielectric constant can reach 1.1; in the environment of the CF4, the N2, the Ar and the C4F8, the ratio of the etching rate of the silicon-containing coating to the etching rate of the dielectric layer with the low dielectric constant can reach 3, thereby over etching of the silicon-containing coating is extremely realized when the interconnected groove etching is carried out. Therefore, the method is beneficial to enabling the top of a through hole and the bottom of the interconnected groove to form a circular corner, avoids the damage to the side of the interconnected groove and enables the interconnected groove to keep vertical.

Description

The method for preparing double damask structure
Technical field
The present invention relates to technical field of semiconductor device, relate in particular to a kind of method for preparing double damask structure.
Background technology
Along with the continuous development of ic manufacturing technology, the characteristic line breadth of semiconductor chip constantly dwindles; Simultaneously, along with the number of transistors in the chip constantly increases, function is more and more stronger, and the metal connecting line of chip is in more and more thinner, and level is more and more.This just makes by the RC delay of dielectric layer electric capacity generation between connection resistances and line increasing to the influence of chip speed, even has surpassed the grid delay of the speed of decision transistor own.Therefore manage to reduce connection resistances and reduce electric capacity between line, become the key of further raising chip speed.
In order to solve the problem that resistance-capacitance postpones (RC delay); The measure of taking in the industry is: the dielectric materials (dielectric constant is 0.2 to 0.4) that meets IC technology is used in (1); Make the permittivity ratio silicon of the dielectric layer between the multi-metal intra-connection lower, thereby reduce parasitic capacitance; (2) adopt copper to replace the electric conducting material of aluminium, reduce resistance as interconnection line in the semiconductor element; Compare with aluminium, the resistance coefficient of copper is little, and fusing point is high, and anti-electromigration ability is strong, and can carry higher current density, and because copper can be done carefullyyer, therefore adopts copper wiring can also reduce electric capacity and power consumption, can improve the packaging density of element simultaneously.
Because copper is difficult to be etched, the lithographic technique that therefore is used to form the aluminum metal wiring traditionally is inapplicable for copper.For this reason, a kind of new wire laying mode that is called as dual damascene (Dual Damascene) structure is developed.The wire laying mode of so-called double damask structure is meant: in dielectric layer, leave earlier interconnection channel and through hole, then through electroplating or electroless copper cement copper in interconnection channel and through hole, utilize chemico-mechanical polishing (CMP) to grind off crossing the copper of filling out again.
More than adopt back end of line (BEOL, the Back End Of Line) technology of dielectric materials and copper-connection to be commonly referred to high-end back end of line technology, high-end back end of line technology need satisfy following two requirements usually:
(1) please refer to Figure 1A; In double damask structure; Radiused corners (shown in circle identification division among Figure 1A) need be formed on the bottom of the top of through hole 102 and interconnection channel 101; The current density that prevents corner is excessive and cause adjacent area to produce electromigration (electro migration), makes it can pass through electro-migration testing;
(2) please refer to Figure 1B; In double damask structure; The side of interconnection channel 101 (shown in circle identification division among Figure 1B) needs vertical, generally requires the side of interconnection channel 101 and the angle of horizontal plane to spend greater than 86, prevents to diminish because of the distance that interconnection channel 101 tilts to cause to link to each other between two metals in the same metal level; Cause that puncture voltage (VBD, Voltage Break Down) reduces; It can be tested through puncture voltage.
The traditional preparation method of double damask structure please refer to Fig. 2 and Fig. 3 A to Fig. 3 H; Wherein, Fig. 2 is the traditional preparation method flow chart of steps of double damask structure; Fig. 3 A to Fig. 3 H is the cross-sectional view of the corresponding device of each step in the traditional preparation method of double damask structure, and shown in Fig. 2 and Fig. 3 A to Fig. 3 H, the traditional preparation method of double damask structure comprises the steps:
S101, Semiconductor substrate 101 is provided; Wherein, Required semiconductor device and the first metal layer have been prepared on the said Semiconductor substrate 101; Said the first metal layer comprises intermetallic dielectric layer (IMD, Inter-Metal Dielectric) 102 and the metal 103 that is arranged in said intermetallic dielectric layer 102;
S102, on said ground floor metal level deposit etching barrier layer 104, first dielectric layer 105, second dielectric layer 106 and photoresistance 107 successively, and said photoresistance 107 is graphical, the definition via hole image is shown in Fig. 3 A;
S103, be mask, said first dielectric layer 105 and second dielectric layer 106 are carried out etching, form through hole 108, and remove said patterned photoresistance 107, shown in Fig. 3 B with said patterned photoresistance 107;
S104, deposit bottom antireflective coating (BARC, Bottom Anti Reflective Coating) the 109, the 3rd dielectric layer 110 and photoresistance 111 successively, said bottom antireflective coating 109 fills up said through hole 108, and covers said second dielectric layer 106;
S105, said photoresistance 111 is graphical, definition interconnection channel figure is shown in Fig. 3 C;
S106, be mask, said the 3rd dielectric layer 110 is carried out etching, expose said bottom antireflective coating 109, shown in Fig. 3 D with said patterned photoresistance 111; And remove said graphical photoresistance 111;
S107, be mask with the 3rd dielectric layer 110 after the said etching; Said bottom antireflective coating 109 and said second dielectric layer 106 are carried out etching; Expose said first dielectric layer 105; Afterwards said bottom antireflective coating 109 is returned etching, make its height that highly is lower than said first dielectric layer 105, shown in Fig. 3 E; And remove said the 3rd dielectric layer 110;
S108, be mask, said first dielectric layer 105 and said bottom antireflective coating 109 are carried out etching, form interconnection channel 112, shown in Fig. 3 F with second dielectric layer 106 after the said etching;
S109, the remaining bottom antireflective coating 109 of removal are shown in Fig. 3 G; And
S110, remove the etching barrier layer 104 under the said through hole, said through hole is contacted, with metal 103 in the said the first metal layer shown in Fig. 3 H.
Utilize the double damask structure of above-mentioned conventional method preparation,, can not satisfy the top of through hole and the bottom of interconnection channel and need form this requirement of radiused corners though can satisfy this requirement of lateral vertical of interconnection channel; Therefore, be easy to generate electromigration.
For radiused corners is formed on the bottom of the top that makes through hole and interconnection channel; The another kind of method for preparing double damask structure has been proposed; Please refer to Fig. 4 and Fig. 5 A to Fig. 5 J; Wherein Fig. 4 is existing second kind of preparation method's flow chart of steps of double damask structure; Fig. 5 A to Fig. 5 J is the cross-sectional view of the corresponding device of each step among existing second kind of preparation method of double damask structure, and shown in Fig. 4 and Fig. 5 A to Fig. 5 J, existing second kind of preparation method of double damask structure comprises the steps:
S201, Semiconductor substrate 201 is provided; Wherein, Required semiconductor device and the first metal layer have been prepared on the said Semiconductor substrate 201; Said the first metal layer comprises intermetallic dielectric layer (IMD, Inter-Metal Dielectric) 202 and the metal 203 that is arranged in said intermetallic dielectric layer 202;
S202, on said ground floor metal level deposit etching barrier layer 204, first dielectric layer 205, second dielectric layer 206 and photoresistance 207 successively, and said photoresistance 207 is graphical, the definition via hole image is shown in Fig. 5 A;
S203, be mask, said first dielectric layer 205 and second dielectric layer 206 are carried out etching, form through hole 208, and remove said patterned photoresistance 207, shown in Fig. 5 B with said patterned photoresistance 207;
S204, deposit bottom antireflective coating (BARC, Bottom Anti Reflective Coating) the 209, the 3rd dielectric layer 210 and photoresistance 211 successively, said bottom antireflective coating 209 fills up said through hole 208, and covers said second dielectric layer 206;
S205, said photoresistance 211 is graphical, definition interconnection channel figure is shown in Fig. 5 C;
S206, be mask, said the 3rd dielectric layer 210 is carried out etching, expose said bottom antireflective coating 209, shown in Fig. 5 D with said patterned photoresistance 211; And remove said graphical photoresistance 211;
S207, be mask with the 3rd dielectric layer 210 after the said etching; Said bottom antireflective coating 209 and said second dielectric layer 206 are carried out etching; Expose said first dielectric layer 205; Afterwards said bottom antireflective coating 209 is returned etching, make its height that highly is lower than said first dielectric layer 205, shown in Fig. 5 E; And remove said the 3rd dielectric layer 210;
S208, be mask with second dielectric layer 206 after the said etching; Said first dielectric layer 205 and said bottom antireflective coating 209 are carried out etching; The height of said bottom antireflective coating 209 is identical with the height of said first dielectric layer 205, forms interconnection channel 212, shown in Fig. 5 F;
S209, said bottom antireflective coating 209 is carried out over etching, make the height of said bottom antireflective coating 209 be lower than the height of said first dielectric layer 205, shown in Fig. 5 G;
S210, said bottom anti-reflection layer 209 and said first dielectric layer 205 are carried out etching, make the bottom of interconnection channel 212 and the top formation radiused corners of through hole, shown in Fig. 5 H;
S211, the remaining bottom antireflective coating 209 of removal are shown in Fig. 5 I; And
S212, remove the etching barrier layer 204 under the said through hole, said through hole is contacted, with metal 203 in the said the first metal layer shown in Fig. 5 J.
Utilize the double damask structure of above-mentioned existing second method preparation; Need form this requirement of radiused corners though can satisfy the top of through hole and the bottom of interconnection channel; But can not satisfy this requirement of lateral vertical of interconnection channel; This is because in step S210, and the side of interconnection channel 212 is by further etching, thus the formation incline structure.
Therefore, utilize existing method to be difficult to satisfy simultaneously the top of through hole and the bottom formation radiused corners of interconnection channel, and these two requirements of the lateral vertical of interconnection channel.
Summary of the invention
The object of the present invention is to provide a kind of method for preparing double damask structure; Can not satisfy the top of through hole and the bottom formation radiused corners of interconnection channel simultaneously with the method that solves the existing preparation dual damascene, and the problem of these two requirements of the lateral vertical of interconnection channel.
For addressing the above problem, the present invention proposes a kind of method for preparing double damask structure, and this method comprises the steps:
Semiconductor substrate is provided, wherein, has prepared required semiconductor device and the first metal layer on the said Semiconductor substrate;
Deposit etching barrier layer, first dielectric layer, second dielectric layer and photoresistance successively on said ground floor metal level, and said photoresistance is graphical, the definition via hole image;
With said patterned photoresistance is mask, and said first dielectric layer and second dielectric layer are carried out etching, forms through hole, and removes said patterned photoresistance;
Depositing silicon coating in said through hole, the said silicon coating that contains does not fill up said through hole, and the said thickness of silicon coating in said through hole that contains is first thickness;
Deposit bottom antireflective coating, the 3rd dielectric layer and photoresistance successively, said bottom antireflective coating fills up and is not contained the part that silicon coating is filled in the said through hole, and covers said second dielectric layer;
Said photoresistance is graphical, definition interconnection channel figure;
With said patterned photoresistance is mask, and said the 3rd dielectric layer is carried out etching, until exposing said bottom antireflective coating, and removes patterned photoresistance;
With the 3rd dielectric layer after the said etching is mask, and the said bottom antireflective coating and second dielectric layer are carried out etching, until exposing said first dielectric layer, and removes the 3rd dielectric layer after the said etching;
With second dielectric layer after the said etching and the bottom antireflective coating that is positioned on said second dielectric layer is mask; Bottom antireflective coating in said first dielectric layer and the through hole carries out etching; Until exposing the said silicon coating that contains; At this moment, be coated with remaining bottom antireflective coating on second dielectric layer after the said etching;
With second dielectric layer after the said etching and bottom antireflective coating is mask, is feeding CF 4, N 2And under the condition of Ar to said first dielectric layer and contain silicon coating and carry out etching; Perhaps formerly feed CF 4, N 2And under the condition of Ar to said first dielectric layer and after containing silicon coating etching a period of time, feeding CF again 4, N 2, Ar and C 4F 8Condition under to said first dielectric layer and contain silicon coating and carry out etching, form interconnection channel, at this moment, said through hole contains residue and contains silicon coating;
Remove remaining bottom anti-reflection layer and the remaining silicon coating that contains; And
Remove the etching barrier layer under the said through hole, said through hole is contacted with said the first metal layer.
Optional, the said silicon coating that contains is that deep UV absorbs oxide or siliceous bottom antireflective coating.
Optional, the scope of said first thickness is 500~2000 dusts.
Optional, said CF 4Flow be 50~500sccm, N 2Flow be 100~500sccm, the flow of Ar is 100~500sccm.
Optional, said CF 4Flow be 50~500sccm, N 2Flow be 100~500sccm, the flow of Ar is 100~500sccm, C 4F 8Flow be 10~50sccm.
Optional, the said remaining silicon coating that contains is removed through wet etching.
Optional, said graphically is to realize through the immersion lithography technology with photoresistance.
Optional, said etching barrier layer is the carborundum that silicon nitride or nitrogen mix.
Optional, said first dielectric layer is a low dielectric coefficient medium layer.
Optional, said low dielectric coefficient medium layer is the silicon dioxide or the cellular silicon dioxide of carbon dope.
Optional, said second dielectric layer is a hard mask layer, its material is tetraethyl orthosilicate (TEOS).
Optional, said the 3rd dielectric layer is a cap rock, its material is silicon dioxide or silicon nitride.
Compared with prior art, the method for preparing double damask structure provided by the invention through in through hole earlier a deposition part contain silicon coating, deposit bottom antireflective coating again, carry out the interconnection channel etching afterwards, said when containing silicon coating when exposing, feed CF 4, N 2Reach Ar and continue etching, perhaps feed CF earlier 4, N 2Reach Ar and carry out etching, feed CF again 4, N 2, Ar and C 4F 8Continue etching; Because at CF 4, N 2And under the environment of Ar, the etching rate that contains silicon coating can reach 1.1 with the ratio of the etching rate of low dielectric coefficient medium layer, at CF 4, N 2, Ar and C 4F 8Environment under; The etching rate that contains silicon coating can reach 3 with the ratio of the etching rate of low dielectric coefficient medium layer, thereby when carrying out the interconnection channel etching, can very easily realize containing the over etching of silicon coating; Thereby help making the top of through hole and the bottom of interconnection channel to form radiused corners; And because the said required etch period weak point of over etching that contains silicon coating, thereby avoid damage is caused in the side of interconnection channel, make the side of interconnection channel keep vertical.
Description of drawings
Figure 1A to Figure 1B is the double damask structure sketch map;
Fig. 2 is the traditional preparation method flow chart of steps of double damask structure;
Fig. 3 A to Fig. 3 H is the cross-sectional view of the corresponding device of each step in the traditional preparation method of double damask structure;
Fig. 4 is existing second kind of preparation method's flow chart of steps of double damask structure;
Fig. 5 A to Fig. 5 J is the cross-sectional view of the corresponding device of each step among existing second kind of preparation method of double damask structure;
The method step flow chart of the preparation double damask structure that Fig. 6 provides for the embodiment of the invention;
Fig. 7 A to Fig. 7 J is the cross-sectional view of the corresponding device of each step in the method for preparing double damask structure that provides of the embodiment of the invention;
The shape of double damask structure after electro-coppering that the method that Fig. 8 provides for the employing embodiment of the invention prepares.
Embodiment
Below in conjunction with accompanying drawing and specific embodiment the method for preparing double damask structure that the present invention proposes is done further explain.According to following explanation and claims, advantage of the present invention and characteristic will be clearer.What need explanation is, accompanying drawing all adopts the form of simplifying very much and all uses non-ratio accurately, only is used for conveniently, the purpose of the aid illustration embodiment of the invention lucidly.
Core concept of the present invention is, a kind of method for preparing double damask structure is provided, and this method contains silicon coating through in through hole, depositing a part earlier; Deposit bottom antireflective coating again; Carry out the interconnection channel etching afterwards, said when containing silicon coating when exposing, feed CF 4, N 2Reach Ar and continue etching, perhaps feed CF earlier 4, N 2Reach Ar and carry out etching, feed CF again 4, N 2, Ar and C 4F 8Continue etching; Because at CF 4, N 2And under the environment of Ar, the etching rate that contains silicon coating can reach 1.1 with the ratio of the etching rate of low dielectric coefficient medium layer, at CF 4, N 2, Ar and C 4F 8Environment under; The etching rate that contains silicon coating can reach 3 with the ratio of the etching rate of low dielectric coefficient medium layer, thereby when carrying out the interconnection channel etching, can very easily realize containing the over etching of silicon coating; Thereby help making the top of through hole and the bottom of interconnection channel to form radiused corners; And because the said required etch period weak point of over etching that contains silicon coating, thereby avoid damage is caused in the side of interconnection channel, make the side of interconnection channel keep vertical.
Please refer to Fig. 6; And Fig. 7 A to Fig. 7 J; Wherein, the method step flow chart of the preparation double damask structure that Fig. 6 provides for the embodiment of the invention, Fig. 7 A to Fig. 7 J are the cross-sectional view of the corresponding device of each step in the method for preparing double damask structure that provides of the embodiment of the invention; Shown in Fig. 6 and Fig. 7 A to Fig. 7 J, the method for preparing double damask structure that the embodiment of the invention provides comprises the steps:
S301, Semiconductor substrate 301 is provided, wherein, has prepared required semiconductor device and the first metal layer on the said Semiconductor substrate 301; Concrete, said the first metal layer comprises intermetallic dielectric layer (IMD, Inter-Metal Dielectric) 302 and the metal 303 that is arranged in said intermetallic dielectric layer 302;
S302, on said ground floor metal level deposit etching barrier layer 304, first dielectric layer 305, second dielectric layer 306 and photoresistance 307 successively, and said photoresistance 307 is graphical, the definition via hole image is shown in Fig. 7 A;
S303, be mask, said first dielectric layer 305 and second dielectric layer 306 are carried out etching, form through hole 308, and remove said patterned photoresistance 307, shown in Fig. 7 B with said patterned photoresistance 307;
S304, in said through hole 308 depositing silicon coating 309, the said silicon coating 309 that contains does not fill up said through hole 308, and said to contain the thickness of silicon coating 309 in said through hole 308 be first thickness, shown in Fig. 7 C;
S305, deposit bottom antireflective coating 310, the 3rd dielectric layer 311 and photoresistance 312 successively, said bottom antireflective coating 310 fills up and is not contained the part that silicon coating 309 is filled in the said through hole, and covers said second dielectric layer 306;
S306, said photoresistance 312 is graphical, definition interconnection channel figure is shown in Fig. 7 D;
S307, be mask, said the 3rd dielectric layer 311 carried out etching, until exposing said bottom antireflective coating 310, shown in Fig. 7 E with said patterned photoresistance 312; And remove patterned photoresistance 312;
S308, be mask, the said bottom antireflective coating 310 and second dielectric layer 306 carried out etching, until exposing said first dielectric layer 305, shown in Fig. 7 F with the 3rd dielectric layer 311 after the said etching; And remove the 3rd dielectric layer 311 after the said etching;
S309, be mask with second dielectric layer 306 after the said etching and the bottom antireflective coating 310 that is positioned on said second dielectric layer 306; Bottom antireflective coating 310 in said first dielectric layer 305 and the through hole carries out etching; Until exposing the said silicon coating 309 that contains; At this moment, be coated with remaining bottom antireflective coating 310 on second dielectric layer 306 after the said etching, shown in Fig. 7 G;
S310, be mask, feeding CF with second dielectric layer 306 after the said etching and bottom antireflective coating 310 4, N 2And under the condition of Ar to said first dielectric layer 305 and contain silicon coating 309 and carry out etching; Perhaps formerly feed CF 4, N 2And under the condition of Ar to said first dielectric layer 305 and contain silicon coating 309 etchings after a period of time, feeding CF again 4, N 2, Ar and C 4F 8Condition under to said first dielectric layer 305 and contain silicon coating 309 and carry out etching, form interconnection channel 301, at this moment, said through hole contains residue and contains silicon coating 309, shown in Fig. 7 H;
S311, the remaining bottom antireflective coating 310 of removal and the remaining silicon coating 309 that contains are shown in Fig. 7 I; And
S312, remove the etching barrier layer 304 under the said through hole, said through hole is contacted with said the first metal layer, concrete, said through hole is contacted, shown in Fig. 7 J with metal 303 in the said the first metal layer.
Further, the said silicon coating 309 that contains absorbs oxide or siliceous bottom antireflective coating for deep UV, thereby makes it at CF 4, N 2And can have high etching selection ratio under the condition of Ar.
Further, the scope of said first thickness is 500~2000 dusts, thereby makes the said silicon coating 309 that contains after forming interconnection channel, still have residue.
Further, said CF 4Flow be 50~500sccm, N 2Flow be 100~500sccm, the flow of Ar is 100~500sccm.
Further, said CF 4Flow be 50~500sccm, N 2Flow be 100~500sccm, the flow of Ar is 100~500sccm, C 4F 8Flow be 10~50sccm.
Further, the said remaining silicon coating that contains is removed through wet etching.
Further, said graphically is to realize through the immersion lithography technology with photoresistance.
Further, said etching barrier layer is the carborundum that silicon nitride or nitrogen mix.
Further, said first dielectric layer is a low dielectric coefficient medium layer.
Further, said low dielectric coefficient medium layer is the silicon dioxide or the cellular silicon dioxide of carbon dope.
Further, said second dielectric layer is a hard mask layer, and its material is tetraethyl orthosilicate (TEOS), and it act as after electro-coppering, copper is carried out shield in the process of CMP, prevents to damage first dielectric layer.
Further, said the 3rd dielectric layer is a cap rock, and its material is silicon dioxide or silicon nitride.
Please continue with reference to figure 8; The shape of double damask structure after electro-coppering that the method that Fig. 8 provides for the employing embodiment of the invention prepares; As shown in Figure 8, after the electro-coppering, semicircular structure is formed on the interconnection channel of this damascene structure bottom; The ratio of width x of distance y and interconnection channel bottom that is bottom to the via top of interconnection channel is 1, and wherein x is 200 dusts; And the angle of interconnection channel side and bottom is 88 degree.Thereby the top of satisfying through hole keeps vertical these two requirements with the side that radiused corners and interconnection channel are formed on the bottom of interconnection channel.
In a specific embodiment of the present invention, the flow of said Ar is 100~500sccm, yet should be realized that, because Ar mainly shields, its range of flow is wider, according to actual conditions, can also get other flow.
In sum, the invention provides a kind of method for preparing double damask structure, this method through in through hole earlier a deposition part contain silicon coating, deposit bottom antireflective coating again, carry out the interconnection channel etching afterwards, said when containing silicon coating when exposing, feed CF 4, N 2Reach Ar and continue etching, perhaps feed CF earlier 4, N 2Reach Ar and carry out etching, feed CF again 4, N 2, Ar and C 4F 8Continue etching; Because at CF 4, N 2And under the environment of Ar, the etching rate that contains silicon coating can reach 1.1 with the ratio of the etching rate of low dielectric coefficient medium layer, at CF 4, N 2, Ar and C 4F 8Environment under; The etching rate that contains silicon coating can reach 3 with the ratio of the etching rate of low dielectric coefficient medium layer, thereby when carrying out the interconnection channel etching, can very easily realize containing the over etching of silicon coating; Thereby help making the top of through hole and the bottom of interconnection channel to form radiused corners; And because the said required etch period weak point of over etching that contains silicon coating, thereby avoid damage is caused in the side of interconnection channel, make the side of interconnection channel keep vertical.
Obviously, those skilled in the art can carry out various changes and modification to invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.

Claims (12)

1. a method for preparing double damask structure is characterized in that, this method comprises the steps:
Semiconductor substrate is provided, wherein, has prepared required semiconductor device and the first metal layer on the said Semiconductor substrate;
Deposit etching barrier layer, first dielectric layer, second dielectric layer and photoresistance successively on said ground floor metal level, and said photoresistance is graphical, the definition via hole image;
With said patterned photoresistance is mask, and said first dielectric layer and second dielectric layer are carried out etching, forms through hole, and removes said patterned photoresistance;
Depositing silicon coating in said through hole, the said silicon coating that contains does not fill up said through hole, and the said thickness of silicon coating in said through hole that contains is first thickness;
Deposit bottom antireflective coating, the 3rd dielectric layer and photoresistance successively, said bottom antireflective coating fills up and is not contained the part that silicon coating is filled in the said through hole, and covers said second dielectric layer;
Said photoresistance is graphical, definition interconnection channel figure;
With said patterned photoresistance is mask, and said the 3rd dielectric layer is carried out etching, until exposing said bottom antireflective coating, and removes patterned photoresistance;
With the 3rd dielectric layer after the said etching is mask, and the said bottom antireflective coating and second dielectric layer are carried out etching, until exposing said first dielectric layer, and removes the 3rd dielectric layer after the said etching;
With second dielectric layer after the said etching and the bottom antireflective coating that is positioned on said second dielectric layer is mask; Bottom antireflective coating in said first dielectric layer and the through hole carries out etching; Until exposing the said silicon coating that contains; At this moment, be coated with remaining bottom antireflective coating on second dielectric layer after the said etching;
With second dielectric layer after the said etching and bottom antireflective coating is mask, is feeding CF 4, N 2And under the condition of Ar to said first dielectric layer and contain silicon coating and carry out etching; Perhaps formerly feed CF 4, N 2And under the condition of Ar to said first dielectric layer and after containing silicon coating etching a period of time, feeding CF again 4, N 2, Ar and C 4F 8Condition under to said first dielectric layer and contain silicon coating and carry out etching, form interconnection channel, at this moment, said through hole contains residue and contains silicon coating;
Remove remaining bottom antireflective coating and the remaining silicon coating that contains; And
Remove the etching barrier layer under the said through hole, said through hole is contacted with said the first metal layer.
2. the method for preparing double damask structure as claimed in claim 1 is characterized in that, the said silicon coating that contains is that deep UV absorbs oxide or siliceous bottom antireflective coating.
3. the method for preparing double damask structure as claimed in claim 1 is characterized in that, the scope of said first thickness is 500~2000 dusts.
4. the method for preparing double damask structure as claimed in claim 1 is characterized in that, said CF 4Flow be 50~500sccm, N 2Flow be 100~500sccm, the flow of Ar is 100~500sccm.
5. the method for preparing double damask structure as claimed in claim 1 is characterized in that, said CF 4Flow be 50~500sccm, N 2Flow be 100~500sccm, the flow of Ar is 100~500sccm, C 4F 8Flow be 10~50sccm.
6. the method for preparing double damask structure as claimed in claim 1 is characterized in that, the said remaining silicon coating that contains is removed through wet etching.
7. the method for preparing double damask structure as claimed in claim 1 is characterized in that, said graphically is to realize through the immersion lithography technology with photoresistance.
8. the method for preparing double damask structure as claimed in claim 1 is characterized in that, said etching barrier layer is the carborundum that silicon nitride or nitrogen mix.
9. the method for preparing double damask structure as claimed in claim 1 is characterized in that, said first dielectric layer is a low dielectric coefficient medium layer.
10. the method for preparing double damask structure as claimed in claim 9 is characterized in that, said low dielectric coefficient medium layer is the silicon dioxide or the cellular silicon dioxide of carbon dope.
11. the method for preparing double damask structure as claimed in claim 1 is characterized in that, said second dielectric layer is a hard mask layer, and its material is tetraethyl orthosilicate (TEOS).
12. the method for preparing double damask structure as claimed in claim 1 is characterized in that, said the 3rd dielectric layer is a cap rock, and its material is silicon dioxide or silicon nitride.
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