CN102324418A - 半导体元件封装结构与其制造方法 - Google Patents

半导体元件封装结构与其制造方法 Download PDF

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Publication number
CN102324418A
CN102324418A CN2011103188729A CN201110318872A CN102324418A CN 102324418 A CN102324418 A CN 102324418A CN 2011103188729 A CN2011103188729 A CN 2011103188729A CN 201110318872 A CN201110318872 A CN 201110318872A CN 102324418 A CN102324418 A CN 102324418A
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those
layer
semiconductor component
packaging structure
component packaging
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博纳德.K.艾皮特
凯.S.艾斯格
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Publication of CN102324418A publication Critical patent/CN102324418A/zh
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    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Abstract

本发明公开一种半导体元件封装结构与其制造方法。半导体元件封装结构至少包括管芯、重布线路层与电性连结至该重布线路层的多个导电柱。封装胶体部分包覆住该管芯与该些导电柱。该封装胶体上的多个内连线图案与该些导电柱电性连结，该些内连线图案提供电性连结至堆叠的第二个半导体封装。

Description

半导体元件封装结构与其制造方法
技术领域
本发明涉及一种半导体，且特别是涉及一种半导体组装与封装制作工艺。 
背景技术
目前所普遍采用的晶片级封装方式(Wafer level packaging；WLP)可大大地改善封装效率并降低半导体封装的尺寸。传统扇入(Fan-in)晶片级封装制作工艺是在未切割的晶片上进行，而使最终封装产品尺寸约与管芯大小差不多。而扇出(Fan-out)晶片级封装制作工艺则是利用重建晶片(Reconstitution wafer)，亦即是将各独立管芯重新排列成为人造模铸晶片，因此可减少使用昂贵覆晶基底的需求，以封装胶体扩大封装尺寸，以供更高输出/输入(Input/Output；I/O)端应用。 
而立体晶片级封装方式(3-D WLP)中堆叠的元件之间相当需要有效率并可靠电性连结。 
发明内容
为解决上述问题，本发明的一实施例提出一种半导体元件封装结构。该封装结构包含具有有源表面的一芯片。该封装结构更包含部分包覆该芯片且具有上表面的一封装胶体。该封装结构更包含一重布线路层，包括至少一导电层与至少一介电层。该重布线路层部分形成于该有源表面与部分形成于该封装胶体的下表面。该封装结构更包含多个导电柱位于该封装胶体内并电连接至该重布线路层。该封装结构更包含位于该封装胶体上表面的多个凹陷。该些凹陷的位置对应于该些导电柱的位置。该封装结构更包含多个内连线图案电连接至该些导电柱。该些内连线图案中的至少一个延伸至该些凹陷中的至少一个。 
本发明的另一实施例提出一种半导体元件封装结构。该封装结构包含具 有有源表面的一芯片。该封装结构更包含部分包覆该芯片且具有上表面的一封装胶体。该封装结构更包含一重布线路层，包括至少一导电层与至少一介电层。该重布线路层部分形成于该有源表面与部分形成于该封装胶体的下表面。该封装结构更包含多个导电柱位于该封装胶体内并电连接至该重布线路层。该封装结构更包含位于该封装胶体上表面的多个凹陷。该些凹陷的位置对应于该些导电柱的位置，且暴露出至少该些导电柱的上表面的至少一部分。该封装胶体叠盖住该些导电柱的上表面的边缘。 
本发明的另一实施例提出一种半导体元件封装结构制造方法。该方法包含形成多个导电柱位于一牺牲层上。该方法更包括安置至少一芯片于该牺牲层上。。该方法更包括形成一封装胶体于该牺牲层上，包覆该至少芯片并至少部分包覆该些导电柱。该方法更包括形成多个凹陷于该封装胶体中邻近该些导电柱的上表面。该方法更包括形成多个内连线图案于该封装胶体与该些导电柱上，该些内连线图案至少部分填入该封装胶体内的该些凹陷。。该方法更包括移除该牺牲层。该方法更包括形成一重布线路层于该芯片、该些导电柱与该封装胶体上。该重布线路层包括至少一导电层与至少一介电层。 
为让本发明的上述特征和优点能更明显易懂，下文特举实施例，并配合所附附图作详细说明如下。 
附图说明
图1是本发明的一实施例的一种晶片级封装结构剖面示意图； 
图2A是本发明的一实施例的一种堆叠封装结构剖面示意图； 
图2B是本发明的另一实施例的一种堆叠封装结构剖面示意图； 
图3A-图3H是本发明的一实施例的一种堆叠晶片级封装结构制造方法的剖面示意图； 
图4A-图4G是本发明的另一实施例的一种堆叠晶片级封装结构制造方法的剖面示意图； 
图5A-图5G是本发明的另一实施例的一种堆叠晶片级封装结构制造方法的剖面示意图； 
图6A-图6F是本发明的又一实施例的一种堆叠晶片级封装结构制造方法的剖面示意图； 
图7A-图7E是本发明的又一实施例的一种堆叠晶片级封装结构制造方 法的剖面示意图。 
主要元件符号说明 
10、22、24、26：封装结构 
20a、20b、20c：电子元件 
100：牺牲层 
102：胶带 
106：插柱 
109：接触垫 
110：芯片 
112a：内连线图案 
112b：导线图案 
113、115：介电层 
112、114：导电层 
114a：底内连线图案 
114b：底导线图案 
116：重布线路层 
130、130a：封装胶体 
106a、110a：上表面 
106b、110b、130b：下表面 
140：电性接点 
240：接点 
S：开口 
S1：凹陷 
A：芯片设置区 
具体实施方式
图1是描述依照本发明的一实施例的一种晶片级封装结构(WLP)10。封装结构10至少包括芯片(也称管芯)110、一封装胶体130包覆芯片110、多个插柱106埋于封装胶体130内、内连线图案(interconnect pattern)112a连接至该些柱106与导线图案(trace pattern)112b以及重布线路层(redistribution  layer；RDL)116。重布线路层116包括一第一介电层113、一导电层114与一第二介电层115。其他实施例中，重布线路层116可为单层结构(仅包括导电层114)。 
晶片级封装结构10可包括在内连线图案112a与封装胶体130间、内连线图案112a与该些柱106之间以及导线图案112b与封装胶体130间形成种层111。通过内连线图案112a，其上可堆叠其他半导体封装或堆叠不同电子元件于晶片级封装结构10之上，如后续所述。 
此外，晶片级封装结构10可更包括位于重布线路层116的导电层114上的电性接点(electrical contacts)140。电性接点140可为例如焊球来连接晶片级封装结构10至外接端如系统级电路板(未图示)。导电层114电连接芯片110的接触垫109与电性接点140或电连接该些柱106之一至电性接点140之一。在底面的导电层114图案化成为连接至该些柱106的底内连线图案114a与底导线图案114b。芯片110可为集成电路或任意半导体芯片如微电机系统(MEMS)。图1所示晶片级封装结构10仅包含两芯片，但也可理解本案的封装结构端视所需可包括任意数目(单一、二个、或多个)芯片。 
实施例中所述的该些插柱106为圆柱状的，但是其他实施例中该些插柱106也可为其他形状例如圆锥体状的。该些柱106可以任意导电材质如铜而制成。举例而言，相较于电镀插塞，实心铜柱可提供较优异的导电性。后续会被封装胶体130包覆且连接至内连线图案112a的该些插柱106的优点之一即是其深宽比(aspect ratio)变小，亦即插柱对应孔深/孔洞直径比变小。较低的深宽比可提高插柱无空洞或异变的可能性，也就是改善内连线的可靠度。 
图2A是依照本发明的一实施例的一种堆叠封装结构剖面示意图。图2A所示的堆叠封装结构22包括多个电子元件20a、20b、20c，堆叠在晶片级封装结构10之上。电子元件20a、20b、20c可为管芯、封装或其他元件如无源元件等，通过如覆晶技术、表面粘着式(SMT)或其他连结方式，堆叠在晶片级封装结构10之上。 
图2B是依照本发明的另一实施例的一种堆叠封装结构剖面示意图。图2B所示的堆叠封装结构24包括一封装结构26堆叠在晶片级封装结构10之上。封装结构26与封装结构10通过多个接点240而电性相连。此实施例中封装结构26可以是另一个晶片级封装结构而在底面具有扇出的重布线路层 (未显示)，而电性连结至封装结构10的上表面。 
图3A-图3H是依照本发明的一实施例的一种晶片级封装结构制造方法的剖面示意图。如图3A，先提供一牺牲层100，牺牲层100上表面上具有胶带102而胶带102上又覆盖光致抗蚀剂层104。牺牲层100、胶带102及光致抗蚀剂层104之下具有硬质载体100C用以支持其上各层。胶带102及光致抗蚀剂层104中形成有多个开口S。开口S可利用如：紫外光激光钻孔、二氧化碳激光钻孔或其他技术所形成。牺牲层100可为金属例如铜箔或其他金属箔。胶带102可为例如管芯粘接胶带。光致抗蚀剂层104可为如干膜式光致抗蚀剂层或其他光致抗蚀剂层。 
如图3B，在多个开口S中形成多个插柱106。该些插柱106可以电镀方式或其他方式形成。实施例中，该些插柱106可以例如图案电镀法所形成的金属例如铜所制得。实施例中，牺牲层100可作为阴极，以便于电镀形成插柱106于开口S中。 
如图3C，移除光致抗蚀剂层104后，至少一芯片(或管芯)110面朝下粘附至胶带102。芯片110包括至少一个接触垫109位于其朝下面(有源面)118上。此处芯片110指重建晶片的单一芯片或管芯，而芯片为从晶片中挑出并测试确定为好的芯片(Known good die；KGD)。管芯可能限于I/O垫数目而需要扇出以容纳较大的外界连接结构如锡球。或者，若完成应用端需要是立体封装则芯片110可不限于I/O垫数目。管芯不会置于已经发现插柱电镀缺陷的位置，因电镀缺陷会导致次佳电连接。光学检查可检出插柱106电镀的缺失、不完全或瑕疵。将好的芯片置于好的插柱即可增加封装良率。 
如图3D，模封牺牲层、胶带102与其上的芯片110而形成一封装胶体130覆盖住芯片110、该些插柱106、胶带102与牺牲层100。模封可包括压合模塑制作工艺(compression molding process)，可以减低或避免封装胶体130内含空隙的产生。 
于封装胶体130中形成多个凹陷S1，通过移除一部分的封装胶体130直至该些插柱106的表面106a露出而得到凹陷S1。移除过程可以钻孔步骤例如是紫外光激光钻孔或二氧化碳激光钻孔来进行。实施例中，凹陷S1的形状为倾斜渐缩的或锥状的，而上开口孔径121大于底开口孔径123。其他实施例中，凹陷S1的形状可为非倾斜渐缩的与/或孔径略小于该些柱106的直径以避免插柱106与封装胶体130之间有空隙。 
接着，如图3D，封装胶体130覆盖该些插柱106上表面106a的边缘。该些凹陷S1的形状为锥状的，而上开口较大孔径距离插柱106上表面106a较远，较小底开口孔径距离插柱106上表面106a较近。利用例如钻孔(drilling)步骤形成该些凹陷S1可导致此开口形状与封装胶体130覆盖该些插柱106的边缘。若激光没有对准插柱106，可能会不当地移除插柱106旁的封装胶体130，但以实施例的形状来形成凹陷S1可降低不当操作可能性。或者，也可研磨封装胶体130直至露出插柱上表面106a。 
如图3E，形成一种层111于封装胶体上表面上与凹陷S1中并覆盖插柱上表面106a。种层111可以溅镀或其他制作工艺制得，种层111的材质可为任意材质，也可为多层结构。例如：种层111为覆盖铜、镍或铬的钨层。接着，于种层111上形成一导电层112并电连接至该些柱106。导电层112可为金属如铜或铜合金，或其他金属。导电层112可以例如电镀或其他制作工艺制得。 
一般而言，视凹陷S1的深宽比而定，导电层112可完全填满或部分填入凹陷S1。较佳而言，导电层112至少电镀覆盖凹陷S1的侧壁并电连接至该些插柱106。位于凹陷S1内的导电层112作为插塞将封装结构底面的信号传至封装结构上面。 
如图3F，图案化导电层112而于封装胶体130上表面上形成布线层或导线图案112b以及电连接至金属柱106的内连线图案112a。该些图案可利用例如扣减式蚀刻(subtractive etching)或其他制作工艺形成。图案化导电层11之后，移除载体100C(图3E所示)。接着，移除在底面的牺牲层100与一部分的该些插柱106，直到该些插柱底面106b实质上与芯片底面110b齐平。移除过程可包括如蚀刻或其他步骤。或者，金属插塞106的底面106b可略略突出或凹陷于封装胶体130的下表面130b。接着，移除胶带102而暴露出该些插柱106与芯片底面110b，芯片110的接触垫109也暴露出来。 
另一实施例中，可选择性地移除牺牲层100，移除邻近该些插柱106的牺牲层100，直到该些插柱底面106b实质上齐平于或略略突出或凹陷于封装胶体130的下表面130b。然后，胜于的牺牲层100与胶带102一起移除，而暴露出该些插柱106与芯片底面110b。 
如图3G，形成一底导电层114覆盖住该些插柱106与芯片底面110b，其后可能需以清洁步骤清理。底导电层114材质可为金属如铜或铜合金，也 或其他材质。此实施例中，芯片110的接触垫109可为铜垫，其厚度需足够进行清洁与金属化步骤。 
如图3H，图案化底导电层114而形成电连接至该些柱106的底内连线图案114a以及底导线图案114b。上下表面上的导电层112、114可以利用双面制作工艺同时图案化，或依序分两次进行。导线图案112b与底导线图案114b可以相同或不同，端视产品设计。而内连线图案112a与底内连线图案114a的位置对应于该些柱106的位置。不过，视所搭配的芯片或元件，该些图案的设计或排列均可调整。 
之后，在前述上下金属图案112/114上，可形成抗锈层或表面加工层，例如是镍/金叠层、有机保焊剂(organic solderability preservatives，OSP)，或者材质可为化学镍钯浸金(electroless nickel electroless palladium immersion gold，ENEPIG)或化学镍金(electroless nickel immersion gold，ENIG)，以帮助增加连结。也可选择性地形成保护层如防焊层以保护前述上下金属图案，而仅有预定的接触垫露出以承载锡球。 
虽然根据前述实施例描述，该些柱可于单一步骤中图案电镀于铜箔上。薄箔可以是面板(四方)矩阵格式。一实施例中，可一次电镀两三片晶片再转至适当载体。显示面板是数倍大于印刷电路板，该些板材可承载晶片，显著增加插柱电镀效率。若以面板格式电镀，单一载体可承载两薄箔而同时电镀两薄箔，改善制造效能。 
在上述依序形成该些插柱106与导电层112的过程中，该些插柱的高度是依设计需求为适当合理高度，不暴露出芯片110或封装胶体130，特别是电镀过程中不将该些元件暴露于电镀化学反应中以避免该些元件被攻击。 
图4A-图4G是依照本发明的另一实施例的一种晶片级封装结构制造方法的剖面示意图。如图4A，先提供一牺牲层100，牺牲层100上表面上具有胶带102而胶带102上又具有至少一芯片110。形成光致抗蚀剂层104于该芯片110与胶带102上之后，在胶带102及光致抗蚀剂层104中形成多个开口S。开口S可利用前述实施例的技术所形成。一般而言，牺牲层100如前述实施例贴附至硬质载体100C上，但图示中为描述方便忽略未绘示出硬质载体100C。 
如图4B，于多个开口S中形成多个插柱106并位于牺牲层100上。虽然图示中该些插柱顶面106a实质上与芯片上表面110a齐平，但实际上该些 插柱106可略高于或矮于芯片110。然后，移除光致抗蚀剂层104。 
如图4C，模封牺牲层100、胶带102与其上的芯片110而形成一封装胶体130覆盖住芯片110、该些插柱106、胶带102与牺牲层100。接着，于封装胶体130中形成多个凹陷S1，通过移除一部分的封装胶体130直至该些插柱106的上表面106a露出而得到凹陷S1。移除过程可以包括进行前述实施例所述的技术。凹陷S1可为具有单一一致直径的开口，也可如图所示开口形状为锥状的。 
接着，如图4D，形成一种层111于封装胶体上表面上与凹陷S1中并覆盖插柱上表面106a。种层111可以溅镀或其他制作工艺制得，接着，于种层111上形成一导电层112并电连接至该些柱106。导电层112共形覆盖封装胶体130，但导电层112完全填满或部分填入凹陷S1。既然凹陷S1的深宽比较小，导电层112可完全填满凹陷S1。导电层112覆盖凹陷S1的侧壁并电连接至该些插柱106。 
如图4E，。蚀刻移除在底面的牺牲层100与一部分的该些插柱106，直到该些插柱底面106b实质上与芯片底面110b齐平。接着，移除胶带102而暴露出该些插柱106与芯片110的接触垫109。 
如图4F，形成一重布线路层116覆盖住该些插柱106底面106b与芯片底面110b。此处所述重布线路层116为多层，包括一第一介电层113、一导电层114与一第二介电层115。导电层114夹在第一介电层113与第二介电层115之间。重布线路层可帮助扇出芯片垫，以容纳具微细垫间间距(fine pad pitch)的芯片，也可内连至某些插柱106。重布线路层116的形成与标准晶片级封装制作工艺或制作工艺相关材料是相容的，而例示步骤描述于后。 
一实施例中，在重组晶片底面形成第一介电层113之后，在其中形成接触窗图案(via pattern)以连接插柱与芯片接触垫，接着固化第一介电层113。介电层113可以旋涂或其他制作工艺所形成。在介电层113上形成导电层114，图案化底导电层114而形成底内连线图案114a以及底导线图案114b。底内连线图案114a以及底导线图案114b扇出芯片接触垫109并且设计为内连接插柱106与芯片接触垫109。 
举例而言，至少介电层113或115之一者材质可以是聚乙酰胺(polyimide)、聚苯并恶唑(polybenzoxazole)、苯并环丁烯(benzocyclobutene)、其组合或其他材质。介电层113或115可以相同或不同介电材料所形成。一 实施例中，底导线图案114b连接芯片接触垫109。底内连线图案114a可电连接芯片接触垫109与插柱106或仅连接插柱106。底内连线图案114a可用以扇出芯片接触垫109或用以帮助连接外部连结。 
如图4G，在第二介电层115的开口S2中形成电性接点(electrical contacts)140，电性接点140电性连结至底内连线图案114a。电性接点140可为例如锡球、金扣柱(gold stud)或铜柱或其他适当电性接点。此外，第二介电层115还可具有凸块下金属化层(under-bump metallization，UBM)以强化与电性接点的粘着。导电层112图案化为连接至插柱106的内连线图案112a与导线图案112b。 
图5A-图5G是依照本发明的另一实施例的一种晶片级封装结构制造方法的剖面示意图。如图5A，先提供一牺牲层100，牺牲层100上具有胶带102而胶带102上又具有至少一芯片110。一般而言，牺牲层100如前述实施例贴附至硬质载体100C上，但图示中为描述方便忽略未绘示出硬质载体100C。 
如图5B，模封牺牲层100、胶带102与其上的芯片110而形成一封装胶体130覆盖住芯片110、胶带102与牺牲层100。 
如图5C，接着，在封装胶体130中形成多个开口S，移除过程可以包括进行前述实施例所述的技术。开口S可为具有单一一致直径的开口、渐缩形状的开口或两者组合。若开口S以激光钻孔形成，因封装胶体130颗粒会阻碍激光会使其表面132粗糙。粗糙表面比平滑表面难以电镀。因此，较佳是先形成插柱106再形成封装胶体130围绕插柱106，如图3A-图3H与图4A-图4G所示。 
如图5D，形成一种层111于封装胶体130上表面上与开口S中并覆盖开口内表面。种层111可以前述实施例中任意相关制作工艺制得，接着，于种层111上形成一导电层112。导电层112覆盖封装胶体130，但导电层112完全填满或部分填入开口S。既然开口S的深宽比较小，导电层112可完全填满开口S。导电层112填充于开口S内的部分可视为插柱部分112c。导电层112较佳是完全覆盖开口S的侧壁与底部。此实施例中，单一形成导电层112的步骤取代了前述实施例中分开形成插柱106与导电层的步骤。 
如图5E，移除在底面的牺牲层100与一部分的插柱部分112c，直到插柱部分112c的底面113实质上与芯片底面110b齐平。该移除步骤可以前述 实施例的技术进行。接着，移除胶带102而暴露出插柱部分112c与芯片110的底面110b。 
如图5F，形成一底导电层114覆盖住插柱部分112c与芯片110的底面110b。导电层112或底导电层114材质可包括前述实施例的金属或其他材质。 
如图5G，图案化导电层112为布线或导线图案112b与内连线图案112a(包括插柱部分112c)。图案化底导电层114而形成电连接至插柱部分112c的底内连线图案114a以及底导线图案114b。 
图6A-图6F是依照本发明的另一实施例的一种晶片级封装结构制造方法的剖面示意图。如图6A，先提供一牺牲层100，牺牲层100上具有多个插柱106，而牺牲层100通过胶带102贴附至硬质载体100C上。部分移除牺牲层100而定义出一芯片安置区A，至少一芯片位于胶带102上并位于芯片安置区A内。芯片安置区可利用选择性蚀刻或其他制作工艺制得。 
如图6B，模封牺牲层100与其上的芯片110而形成一封装胶体130覆盖住芯片110、该些插柱106与牺牲层100，并位于胶带102之上。接着，于封装胶体130中形成多个凹陷S1，通过移除一部分的封装胶体130直至该些插柱106露出而得到凹陷S1。凹陷S1可为具有单一一致直径的开口，也可如图所示开口形状为锥状的。 
接着，如图6C，形成一种层111于封装胶体上表面上与凹陷S1中并覆盖插柱上表面106a。接着，在种层111上形成一导电层112并电连接至该些柱106。导电层112共形覆盖封装胶体130，但导电层112完全填满或部分填入凹陷S1。既然凹陷S1的深宽比较小，导电层112可完全填满凹陷S1。导电层112覆盖凹陷S1的侧壁并电连接至该些插柱106。 
如图6D，移除硬质载体100C与胶带102。移除在底面的牺牲层100与一部分的该些插柱106。移除步骤可以前述技术进行。因牺牲层100相当薄，可忽视芯片底面110b与封装胶体130底面的高度差不计。芯片底面110b与封装胶体130底面的高度差异绘示与实际比例不同。 
如图6E，形成一底导电层114覆盖住插柱106与芯片110的底面110b。 
如图6F，图案化导电层112为布线或导线图案112b与连接插柱106的内连线图案112a。图案化底导电层114而形成电连接至插柱106的底内连线图案114a以及底导线图案114b。 
图7A-图7F是依照本发明的另一实施例的一种晶片级封装结构制造方 法的剖面示意图。如图7A，先提供一牺牲层100，牺牲层100上具有多个插柱106，而牺牲层100与该些插柱106位于胶带102上。部分移除牺牲层100而定义出一芯片安置区A，至少一芯片位于胶带102上并位于芯片安置区A内。芯片安置区可利用选择性蚀刻或其他制作工艺制得。该些插柱106的顶面106a高于芯片110的顶面110a。一般而言，牺牲层100贴附于硬质载体100C，但图示描述中省略。 
如图7B，模封牺牲层100与其上的芯片110而形成一封装胶体130覆盖住芯片110、该些插柱106与牺牲层100，并位于胶带102之上。 
如图7C，接着，从上面移除封装胶体130的部分薄化封装胶体130，直至该些插柱106的表面106a露出。该移除步骤可包括研磨或其他步骤。此实施例中的插柱106可视为贯穿封装胶体的插塞。薄化的封装胶体130a的厚度厚于芯片，方能提供管芯与后续形成导线图案间的背面绝缘。 
如图7D，移除胶带102而露出牺牲层100。移除在底面的牺牲层100，移除步骤可以前述技术进行。分别形成导电层112、114覆盖薄化的封装胶体130a的顶面、底面。 
如图7E，图案化导电层112为布线或导线图案112b与连接插柱106的内连线图案112a。图案化底导电层114而形成电连接至插柱106的底内连线图案114a以及底导线图案114b。。 
之后，在前述上下金属图案112/114上，可形成抗锈层或表面加工层，例如是镍/金叠层、有机保焊剂(OSP)，或者材质可为化学镍钯浸金(ENEPIG)或化学镍金(ENIG)，以帮助增加连结。也可选择性地形成防焊层以保护前述上下金属图案。 
另一实施例中，类似图7C中薄化封装胶体130的步骤可持续进行直到芯片110背面与插柱106上部从薄化的封装胶体130a暴露出来。可额外形成一介电覆盖层(未绘示)于封装胶体130a上与芯片110背面上，但不覆盖插柱106，然后再形成导电层112于介电覆盖层与该些插柱106上。 
其他实施例中，可使用多层重布线路层来取代前述实施例的底面金属图案，以便将小间距芯片垫扇出或重布高密度导线线路。 
由前述实施例可知，晶片级封装结构可提供安装于其上的元件或下一级基板直接电性连结。亦即，本发明的晶片级封装结构可直接电性连结安装于其两面的元件。因此，本案的晶片级封装结构适合用于立体晶片级封装，而  堆叠封装尺寸颇小。本发明的晶片级封装结构可在双面设置重布线路图案，以堆叠不同种类或尺寸封装结构，提供产品设计弹性。 
本案实施例中电镀该些插柱106的电镀制作工艺可有效调整最佳化电镀化学反应与配方程式，以电镀形成该些柱106而不电镀封装胶体130上表面/种层111。另一方面，贯穿胶体的接触窗电镀较为复杂，因电镀多会发生于接触窗孔，但少数电镀仍会发生于封装胶体130上表面/种层111。因此，此种电镀所应用的电镀化学反应与配方程式也不相同。电镀表面可能需要平坦化以便移除过度电镀区域，亦即不均匀处。此一步骤可能会导致插柱106缺陷，例如电镀包含物或空隙的产生。 
前述实施例中重布线路层仅设置于封装结构底侧(芯片侧)，但重布线路层可以设置于封装结构两面以达到最高导线密度解析度。此外，虽然只显示单一层的重布线路层，但不同实施例中可视设计使用多层重布线路层。 
虽然结合以上实施例揭露了本发明，然而其并非用以限定本发明，任何所属技术领域中熟悉此技术者，在不脱离本发明的精神和范围内，可作些许的更动与润饰，故本发明的保护范围应以附上的权利要求所界定的为准。 

Claims (20)

1.一种半导体元件封装结构，包含：
芯片，其具有一有源表面；
封装胶体，部分包覆该芯片且具有一上表面；
重布线路层，包括至少一导电层与至少一介电层，其中该重布线路层部分形成于该有源表面与部分形成于该封装胶体的一下表面；
多个导电柱位于该封装胶体内并电连接至该重布线路层；
多个凹陷，位于该封装胶体的该上表面，其中该些凹陷的位置对应于该些导电柱的位置；以及
多个内连线图案，电连接至该些导电柱，而该些内连线图案中的至少一个延伸至该些凹陷中的至少一个。
2.如权利要求1所述的半导体元件封装结构，还包括种层，位于该封装胶体与该些内连线图案之间。
3.如权利要求1所述的半导体元件封装结构，其中该些凹陷为锥状。
4.如权利要求3所述的半导体元件封装结构，其中该些凹陷在远离该些导电柱的位置的直径大于邻近该些导电柱的位置的直径。
5.如权利要求1所述的半导体元件封装结构，其中该封装胶体叠盖住该些导电柱的上表面的边缘。
6.如权利要求1所述的半导体元件封装结构，其中该重布线路层包括导电层，介于一上介电层与一下介电层之间。
7.如权利要求1所述的半导体元件封装结构，其中该半导体元件封装结构为第一半导体元件封装结构，还包括第二半导体元件封装结构，堆叠于该第一半导体元件封装结构上。
8.一种半导体元件封装结构，包含：
芯片，其具有有源表面；
封装胶体，部分包覆该芯片且具有上表面；
重布线路层，包括至少一导电层与至少一介电层，其中该重布线路层部分形成于该有源表面与部分形成于该封装胶体的一下表面；
多个导电柱位于该封装胶体内并电连接至该重布线路层；以及
多个凹陷，位于该封装胶体的该上表面，其中该些凹陷的位置对应于该些导电柱的位置，且暴露出至少该些导电柱的上表面的至少一部分，
其中该封装胶体叠盖住该些导电柱的上表面的边缘。
9.如权利要求8所述的半导体元件封装结构，还包括多个内连线图案位于该封装胶体与该些导电柱上，该些内连线图案至少部分填入该封装胶体的该些凹陷。
10.如权利要求9所述的半导体元件封装结构，还包括种层，位于该封装胶体与该些内连线图案之间。
11.如权利要求8所述的半导体元件封装结构，其中该些凹陷为锥状。
12.如权利要求11所述的半导体元件封装结构，其中该些凹陷在远离该些导电柱的位置的直径大于邻近该些导电柱的位置的直径。
13.如权利要求8所述的半导体元件封装结构，其中该重布线路层包括导电层，介于一上介电层与一下介电层之间。
14.如权利要求8所述的半导体元件封装结构，其中该半导体元件封装结构为第一半导体元件封装结构，还包括第二半导体元件封装结构堆叠于该第一半导体元件封装结构上。
15.一种半导体元件封装结构制造方法，包含：
形成多个导电柱位于一牺牲层上；
安置至少一芯片于该牺牲层上；
形成一封装胶体于该牺牲层上，包覆该至少芯片并至少部分包覆该些导电柱；
形成多个凹陷于该封装胶体中邻近该些导电柱的上表面；
形成多个内连线图案于该封装胶体与该些导电柱上，该些内连线图案至少部分填入该封装胶体内的该些凹陷；
移除该牺牲层；以及
形成一重布线路层于该芯片、该些导电柱与该封装胶体上，该重布线路层包括至少一导电层与至少一介电层。
16.如权利要求15所述的半导体元件封装结构制造方法，其中形成该些凹陷的步骤还包括进行一激光钻孔制作工艺。
17.如权利要求15所述的半导体元件封装结构制造方法，还包括形成一种层于该封装胶体之上并至少部分填入于该些凹陷。
18.如权利要求15所述的半导体元件封装结构制造方法，其中该些凹陷为锥状。
19.如权利要求18所述的半导体元件封装结构制造方法，其中该些凹陷在远离该些导电柱的位置的直径大于邻近该些导电柱的位置的直径。
20.如权利要求15所述的半导体元件封装结构制造方法，其中该重布线路层包括导电层，夹于一上介电层与一下介电层之间。
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