CN102315131A - Manufacturing method of transistor - Google Patents
Manufacturing method of transistor Download PDFInfo
- Publication number
- CN102315131A CN102315131A CN201110300269A CN201110300269A CN102315131A CN 102315131 A CN102315131 A CN 102315131A CN 201110300269 A CN201110300269 A CN 201110300269A CN 201110300269 A CN201110300269 A CN 201110300269A CN 102315131 A CN102315131 A CN 102315131A
- Authority
- CN
- China
- Prior art keywords
- ion
- source
- light dope
- transistor
- region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention relates to a manufacturing method of a transistor, which comprises the following steps of: providing a semiconductor substrate; sequentially forming a grid-electrode structure and a lateral wall positioned on the lateral surface of the grid-electrode structure on the semiconductor substrate; forming a patterned photoresist layer on the semiconductor substrate; by using the photoresist layer, the grid-electrode structure and the lateral wall as masks, carrying out lightly-doped ion injection in the semiconductor substrate to form a source/drain extension area; and by using the photoresist layer, the grid-electrode structure and the lateral wall as the masks, carrying out heavily-doped ion injection in the source/drain extension area to form a source/drain area. Through the manufacturing method of the transistor, the steps can be simplified, and the production cost is saved.
Description
Technical field
The present invention relates to technical field of semiconductors, relate in particular to a kind of transistorized manufacture method.
Background technology
In semiconductor device; Lightly doped drain (Lightly Doped Drain, LDD) structure is that MOS (Metal Oxide Semiconductor, metal-oxide semiconductor (MOS)) transistor is in order to weaken the drain region electric field; To overcome a kind of structure that hot current-carrying effect (Hot carrier effect) is taked; Promptly in raceway groove, near draining, a low-doped drain extension region is set, lets this low-doped drain extension region also bear part voltage, thereby prevent hot current-carrying effect.Therefore, generally all to form the LDD structure in the existing MOS transistor manufacture craft.
Below (Laterally Diffused Metal Oxide Semiconductor, LDMOS) the transistorized example that is made as is explained the transistorized manufacturing process that comprises the LDD structure in the prior art with LDMOS.
With reference to shown in Figure 1, the Semiconductor substrate 10 of P type is provided;
With reference to shown in Figure 2, in said Semiconductor substrate 10, form the high-pressure trap area 11 of P type;
With reference to shown in Figure 3, in said high-pressure trap area 11, form the drift region 13 of the body 12 and the N type of P type, said body 12 links to each other with said drift region 13, and the degree of depth of said drift region 13 is greater than the degree of depth of said body 12;
With reference to shown in Figure 4, in said body 12 and drift region 13, form fleet plough groove isolation structure 14 respectively, wherein the region deviding between two fleet plough groove isolation structures 14 in said drift region 13 drain region;
With reference to shown in Figure 5, on said Semiconductor substrate 10, form grid structure, said grid structure comprises gate dielectric layer 15 and grid 16;
With reference to shown in Figure 6, on said Semiconductor substrate 10, form first photoresist 23 of patterning, be that mask carries out the injection of light dope ion with said first photoresist 23 and said grid structure;
With reference to shown in Figure 7, in body 12, form N type source extension area 17, and in drift region 13, form N type drain extension region 18, said source extension area 17 is formed the LDD structure with drain extension region 18, and removes said first photoresist 23;
With reference to shown in Figure 8, around said grid structure, form side wall 19;
With reference to shown in Figure 9, on said Semiconductor substrate 10, form second photoresist 24 of patterning, be that mask carries out heavy doping ion and injects with said second photoresist 24, said grid structure and said side wall 19;
With reference to shown in Figure 10, in source extension area 17, form the source region 20 of N type, and in drain extension region 18, form the drain region 21 of N type, and remove said second photoresist 24;
With reference to shown in Figure 11, in said body 12, form the body draw-out area 22 of P type.
So far, obtain comprising the N type ldmos transistor of LDD structure.
Under the identical prerequisite of drain width; Relatively comprise the ldmos transistor of LDD structure and do not comprise the resistivity of the ldmos transistor of LDD structure; With reference to shown in Figure 12; Can find: the drain resistance rate of ldmos transistor that comprises the LDD structure is smaller, comprises that promptly the series resistance of ldmos transistor drain electrode of LDD structure is smaller.
But in above-mentioned manufacturing process,, need to form earlier first photoresist 23 of patterning, remove said first photoresist 23 after source/drain extension region to be formed in order to obtain source/drain extension region and source/drain region; Form side wall 19 then; Form second photoresist 24 of patterning again, remove said second photoresist 24 after source/drain region to be formed, said first photoresist 23 is basic identical with said second photoresist 24.Thereby the making step more complicated, the production cost of ldmos transistor is than higher.
Similarly, comprise in the manufacturing process of metal-oxide-semiconductor of LDD structure,, also need successively carry out for twice the formation of photoresist and remove step in order to obtain source/drain extension region and source/drain region at other.
Therefore, how to comprise in the metal-oxide-semiconductor of LDD structure that reduce making step, reducing production costs just becomes those skilled in the art's problem demanding prompt solution in making.
Summary of the invention
The problem that the present invention solves provides a kind of transistorized manufacture method, to simplify step, saves production cost.
For addressing the above problem, the invention provides a kind of transistorized manufacture method, comprising:
Semiconductor substrate is provided;
On said Semiconductor substrate, form grid structure and the side wall that is positioned at said grid structure side successively;
On said Semiconductor substrate, form the photoresist layer of patterning;
With said photoresist layer, grid structure and side wall is mask, in said Semiconductor substrate, carries out the light dope ion and injects formation source/drain extension region;
With said photoresist layer, grid structure and side wall is mask, in said source/drain extension region, carries out heavy doping ion and injects formation source/drain region.
Alternatively, said transistor is a ldmos transistor.
Alternatively, said transistor is CMOS (Complementary Metal-Oxide-Semiconductor Transistor, a complementary metal oxide semiconductors (CMOS)) transistor.
Alternatively, said transistorized source region and drain region are unsymmetric structure.
Alternatively, said transistorized manufacture method also comprises: form after said source/drain extension region, carry out annealing in process.
Alternatively, said transistorized manufacture method also comprises: form after said source/drain region, carry out annealing in process.
Alternatively, said transistor comprises the body draw-out area, and said manufacture method also comprises: after forming said source/drain region, and the organizator draw-out area; After forming said body draw-out area, carry out annealing in process.
Alternatively, said transistor is the N type, and said light dope ion is a phosphonium ion; The energy range that said light dope ion injects comprises 50keV～100keV, and the dosage range that said light dope ion injects comprises 1E13/cm
2～1E14/cm
2
Alternatively, said transistor is the N type, and said light dope ion is an arsenic ion; The energy range that said light dope ion injects comprises 90keV～200keV, and the dosage range that said light dope ion injects comprises 1E13/cm
2～1E14/cm
2
Alternatively, said transistor is the P type, and said light dope ion is the boron ion; The energy range that said light dope ion injects comprises 12keV～35keV, and the dosage range that said light dope ion injects comprises 1E13/cm
2～1E14/cm
2
Alternatively, said transistor is the P type, and said light dope ion is an indium ion; The energy range that said light dope ion injects comprises 80keV～300keV, and the dosage range that said light dope ion injects comprises 1E13/cm
2～1E14/cm
2
Compared with prior art, the present invention has the following advantages: after forming grid structure, form side wall earlier; Then forming the photoresist layer of patterning, is mask with said photoresist layer, grid structure and side wall respectively, successively carries out injection of light dope ion and heavy doping ion and injects; Form source/drain extension region and source/drain region successively; Thereby save the formation of a photoresist layer and removed step, simplified transistorized making step, finally reduced transistorized production cost.
Description of drawings
Fig. 1 to Figure 11 is the transistorized manufacturing process sketch map that comprises the LDD structure in the prior art;
Figure 12 is the drain resistance rate-drain width sketch map that comprises the LDD structure and do not comprise the ldmos transistor of LDD structure;
Figure 13 is the schematic flow sheet of the transistorized manufacture method of embodiment of the present invention;
Figure 14 to Figure 22 is the sketch map of the manufacture method of the embodiment of the invention one ldmos transistor;
Figure 23 to Figure 29 is the sketch map of the manufacture method of the embodiment of the invention two ldmos transistors;
Figure 30 is the sketch map of the manufacture method of the embodiment of the invention three nmos pass transistors.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Set forth a lot of details in the following description so that make much of the present invention, implement but the present invention can also adopt other to be different from alternate manner described here, so the present invention has not received the restriction of following disclosed specific embodiment.
Said as the background technology part; Prior art comprises in the transistorized process of LDD structure in making; For formation source/drain extension region and source/drain region, need the photoresist of twice essentially identical patterning of formation successively, promptly need carry out twice essentially identical lithography step.In order to simplify making step and to reduce production costs, the invention provides a kind of transistorized manufacture method, form side wall earlier; Then form the photoresist layer of patterning; Be mask with said photoresist layer respectively, successively carry out injection of light dope ion and heavy doping ion and inject, form source/drain extension region and source/drain region successively; Thereby save the formation of a photoresist layer and removed step, promptly save lithography step one time.
With reference to shown in Figure 13, the manufacture method of semiconductor device provided by the invention comprises:
Step S1 provides Semiconductor substrate;
Step S2 forms grid structure and the side wall that is positioned at said grid structure side successively on said Semiconductor substrate;
Step S3, the photoresist layer of formation patterning on said Semiconductor substrate;
Step S4 is a mask with said photoresist layer, grid structure and side wall, in said Semiconductor substrate, carries out the light dope ion and injects formation source/drain extension region;
Step S5 is a mask with said photoresist layer, grid structure and side wall, in said source/drain extension region, carries out heavy doping ion and injects formation source/drain region.
Be elaborated below in conjunction with accompanying drawing.
Embodiment one
Present embodiment is an example to make N type ldmos transistor, and the manufacture method of ldmos transistor specifically may further comprise the steps.
At first, with reference to shown in Figure 14, Semiconductor substrate 100 is provided.
The material of said Semiconductor substrate 100 can for silicon, germanium silicon or silicon-on-insulator (Silicon-On-Insulator, SOI) etc.In the present embodiment, the silicon substrate that the material of said Semiconductor substrate 100 mixes for the P type.
Comprise in the said Semiconductor substrate 100:
High-pressure trap area 110;
Be positioned at the body 120 and drift region 130 of said high-pressure trap area 110, said body 120 links to each other with said drift region 130, and the degree of depth of said drift region 130 is greater than the degree of depth of said body 120;
Be positioned at a plurality of fleet plough groove isolation structures 140 of said body 120 and said drift region 130.
Wherein, said high-pressure trap area 110, body 120, drift region 130 can form through in Semiconductor substrate 100, carrying out the mode that ion injects, and said high-pressure trap area 110 is the P type with body 120 and mixes, and said drift region 130 is the doping of N type.
Wherein, the region deviding between two fleet plough groove isolation structures 140 in said drift region 130 is the drain region.
Particularly, the dopant ion of said P type doping can be boron ion or indium ion etc.; The dopant ion that said N type mixes can be phosphonium ion or arsenic ion etc.
Then, with reference to shown in Figure 15, on said Semiconductor substrate 100, form grid structure, said grid structure comprises gate dielectric layer 150 and grid 160.
The formation method of said grid structure is known for those skilled in the art, so repeat no more at this.For example: the material of said gate dielectric layer 150 can be silica, and the material of said grid 160 can be polysilicon.
Then, with reference to shown in Figure 16, form side wall 170 in the side of said grid structure.
The material of said side wall 170 can be in silica, silicon nitride, the silicon oxynitride a kind of or they make up arbitrarily, it specifically forms technology knows for those skilled in the art, so repeat no more at this.
Then, with reference to shown in Figure 17, on said Semiconductor substrate 100, form the photoresist layer 180 of patterning.Particularly, the upper surface in structure shown in Figure 16 applies photoresist earlier, forms structure shown in Figure 17 through photoetching processes such as exposure and developments then.
Wherein, the photoresist layer 180 that is positioned at said body 120 upper surfaces has defined the zone of the body draw-out area of follow-up formation.Said photoresist layer 180, fleet plough groove isolation structure 140, grid structure and side wall 170 have defined source region and drain region jointly.Preferably; Said source region and drain region are not the center symmetry with the grid structure; Thereby the source/drain region that has guaranteed follow-up formation is a unsymmetric structure; Be the drain region away from grid structure, so the existence of side wall 170 can not impact drain extension region, finally can guarantee the drain electrode stable performance of semiconductor device.
The photoresist layer of the patterning that forms during formation source in the photoresist layer 180 that this step forms and the prior art/drain region is identical, so repeat no more at this.
Then, with reference to shown in Figure 180, be mask with said photoresist layer 180, grid structure and side wall 170, in said body 120 and said drift region 130, carry out the light dope ion respectively and inject.
Carry out N type light dope ion in the present embodiment and inject, to form N type source/drain extension region.Because formed side wall 170 this moment, and the source extension area need be formed in the corresponding Semiconductor substrate 100 of side wall 170 lower surfaces, so part light dope ion need pass the side wall 170 of a side, to form the source extension area.
In an example; In said body 120 and said drift region 130, inject phosphonium ion respectively; Vertical plane with the vertical semiconductor devices surface is a benchmark; The angle that ion injects can and be less than or equal to 45 degree greater than 0 degree, and the energy range that ion injects can be 50keV～100keV, and the dosage range that ion injects can be 1E13/cm
2～1E14/cm
2Thereby, form source extension area shown in Figure 19 210 and drain extension region 220.
In another example; In said body 120 and said drift region 130, inject arsenic ion respectively; Vertical plane with the vertical semiconductor devices surface is a benchmark; The angle that ion injects can and be less than or equal to 45 degree greater than 0 degree, and the energy range that ion injects can be 90keV～200keV, and the dosage range that ion injects can be 1E13/cm
2～1E14/cm
2Thereby, form source extension area shown in Figure 19 210 and drain extension region 220.
In addition, after formation source/drain extension region, can also carry out annealing in process, as: quick sharp cutting edge of a knife or a sword annealing process (RTA), with the dopant ion in activation of source/drain extension region.
Then, with reference to shown in Figure 20, be mask with said photoresist layer 180, grid structure and side wall 170, in said source extension area 210 and drain extension region 220, carry out heavy doping ion respectively and inject.
Carry out N type heavy doping ion in the present embodiment and inject, to form N type source/drain region.The method that present embodiment forms source/drain region is identical with prior art; Be that the present invention can not change the parameters such as ion implantation angle, ion implantation energy and ion implantation dosage in the heavy doping ion injection process; In said source extension area 210 and said drain extension region 220, inject phosphonium ion or arsenic ion respectively, thereby form source region shown in Figure 21 230 and drain region 240.
After formation source/drain region, just can remove said photoresist layer 180.
Wherein, removing said photoresist layer 180 can adopt the method for ashing to realize that can adopt other known photoresist removal methods in the prior art, it should not limit protection scope of the present invention at this yet.
Then, with reference to shown in Figure 22, organizator draw-out area 250 in said body 120.
Particularly, said body draw-out area 250 can form through in body 120, injecting P type dopant ion, and it is known for those skilled in the art, so repeat no more at this.
After organizator draw-out area 250, can also carry out annealing in process, to activate the dopant ion in source region 230, drain region 240 and the body draw-out area 250.
Need to prove; In other embodiments of the invention; After formation source/drain extension region, can not carry out annealing in process, but after organizator draw-out area 250; Carry out annealing in process, with the dopant ion in while activation of source extension area 210, drain extension region 220, source region 230, drain region 240 and the body draw-out area 250.
So far, obtain ldmos transistor shown in Figure 22.
In other embodiments, when forming P type ldmos transistor, said light dope ion can be the boron ion, and at this moment, the energy range that ion injects can comprise 12keV～35keV, and the ion implantation dosage scope can comprise 1E13/cm
2～1E14/cm
2, the angle that ion injects can and be less than or equal to 45 degree greater than 0 degree; Said light dope ion can also be an indium ion, and at this moment, the energy range that ion injects can comprise 80keV～300keV, and the ion implantation dosage scope can comprise 1E13/cm
2～1E14/cm
2, the angular range that ion injects can and be less than or equal to 45 degree greater than 0 degree.
Embodiment two
Present embodiment provides the manufacture method of another kind of ldmos transistor, mainly comprises:
With reference to shown in Figure 23, Semiconductor substrate 100 is provided, comprise in the said Semiconductor substrate 100: body 120 and drift region 130, said body 120 links to each other with said drift region 130, and the degree of depth of said drift region 130 equals the degree of depth of said body 120;
With reference to shown in Figure 24, on said Semiconductor substrate 100, form grid structure and be positioned at said grid structure side wall 170 on every side, said grid structure comprises the gate dielectric layer 150 and grid 160 that is positioned on the said Semiconductor substrate 100 successively;
With reference to shown in Figure 25, on said Semiconductor substrate 100, form the photoresist layer 280 of patterning;
With reference to shown in Figure 26, be mask with said photoresist layer 280, grid structure and side wall 170, in said body 120 and said drift region 130, carry out the light dope ion respectively and inject, form source extension area 210 and drain extension region 220;
With reference to shown in Figure 27, be mask with said photoresist layer 280, grid structure and side wall 170, in said source extension area 210 and drain extension region 220, carry out heavy doping ion respectively and inject, form source region 230 and drain region 240;
With reference to shown in Figure 28, remove said photoresist layer 280;
With reference to shown in Figure 29, organizator draw-out area 250 in said body 120.
Present embodiment can carry out annealing in process after formation source/drain region extension area or after formation source/drain region or after the organizator draw-out area 250.
The difference of the ldmos transistor that ldmos transistor that present embodiment is made and embodiment one make is: all do not comprise fleet plough groove isolation structure in body described in the present embodiment 120 and the said drift region 130; Therefore after the photoresist layer 280 that forms patterning, 250 zones, body draw-out area, 230 zones, source region and 240 zones, drain region have been exposed; And 230 zones, said source region and 240 zones, said drain region are asymmetric.
But the relevant parameter reference implementation that the light dope ion injects and heavy doping ion is injected in present embodiment example one.
Present embodiment forms side wall 170 earlier; Then forming the photoresist layer 280 of patterning, is mask with said photoresist layer 280, grid structure and side wall 170 respectively, successively carries out the light dope ion and injects and the heavy doping ion injection; Form source/drain extension region and source/drain region successively; Thereby save the formation of a photoresist layer and removed step, simplified the making step of the ldmos transistor that comprises the LDD structure, finally reduced transistorized production cost.
Need to prove; Can also adopt the method for present embodiment to make the ldmos transistor of other structures; It can only form photoresist layer one time, can be mask with photoresist layer, grid structure and side wall just, carries out injection of light dope ion and heavy doping ion successively and injects; Thereby formation source/drain extension region and source/drain region, so should not limit protection scope of the present invention at this.
Embodiment three
A kind of manufacture method of nmos pass transistor is provided in the present embodiment, and said nmos pass transistor is shown in figure 30, and said method mainly comprises:
The Semiconductor substrate 300 of P type is provided, and said Semiconductor substrate 300 comprises: P type potential well 310 and a plurality of fleet plough groove isolation structures 320, the region deviding between the said fleet plough groove isolation structure 320 of part the drain region;
On said Semiconductor substrate 300, form grid structure, said grid structure comprises: gate dielectric layer 330 and grid 340;
Relative both sides at said grid structure form side wall 350;
On said Semiconductor substrate 300, form photoresist layer;
With said photoresist layer, grid structure and side wall 350 is mask, in said Semiconductor substrate 300, carries out the light dope ion and injects, and forms N type source extension area 360 and N type drain extension region;
With said photoresist layer, grid structure and side wall 350 is mask; In said N type source extension area 360 and N type drain extension region, carrying out heavy doping ion injects; In N type source extension area 360, form N type source region 380, and in N type drain extension region, form N type drain region 390.
Present embodiment can carry out annealing in process after formation source/drain extension region or after formation source/drain region.
Present embodiment forms side wall 350 earlier; Then forming the photoresist layer of patterning, is mask with said photoresist layer, grid structure and side wall 350 respectively, successively carries out injection of light dope ion and heavy doping ion and injects; Form source/drain extension region and source/drain region successively; Thereby save the formation of a photoresist layer and removed step, simplified the making step of the nmos pass transistor that comprises the LDD structure, finally reduced transistorized production cost.
But the relevant parameter reference implementation that the light dope ion injects and heavy doping ion is injected in present embodiment example
Need to prove; In the above-described embodiments, be example with the ldmos transistor of two kinds of concrete structures and a kind of nmos pass transistor of concrete structure, but the present invention is not restricted to this; The inventive method can be used to make other transistors that comprise the LDD structure; As: PMOS transistor, high pressure (is 5V or 3.3V like operating voltage) CMOS transistor, thus save the formation of a photoresist layer and removed step, finally saved transistorized production cost.Preferably, said transistorized source region and drain region are unsymmetric structure, promptly are the center with the grid structure, and said source region and said drain region are asymmetric, and said drain region is away from grid structure, thereby can avoid the influence to drain electrode.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art are not breaking away from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (11)
1. a transistorized manufacture method is characterized in that, comprising:
Semiconductor substrate is provided;
On said Semiconductor substrate, form grid structure and the side wall that is positioned at said grid structure side successively;
On said Semiconductor substrate, form the photoresist layer of patterning;
With said photoresist layer, grid structure and side wall is mask, in said Semiconductor substrate, carries out the light dope ion and injects formation source/drain extension region;
With said photoresist layer, grid structure and side wall is mask, in said source/drain extension region, carries out heavy doping ion and injects formation source/drain region.
2. transistorized manufacture method as claimed in claim 1 is characterized in that, said transistor is a ldmos transistor.
3. transistorized manufacture method as claimed in claim 1 is characterized in that, said transistor is the CMOS transistor.
4. transistorized manufacture method as claimed in claim 1 is characterized in that, said transistorized source region and drain region are unsymmetric structure.
5. transistorized manufacture method as claimed in claim 1 is characterized in that, also comprises: form after said source/drain extension region, carry out annealing in process.
6. transistorized manufacture method as claimed in claim 1 is characterized in that, also comprises: form after said source/drain region, carry out annealing in process.
7. transistorized manufacture method as claimed in claim 2 is characterized in that said transistor comprises the body draw-out area, and said manufacture method also comprises: after forming said source/drain region, and the organizator draw-out area; After forming said body draw-out area, carry out annealing in process.
8. like claim 2 or 3 described transistorized manufacture methods, it is characterized in that said transistor is the N type, said light dope ion is a phosphonium ion; The energy range that said light dope ion injects comprises 50keV～100keV, and the dosage range that said light dope ion injects comprises 1E13/cm
2～1E14/cm
2
9. like claim 2 or 3 described transistorized manufacture methods, it is characterized in that said transistor is the N type, said light dope ion is an arsenic ion; The energy range that said light dope ion injects comprises 90keV～200keV, and the dosage range that said light dope ion injects comprises 1E13/cm
2～1E14/cm
2
10. like claim 2 or 3 described transistorized manufacture methods, it is characterized in that said transistor is the P type, said light dope ion is the boron ion; The energy range that said light dope ion injects comprises 12keV～35keV, and the dosage range that said light dope ion injects comprises 1E13/cm
2～1E14/cm
2
11. like claim 2 or 3 described transistorized manufacture methods, it is characterized in that said transistor is the P type, said light dope ion is an indium ion; The energy range that said light dope ion injects comprises 80keV～300keV, and the dosage range that said light dope ion injects comprises 1E13/cm
2～1E14/cm
2
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110300269.8A CN102315131B (en) | 2011-09-28 | 2011-09-28 | The manufacture method of transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201110300269.8A CN102315131B (en) | 2011-09-28 | 2011-09-28 | The manufacture method of transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102315131A true CN102315131A (en) | 2012-01-11 |
| CN102315131B CN102315131B (en) | 2016-03-09 |
Family
ID=45428163
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201110300269.8A Active CN102315131B (en) | 2011-09-28 | 2011-09-28 | The manufacture method of transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102315131B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113937005A (en) * | 2021-12-16 | 2022-01-14 | 广州粤芯半导体技术有限公司 | Method for manufacturing metal oxide semiconductor transistor |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5217910A (en) * | 1990-11-05 | 1993-06-08 | Mitsubishi Denki Kabushiki Kaisha | Method of fabricating semiconductor device having sidewall spacers and oblique implantation |
| US6426258B1 (en) * | 1997-12-24 | 2002-07-30 | Seiko Instruments Inc. | Method of manufacturing a semiconductor integrated circuit device |
| CN1635617A (en) * | 2003-12-29 | 2005-07-06 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing pMOS for titanium silicide preparing process window |
| US20060125041A1 (en) * | 2004-12-14 | 2006-06-15 | Electronics And Telecommunications Research Institute | Transistor using impact ionization and method of manufacturing the same |
| CN101911302A (en) * | 2008-01-10 | 2010-12-08 | 富士通半导体股份有限公司 | Semiconductor device and manufacturing method thereof |
-
2011
- 2011-09-28 CN CN201110300269.8A patent/CN102315131B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5217910A (en) * | 1990-11-05 | 1993-06-08 | Mitsubishi Denki Kabushiki Kaisha | Method of fabricating semiconductor device having sidewall spacers and oblique implantation |
| US6426258B1 (en) * | 1997-12-24 | 2002-07-30 | Seiko Instruments Inc. | Method of manufacturing a semiconductor integrated circuit device |
| CN1635617A (en) * | 2003-12-29 | 2005-07-06 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing pMOS for titanium silicide preparing process window |
| US20060125041A1 (en) * | 2004-12-14 | 2006-06-15 | Electronics And Telecommunications Research Institute | Transistor using impact ionization and method of manufacturing the same |
| CN101911302A (en) * | 2008-01-10 | 2010-12-08 | 富士通半导体股份有限公司 | Semiconductor device and manufacturing method thereof |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113937005A (en) * | 2021-12-16 | 2022-01-14 | 广州粤芯半导体技术有限公司 | Method for manufacturing metal oxide semiconductor transistor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102315131B (en) | 2016-03-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8133790B2 (en) | Semiconductor device and method for fabricating the same | |
| CN103730420A (en) | CMOS transistor manufacturing method | |
| KR20160012459A (en) | Semiconductor device and method of manufacturing the same | |
| JP2006060208A (en) | Source and drain structure for high-performance sub-0.1 micrometer transistor | |
| CN106328504A (en) | Semiconductor structure and formation method thereof | |
| KR101530579B1 (en) | Semiconductor device and method for manufacturing the same | |
| KR20090021459A (en) | Semiconductor device and method of fabricating the same | |
| CN102800595A (en) | NMOS (N-Channel Metal Oxide Semiconductor) transistor forming method and corresponding COMOS structure forming method | |
| CN102315131B (en) | The manufacture method of transistor | |
| CN102737995A (en) | Method for manufacturing semiconductor device | |
| CN106328505A (en) | Formation method of semiconductor structure | |
| CN102751198A (en) | Forming method for MOS (Metal Oxide Semiconductor) transistor in semiconductor device | |
| US20090166764A1 (en) | Transistor and fabricating method thereof | |
| CN102446767B (en) | Manufacturing method of NMOS (N-channel metal oxide semiconductor) transistor | |
| CN101996885A (en) | Metal oxide semiconductor (MOS) transistor and manufacturing method thereof | |
| CN103247528A (en) | Manufacturing method for metal-oxide-semiconductor field effect transistor (MOSFET) | |
| US10727130B2 (en) | Semiconductor device and fabrication method thereof | |
| CN101442009A (en) | Method for preparing source and drain region of MOS device preparation | |
| CN102386131B (en) | Technology for simultaneously realizing drift drain metal oxide semiconductor (DDMOS) drift region and lateral diffused metal oxide semiconductor (LDMOS) drift region | |
| CN104022154A (en) | SOI PMOS ESD device and manufacturing method thereof | |
| CN111834221A (en) | LDMOS (laterally diffused metal oxide semiconductor) and manufacturing method thereof | |
| CN103996679A (en) | SOI NMOS ESD device and preparing method thereof | |
| CN106024900A (en) | Method for improving gate-induced drain leakage (GIDL), and non-uniform channel doping device | |
| CN102468237A (en) | Manufacturing method for semiconductor device | |
| CN103377923A (en) | MOS transistor and forming method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140408 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20140408 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: Zuchongzhi road in Pudong Zhangjiang hi tech park Shanghai city Pudong New Area No. 1399 201203 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |