CN102216997B - 包括主器件的堆叠的半导体器件 - Google Patents

包括主器件的堆叠的半导体器件 Download PDF

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CN102216997B
CN102216997B CN201080003026.1A CN201080003026A CN102216997B CN 102216997 B CN102216997 B CN 102216997B CN 201080003026 A CN201080003026 A CN 201080003026A CN 102216997 B CN102216997 B CN 102216997B
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金镇祺
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Examine Vincent Zhi Cai management company
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Mosaid Technologies Inc
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Abstract

本发明公开了一种包括堆和多个电通路的系统。该堆包括第一非易失性存储芯片和第二非易失性存储芯片，该第二非易失性存储芯片缺少至少一些非核心电路。多个电通路在该第一非易失性芯片和该第二非易失性存储芯片之间延伸，该电通路有助于使该第一非易失性存储芯片向该第二非易失性存储芯片提供器件操作所需的信号和电压。

Description

包括主器件的堆叠的半导体器件
相关领域的交叉引用
本申请要求2009年2月24日提交的序列号为61/154,910的美国临时专利申请和2009年4月24日提交的序列号为12/429,310的美国专利申请的优先权权益，其全部内容通过引用合并于此。
背景技术
现今，许多电子器件包括存储器系统以存储信息。一些存储器系统存储例如数字化的音频或视频信息，用于通过各媒体播放器进行回放。其它的存储器系统存储例如软件和相关信息，以实现不同类型的处理功能。此外，例如动态随机存取存储器(DRAM)系统和静态随机存取存储器(SRAM)系统的一些类型的存储器系统是易失性存储器系统，这是因为在电源被切断时，所存储的数据不被保存；而例如NAND(与非)闪存系统和NOR(或非)闪存系统的其它类型的存储器系统为非易失性存储器系统，这是因为在断电时，所存储的数据被保存。
随着时间的推进，消费者有这样的期望：存储器系统将具有由尺寸逐渐缩小的芯片来提供的逐渐增大的容量。以往，能够实现上述期望的一个重要因素是工艺技术的成比例缩小；但是，在不久的将来，这种方法的成本和局限非常可能逐渐变得更不利。例如，当工艺技术成比例缩小到50nm以下时，由于晶体管特性和可靠性(例如保持力和耐久性)恶化，使得开发几何结构更小的存储器件(尤其是闪存)变得十分具有挑战性。此外，使处理技术的成比例缩小投入巨大。因此，考虑到工艺技术成比例缩小的上述成本和局限，需要研究和开发新的方法来实现容量逐渐增大的存储器系统。
发明内容
本发明的目的在于提供一种适于堆叠的改进的半导体器件。
根据本发明的一方面，提供一种包括堆(stack)的系统。该堆包括第一非易失性存储芯片和第二非易失性存储芯片。该第二非易失性存储芯片至少缺少一些非核心电路，从而有助于减小芯片尺寸。多个电通路(electrical path)在该第一非易失性存储芯片和该第二非易失性存储芯片之间延伸。电通路有助于使该第一非易失性存储芯片向该二非易失性存储芯片提供器件操作所需的信号和电压。
根据本发明的另一方面，提供一种方法，该方法包括制造相互兼容的第一非易失性存储芯片和第二非易失性存储芯片。该第一非易失性存储芯片和该第二非易失性存储芯片被制造为具有大体相似的核心芯片区域，但是仅第一非易失性存储芯片具有另外的芯片区域，在该另外的芯片区域内设置有提供用于分享第一和第二非易失性存储芯片两者优势的功能的电路。另外芯片区域的电路被配置为产生与第一和第二非易失性存储芯片两者相关的器件操作所需的信号和电压。
根据本发明的又一个方案，提供一种方法，其包括：堆叠至少两个半导体芯片。该半导体芯片中的一个为主存储器件且该半导体芯片中的另一个为从存储器件。该方法还包括用过硅通孔将堆叠的该半导体芯片用导线连在一起；以及通过倒装芯片和凸点，使堆叠的该半导体芯片连接至封装印刷电路板。
根据本发明的再一个方案，提供一种非易失性存储芯片，其包括核心区域，该核心区域占据非易失性存储芯片整个芯片区域的大部分(例如超过百分之八十、或者甚至超过百分之九十)。在该非易失性存储芯片的另外的芯片区域内设置有配置为从另一非易失性存储芯片接收信号和电压的电路。该核心区域与该另外的芯片区域相比具有更微型化的工艺技术。
因此，提供一种包括一个或多个存储器件的改进的系统。
附图说明
现在将通过实例，参考所附附图：
图1是示例性NAND闪存芯片平面图的框图；
图2是另一示例性NAND闪存芯片平面图的框图；
图3是又一示例性NAND闪存芯片平面图的框图；
图4是根据示例实施例的用于主存储器件的NAND闪存芯片平面图的框图；
图5是根据示例实施例的用于从存储器件的NAND闪存芯片平面图的框图；
图6是示出根据示例实施例的一个主存储器件和三个从存储器件的框图；
图7以示意图形式示出了与图6中所示的闪存示例实施例一致的堆的一个实例的俯视图；
图8以示意图形式示出了图7中所示的示例性堆的横截面视图；
图9以示意图形式示出了一横截面视图，其与图8的实例的横截面视图相似、但是还例示了包括堆叠器件的设备如何可以还包括采用了倒装芯片和凸点技术的封装的细节；
图10以示意图形式示出了一横截面视图，其与图8的实例的横截面视图相似、但是还例示了包括堆(即堆叠器件)的设备如何可以还包括适于丝焊技术的传统球栅阵列(BGA)封装的细节；
图11是根据替代实施例的用于主存储器件的NAND闪存芯片平面图的框图；
图12是根据替代实施例的用于从存储器件的NAND闪存芯片平面图的框图；
图13是根据另一替代实施例的用于从存储器件的NAND闪存芯片平面图的框图。
在不同的图中，可能使用了相似或相同的附图标记来表示附图中所例示的相似的示例性特征。此外，各种实施例未以比例示出在附图中。例如，为了便于举例说明，可能已经将某些例示的元件或组件的尺寸放大了。
具体实施方式
虽然术语“区域”在其它语境下可被理解为二维限定空间，但是应理解三维限定空间(地带)与此处使用的术语“区域”也是一致的。
图1是示例性NAND闪存芯片平面图100的框图，其例示了在闪存器件的芯片区域内主要组件布置的一种可能划分。在平面图100中，两个行解码器区域110和112分别在相邻的存储单元阵列区域114和116以及118和120之间延伸。对于行解码器区域110和112，在这些区域内可以找到闪存器件的行解码器。如本领域技术人员可理解的，行解码器是为读操作或编程操作选择页面的存储器件的组件。相比之下，对于传统擦除操作，行解码器不是选择页面而是选择块。对于存储单元阵列区域114、116、118和120，在这些区域内可以找到闪存器件的存储单元阵列。如将被本领域技术人员理解地，闪存器件的存储单元阵列包括许多(例如成百万的)闪存单元，每个闪存单元内都可以存储有一位或多位(逻辑“1”或“0”)。
输入/输出焊盘区域124和126沿平面图100的宽度方向的边缘延伸，并且高电压发生器区域130和132以及外围电路区域134沿平面图100的长度方向的边缘延伸。对于输入/输出焊盘区域124和126，在这些区域内可以找到闪存器件的输入/输出焊盘。如将被本领域技术人员很好理解地，各种信号通过这些焊盘传输进入存储芯片或从存储芯片穿出。此外，根据至少一个替代实例，可以设想使与例示的区域类似的输入/输出焊盘区域在最靠近外围电路区域处沿(平面图的)长度方向的边缘延伸。
对于高电压发生器区域130和132，在这些区域内可以找到闪存器件的高电压发生器，例如电荷泵。在一些实例中，“高电压”指的是比操作电压高的电压(例如比Vcc高的电压)。此外，在一些实例中，高电压发生器共同产生一系列较高电压。
对于外围电路区域134，在此区域中找到可以对于器件操作来说重要的其它电路，例如如下所述：
●用于地址和数据的输入和输出缓冲器
●用于控制和指令信号的输入缓冲器
●包括指令解码器的状态机
●地址计数器
●行和列预解码器
●状态寄存器
附加的电路区域140、142也与外围电路区域134相邻。在这些附加的电路区域内，可以找到闪存器件的页面缓冲器和列解码器。页面缓冲器和列解码器是具有本领域技术人员已知的功能的闪存器件的组件。例如，在闪存编程期间，输入数据经由列解码器依次载入页面缓冲器中。
本领域技术人员将理解的是，根据设计者的选择，非易失性存储器的芯片平面图在工作约束和规范内将是不同的。例如，图2是另一示例性NAND闪存芯片平面图200的框图，其与图1中所示出的不同。在平面图200中，行解码器区域200在平面214、220的区域的两个相邻边缘之间延伸。将平面图200和平面图100相比较，可以发现以下不同(非详尽列表)：行解码器区域202沿平面图200的中心向下延伸而非具有两个间隔开的行解码器区域；仅有单一一个高电压发生器230；输入/输出焊盘区域232、234沿相邻于外围电路区域237的平面图边缘延伸。与其他区域中的一些区域相对比，注意用于页面缓冲器和列解码器的附加电路区域240、242与图1中所示的区域140、142类似设置。
图3是再一示例性NAND闪存芯片平面图300的框图，其与前面所示出和描述的其他框图不同。在平面图300中，用于页面缓冲器和列解码器的第一电路区域310位于第一平面(平面0)的区域的中间。也是用于页面缓冲器和列解码器的第二电路区域312位于第二平面(平面1)的区域的中间。多少与图2示出的平面图200类似，提供沿与外围电路相邻的平面图边缘延伸的输入/输出焊盘区域320，并且也仅有单一一个高电压发生器区域340。
在由Zeng等人发表于ISSCC 2009的技术论文摘要第236-237页的“A172mm2 32Gb MLC NAND Flash Memory in 34nm CMOS”中提供了关于平面图300更详尽的细节。
根据至少一些实施例，闪存器件被归为两种可能的类型之一：主闪存芯片和从闪存芯片。主闪存芯片的平面图可以在许多方面都与传统的NAND闪存之一类似，但是包括TSV区域。在这点上，图4是根据示例实施例的NAND闪存芯片平面图400的框图。
在例示的平面图400中，硅通孔(TSV)区域404沿与单元阵列区域408-411相邻的长度方向的边缘设置(例示的芯片顶部，与输入和输出焊盘区域420相对的一侧)。区域430、432、434、440、442、450和452的布局也分别与前面描述的(图1中示出的平面图)区域130、132、134、140、142、110和112相似。根据至少一些实例，与从器件形成对比，例示的平面图400对应于与系统的主存储器件的平面图。
根据一些实施例，主器件包括地址解码器、用于对从器件进行寻址的行预解码器和列预解码器。主器件和从器件之间的差别将通过本公开中随后提供的细节变得更清楚。
现将参考图5，图5是根据示例实施例的从存储器件的NAND闪存芯片平面图500的框图。例示的示例性从器件的器件结构包括TSV区域504。信号接口电路位于TSV区域504、还有TSV区域404(参见图4)中。信号接口电路例如是有助于传输和接收内部数据和控制信号、用于读、编程和擦除操作的高电压信号、以及Vcc和Vss电源信号的电路。此外，明显地，TSV区域被如此命名是因为它们适于具有延伸穿过它们的TSV，以便在堆中的芯片之间提供电通路。
还参考图5，其它例示的区域是NAND存储单元阵列区域508-511、页面缓冲器和列解码器区域540和542、以及行解码区域550和552。这些区域包括用于NAND存储器核心的核心区域590。在一些实例中，核心区域590的特点在于与TSV区域504中的特征相比而言更小的尺寸特征(例如，工艺技术更微型化了)。
图6是示出根据示例实施例的四器件、64Gb的闪存600的框图，该64Gb的闪存600具有一个16Gb主器件602和三个16Gb从器件605-607。从框图将看出，主器件602包括块610，该块610表示用于输入和输出焊盘、外围电路和高电压发生器的区域；但是在从器件605-607内没有类似的区域，从而非常明显地减小芯片尺寸。
对于上述四裸片堆叠(quad die stacked)的示例实施例，有一个16Gb的主器件和三个16Gb的从器件(即所有四个器件总共64Gb的存储容量)。主器件602对总共64Gb(主器件602中16Gb和从器件605-607中48Gb)的存储空间进行寻址。当然将理解：在一些替代实施例中，将堆叠多于四个的裸片；在一些替代实施例中，可以堆叠少于四个的裸片。此外，示例实施例完全不受器件的存储容量的限制，并且可以考虑所有适当的存储容量。
图7和图8分别示意性地描绘了结合图6描述的64Gb闪存600的俯视图和横截面视图。主器件和三个从器件用TSV连接。TSV的数量可以是本领域技术人员能够理解的适于由主芯片和从芯片构成的给定堆的任意数量(例如几十、几百或几千个)。在例示的图8的实例中，堆叠了四个闪存器件，但是也可以考虑堆叠任意两个以上的非易失性存储器件。
图9示意性地示出一横截面视图，其与图8类似，但是还附加示出了闪存600如何处于采用了倒装芯片和凸点技术的封装中。在例示的实例中，凸球(bumping ball)920位于主闪存芯片和封装印刷电路板(PCB)930之间。封装球940位于封装PCB 930下方并与其连接。虽然为了使说明简单和方便，仅示出了两条路径(每条路径都从主闪存芯片延伸穿过凸球、穿过封装PCB以及穿过封装球)，但是要理解通常会有多条这种路径。芯片倒装和凸点技术对于本领域技术人员来说是众所周知的，其可以从名称为“Flip-Chip Assembly”(芯片倒装组装)的网页获得(当前公开地可获得的路径的URL为http://www.siliconfareast.com/flipchipassy.htm)。
现参考图10，其示出了在封装PCB 1030和主闪存器件之间采用丝焊的替代实例。虽然图10中未示出，但是通过在主闪存芯片和封装PCB 1030之间延伸的焊丝1040而形成的电通路也延伸通过PCB 1030和封装球1050。此外，由于BGA封装技术是众所周知的技术，是许多详尽资料的主题，因此将理解此处不需要提供更详尽的特定实施细节，因为它们对于本领域技术人员来说是显而易见的。
图11是根据替代实施例的NAND闪存芯片平面图1100的框图。在例示的平面图1100中，TSV区域1104位于存储核心区域1105和外围电路区域1134之间。此外，将理解图11中示出的区域1108-1111、1120、1130、1132、1134、1140、1142、1150和1152分别与前面描述的图4的平面图400中示出的区域408-411、420、430、432、434、440、442、450和452类似。因此，平面图1100和图4的平面图400之间的主要差别是TSV区域在芯片平面图内的放置。根据至少一些实例，与从器件形成对比，例示的平面图1100对应于与系统的主存储器件的平面图。此外，在一些实例中，与其他(非核心)区域内的特征相比而言，核心区域1105的特点在于更小的尺寸特征。在这一点上，工艺技术例如可以被更加微型化。
现在参见图12，图12是根据替代实施例的用于从存储器件的NAND闪存芯片平面图1200的框图。例示的从器件的器件结构包括沿平面图1200长度方向的边缘的TSV区域以及相邻的页面缓冲器区域1240和列解码器区域1242。此外，将理解：图12中示出的区域1208-1211、1240、1242、1250和1252分别与前面描述的图5的平面图500中所示出的区域508-511、540、542、550和552类似。因此，平面图1200和图5的平面图500之间的主要差别是TSV区域在芯片平面图内的放置。
因此，将图11和图12与图4和图5相比较，可以看出TSV区域在芯片平面图内的放置是不同的(可以考虑任一适当位置)。例如，在另一替代实施例中，TSV区域沿芯片平面图宽度方向的边缘(而非长度方向的边缘)延伸。此外，将理解，TSV区域可以仅沿芯片平面图的长度或宽度的一部分延伸(与沿整个沿芯片平面图的宽度或长度延伸不同)。在又一替代实施例中，TSV区域不与任一芯片平面图的边缘邻接，且可以例如位于芯片平面图的两相对边缘之间的中心。在又一替代实施例中，TSV区域至少大体上位于芯片平面图的两个核心区域之间。此外，在一些实施例中，多个TSV区域可以位于一个芯片平面图内。因此，考虑将一个或多个TSV区域置于芯片平面图内本领域技术人员理解为合适的任一位置。
将理解：根据各种替代实施例(包括图11和图12中例示的那些示例实施例)的主器件和从器件可以与前面示出和描述的图7-图10实例相似的方式堆叠和封装。
在一些实施例中，从存储器件可选择地包括有助于提高组装成品率的从器件测试逻辑电路。在这点上，参见图13。例示的框图与图5的框图相似，但是平面图1300包括用于从器件测试逻辑电路的附加区域1310，该从器件测试逻辑电路配置为在测试期间由主器件驱动。例示的区域1310与TSV区域504相邻；但是可设想在任一给定的芯片平面图内各种适当的可替换位置放置用于从器件逻辑电路的区域。
已经描述了主芯片和从芯片，明显地，主芯片和从芯片应适当地相互兼容，从而主芯片中的非核心电路能够提供分享主芯片和从芯片两者优势的功能。
将理解，可以将一些实施例应用于任一适当的非易失性存储器集成电路系统，包括可以被称为例如NAND闪存EEPROM、NOR闪存EEPROM、AND闪存EEPROM、DiNOR闪存EEPROM、序列闪存EEPROM、ROM、EPROM、FRAM、MRAM和PCRAM。
将理解，此处称元件“连接”或“耦合”至另一元件时，其可以直接连接或耦合至其它元件或者可以有中间元件位于它们之间。相反，此处称元件“直接连接”或“直接耦合”至另一元件时，则在它们之间没有中间元件。应该以类似方式解释用于描述元件之间关系的其他词语(即，“在…之间”相对于“直接在…之间”、“相邻”相对于“直接相邻”、“延伸通过”相对于“整个延伸通过”等等)
可以对所描述的实施例做出某种改变和变型。因此，以上讨论的实施例被认为是示例性而非限制性的。

Claims (15)

1.一种存储器系统，包括：
堆，其包括：
第一非易失性存储芯片；以及
第二非易失性存储芯片，该第二非易失性存储芯片缺少至少一些非核心电路，以有助于减小芯片尺寸；以及
多个电通路，在该第一非易失性存储芯片和该第二非易失性存储芯片之间延伸，该电通路有助于该第一非易失性存储芯片向该第二非易失性存储芯片提供器件操作所需的信号和电压。
2.如权利要求1所述的系统，还包括至少一个另外的非易失性存储芯片，该第一非易失性存储芯片为主器件，第二非易失性存储芯片和另外的非易失性存储芯片为从器件。
3.如权利要求1或2所述的系统，其中该电通路包括硅通孔。
4.如权利要求3所述的系统，还包括封装印刷电路板，该堆通过倒装芯片和凸点而连接至该封装印刷电路板。
5.如权利要求1所述的系统，其中只有该第一非易失性存储芯片包括高电压发生器。
6.如权利要求1或5所述的系统，其中该电压包括用于编程和擦除操作的高电压。
7.如权利要求1、2或5所述的系统，其中该第二非易失性存储芯片包括从器件测试逻辑电路，该从器件测试逻辑电路配置为在测试期间由该第一非易失性存储芯片来驱动。
8.如权利要求1、2或5所述的系统，其中该第一非易失性存储芯片和该第二非易失性存储芯片为NAND闪存芯片。
9.一种用于堆叠存储芯片的方法，包括制造相互兼容的第一非易失性存储芯片和第二非易失性存储芯片，该第一非易失性存储芯片和该第二非易失性存储芯片具有大体相似的核心芯片区域，但仅该第一非易失性存储芯片具有多个另外的芯片区域，在该另外的芯片区域内设置有提供用于分享该第一非易失性存储芯片和该第二非易失性存储芯片两者优势的功能的电路，该另外的芯片区域的电路配置为产生与该第一非易失性存储芯片和该第二非易失性存储芯片两者相关的器件操作所需的信号和电压。
10.如权利要求9所述的方法，其中与该另外的芯片区域相比，该核心芯片区域具有更微型化的工艺技术。
11.如权利要求10所述的方法，其中该另外的芯片区域包括外围电路区域、输入和输出焊盘区域和至少一个高电压发生器区域。
12.如权利要求9、10或11所述的方法，其中该第一非易失性存储芯片和该第二非易失性存储芯片为NAND闪存芯片。
13.如权利要求9、10或11所述的方法，其中该制造包括制造至少一个另外的非易失性存储芯片，该第一非易失性存储芯片作为主器件，并且该第二非易失性存储芯片和另外的非易失性存储芯片作为从器件。
14.如权利要求9、10或11所述的方法，其中该第二非易失性存储芯片包括从器件测试逻辑电路，该从器件测试逻辑电路配置为在测试期间由该第一非易失性存储芯片来驱动。
15.如权利要求9、10或11所述的方法，其中仅该第一非易失性存储芯片包括高电压发生器。
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US8593847B2 (en) 2013-11-26
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