CN102201361A - Method for reducing dislocation effectively and semiconductor device - Google Patents
Method for reducing dislocation effectively and semiconductor device Download PDFInfo
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- CN102201361A CN102201361A CN2010101366708A CN201010136670A CN102201361A CN 102201361 A CN102201361 A CN 102201361A CN 2010101366708 A CN2010101366708 A CN 2010101366708A CN 201010136670 A CN201010136670 A CN 201010136670A CN 102201361 A CN102201361 A CN 102201361A
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- oxide layer
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- nitration case
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Abstract
The invention relates to a method for reducing dislocation effectively. The method comprises the following steps of: providing a silicon substrate, wherein a first oxidation layer and a first nitride layer are formed on the surface of the silicon substrate in sequence; etching the first nitride layer, the first oxidation layer and the silicon substrate to form a shallow trench; fully filling a dielectric layer in the shallow trench to form an isolation structure; removing the first oxidation layer and the first nitride layer, wherein second nitride layers are formed on the side wall and the bottom of the shallow trench before the oxides are filled in the shallow trench. By the method for reducing dislocation effectively, the dislocation problem caused by stress can be improved greatly. The invention also provides a semiconductor device formed by using the method.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly a kind of method of effective minimizing dislocation and a kind of semiconductor device.
Background technology
Along with semiconductor technology enters the deep-submicron epoch, 0.18 the following element of the micron for example active area isolation layer of MOS circuit adopts the shallow trench isolation technology to make mostly, can also find more relevant informations about the shallow trench isolation technology in the patent No. is the United States Patent (USP) of US7112513.
The concrete technology of shallow trench isolation technology comprises: as shown in Figure 1, provide semiconductor silicon substrate 100, and form shallow trench 101 by plasma etching on described semiconductor silicon substrate 100; Insert medium in shallow trench 101, and form dielectric layer on the surface of silicon substrate 100, described dielectric layer material can be oxide containing silicon, as silica; Described dielectric layer is annealed; (ChemicalMechanical Polishing CMP) handles described dielectric layer, to form isolation structure with chemical mechanical polishing method.Silicon substrate 100 between the described isolation structure is an active area 102.
Isolation structure need form grid oxic horizon after forming on the silicon face of described active area 102, reach subsequent device such as grid.Wherein, by on the silicon face of active area 102, passing through means of wet thermal oxidation one deck oxide, as grid oxic horizon.
In the above-mentioned prior art, fill in the isolation structure with the silica be between dielectric layer and the silicon substrate of material because material is different, lattice does not match, and can produce stress, if stress is too high, will cause silicon substrate generation dislocation.
In addition, after having formed isolation structure, when forming grid oxygen on the active area between isolation structure, because gate oxide is to adopt the method for means of wet thermal oxidation to form, though form the efficient height, it is sparse that but the atomic lattice of described gate oxide is arranged, and can not discharge the stress of the rete accumulative total of subsequent technique well, thereby aggravate the formation of silicon substrate dislocation.
Summary of the invention
The problem that the present invention solves provides a kind of method of effective minimizing dislocation, improves the too high caused dislocation problem of stress accumulative total.
For addressing the above problem, the invention provides a kind of method of effective minimizing dislocation, comprising:
Provide the surface to be formed with first oxide layer successively, the silicon substrate of first nitration case;
Etching first nitration case, first oxide layer and silicon substrate form shallow trench;
In described shallow trench, fill full dielectric layer, form isolation structure;
Remove described first oxide layer, first nitration case;
Wherein, in described shallow trench, before the fill oxide, form second nitration case in the sidewall and the bottom of shallow trench.
Optionally, the material of described second nitration case is a silicon nitride, and thickness is 60～200 dusts.
Optionally, the method that forms described second nitration case is a chemical vapour deposition technique.
Optionally, behind the formation isolation structure, also comprise:
On the surface of silicon between the isolation structure, form the first grid oxide layer;
Under hot conditions, on the first grid oxide layer, form the second grid oxide layer then by Low Pressure Chemical Vapor Deposition.
Optionally, form before second nitration case, also comprise: form second oxide layer at shallow trench sidewall and bottom.
Optionally, the material of described second oxide layer is a silica, and described formation technology is thermal oxidation technology or autoxidation technology.
Optionally, described second grid thickness of oxide layer is 300～900 dusts, material oxidation silicon.
Optionally, the formation technology of described second grid oxide layer is the low pressure gas phase deposition method.
Optionally, described high temperature range is 600～900 ℃.
The present invention also provides a kind of semiconductor device, comprising: silicon substrate, be positioned at the shallow trench of silicon substrate, and fill the dielectric layer of full shallow trench; Also comprise: be positioned at the sidewall of shallow trench and second nitration case of bottom.
Optionally, described semiconductor device also comprises: in the silicon substrate of shallow trench sidewall and bottom and second oxide layer between second nitration case.
Compared with prior art, the present invention has the following advantages: before fill oxide forms isolation structure, form nitration case at shallow trench sidewall and bottom earlier, discharged the oxide of follow-up filling and the stress between the substrate better, to improve the dislocation problem of silicon substrate.
Further, on the silicon substrate between the isolation structure, form the thin first grid oxide layer of one deck earlier, as and silicon substrate between good interface, under hot conditions, form the second grid oxide layer then by the low pressure gas phase deposition method, forming the high-temperature oxide atom by the low pressure gas phase deposition method arranges closely, can discharge the stress of the rete accumulative total of subsequent technique better, thereby effectively reduce the formation of dislocation.
Description of drawings
By the more specifically explanation of the preferred embodiments of the present invention shown in the accompanying drawing, above-mentioned and other purpose, feature and advantage of the present invention will be more clear.Reference numeral identical in whole accompanying drawings is indicated identical part.Painstakingly do not draw accompanying drawing, focus on illustrating purport of the present invention by actual size equal proportion convergent-divergent.
Fig. 1 is that existing isolation technology forms the isolation structure schematic diagram;
Fig. 2 to Figure 10 is the process schematic diagram of an embodiment of the method for a kind of effective minimizing dislocation of the present invention.
Embodiment
In the isolation structure process that prior art forms, generally can be because the stress problem between the silicon substrate oxide interior with being filled in shallow trench makes fill oxide generation dislocation, as crack or displacement; In addition on the active area between the isolation structure, the oxide by the wet method deposition can not discharge the stress between the device of silicon substrate and follow-up formation, the device generation dislocation that makes follow-up formation well because atom is arranged sparsely.
For this reason, the present inventor provides a kind of method of effective minimizing dislocation, comprising:
Provide the surface to be formed with first oxide layer successively, the silicon substrate of first nitration case;
Etching first nitration case, first oxide layer and silicon substrate form shallow trench;
In described shallow trench, fill full dielectric layer, form isolation structure;
Remove described first oxide layer, first nitration case.
In described shallow trench, before the fill oxide, form second nitration case in the sidewall and the bottom of shallow trench.
And behind the formation isolation structure, also comprise:
On the surface of silicon between the isolation structure, form the first grid oxide layer;
Under hot conditions, on the first grid oxide layer, form the second grid oxide layer then by Low Pressure Chemical Vapor Deposition.
The present invention utilizes schematic diagram to be described in detail; when the embodiment of the invention was described in detail in detail, for ease of explanation, the profile of expression device architecture can be disobeyed general ratio and be done local the amplification; and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
Fig. 2 to Figure 10 effectively reduces the process schematic diagram of an embodiment of the method for dislocation for the present invention.Below in conjunction with Fig. 2 to Figure 10 the method that the present invention effectively reduces dislocation is described.
With reference to figure 2, silicon substrate 200 is provided, described silicon substrate 200 is used to subsequent technique that platform is provided, and described silicon substrate 200 can be selected from the silicon silicon substrates such as (SOI) on N type silicon substrate, P type silicon substrate, the insulating barrier.
On described silicon substrate 200, form first oxide layer, 210, the first nitration cases 220 successively.
Described first oxide layer, 210 materials are selected from silica, as the etching stop layer in subsequent etching first nitration case 220 steps.
Described first oxide layer 210 can form for selecting thermal oxidation technology for use.Described thermal oxidation technology can select for use oxidation furnace to carry out.
Described first nitration case 220 is selected from silicon nitride, is used for the layer that stops as subsequent chemical-mechanical polishing technology, and described first silicon nitride layer 220 forms technology and can be existing chemical vapor deposition method.
Referring to figs. 2 and 3, described first nitration case 220 of etching, first oxide layer 210 and silicon substrate 200 form shallow trench 300 successively.The formation technology of described shallow trench 300 can be existing plasma etch process.
With reference to figure 4, oxidation is carried out in the sidewall and the bottom of described shallow trench 300, form second oxide layer 301.In the present embodiment, the material of described second oxide layer 301 is an oxide containing silicon, specifically can be silicon dioxide; Thickness is 180 dusts～250 dusts, preferred 200 dusts.The method of described formation second oxide layer 301 is a thermal oxidation technology, specifically selects for use oxidation furnace to carry out.
Described second silicon oxide layer 301 is formed on sidewall in shallow trench 300 and bottom, be because silicon substrate 300 in above-mentioned plasma etching, the lattice order is upset, cause with follow-up oxide lattice to be filled and do not match, so generate silica by its thermal oxidation, improve the lattice match degree, to reduce follow-up oxide and the dislocation between the silicon substrate.
In another example, can adopt autoxidizable method to form second oxide layer 301.
With reference to figure 5, form second nitration case 302 at described shallow trench sidewall and bottom, and second nitration case 302 covers second oxide layer 301.Described second nitration case 302 is selected from silicon nitride, and the thickness of described silicon nitride is 60～200 dusts, can adopt chemical vapour deposition technique to form.Described depositing temperature scope is 600C-900C.
Forming second nitration case 302 is material behaviors of having utilized silicon nitride, and what can discharge silicon substrate silicon and follow-up filling better is between the dielectric layer of material with the silica because the stress that lattice does not match and produced, and then reduces dislocation.
With reference to figure 6, on described first nitration case 220, form the 3rd oxide layer 303, described the 3rd oxide layer 303 is filled described shallow trench simultaneously, and to form isolation structure, the zone between the described isolation structure is an active area.Described the 3rd oxide layer 303 is a silica, specifically can select chemical vapor deposition method or high-density plasma chemical depositing operation for use.Described the 3rd oxide layer 303 is filled shallow trench, to form isolation structure.
With reference to figure 7, remove described the 3rd oxide layer 303 that is positioned at first nitration case, 220 surfaces, until exposing first nitration case 220, described removal technology can be CMP (Chemical Mechanical Polishing) process, here repeats no more.
With reference to figure 8, adopt wet method to remove technology and remove described first nitration case 220 and first oxide layer 210, it needs to be noted, when adopting wet method to remove technology to remove described first nitration case 220, described second nitration case 302 can partly be removed, the 3rd oxide layer 303 of filling can't be removed, thereby the 3rd oxide layer 303 forms than higher step; The following adopted wet method is removed technology removal oxide layer 210 only can remove a spot of filling oxide layer 303.
Be to form in the technology making embodiment of grid oxic horizon at transistor below.
Wherein, do not repeat them here about the formation method such as the above-mentioned description of isolation structure to Fig. 2～Fig. 8.With reference to figure 9, on the active area silicon substrate 200 between the isolation structure, form first grid oxide layer 231, described first grid oxide layer 231 selects for use thermal oxidation technology to form, and described thermal oxidation technology can select for use oxidation furnace to carry out.
Particularly, can for, at first in stove, carry out oxidation, temperature is 750～850 ℃.Oxide thickness is 100 dusts, anneals in nitrogen atmosphere then, and annealing temperature is 900～1000 ℃, and annealing time is 5 minutes to 30 minutes.
With reference to Figure 10, on described first grid oxide layer 231, deposition forms one deck high-temperature oxide 232, and as the second grid oxide layer, thickness is 300～900 dusts, and material can be high-temperature oxydation silicon (HTO).
Described deposition process is low pressure gas phase deposition method (LPCVD), mainly is to utilize silane system (such as SiH4) and oxygen (O2) to deposit high-temperature oxide for reactant; Between about 600～1000 ℃ of the described high temperature, and be preferably between 750～800 ℃; Can certainly utilize other reactants that are to form high-temperature oxide of the present invention.
Traditional oxide layer is to form by the oxidized surface silicon layer, necessary consume silicon substrate, on the contrary, high-temperature oxide layer of the present invention is at high temperature to utilize the low-pressure chemical vapor deposition technology to form, can cover first grid oxide layer 231 equably, form good adhering to, low-pressure chemical vapor deposition is the dry method deposition simultaneously, deposition velocity is slower, the atomic lattice that the forms oxide comparatively dense of arranging, can discharge the stress of silicon substrate 200 and subsequent technique accumulation better, improve the dislocation between the rete.
The present invention also provides a kind of semiconductor device, comprising: silicon substrate, be positioned at the shallow trench of silicon substrate, and fill the dielectric layer of full shallow trench; Wherein, also comprise the sidewall that is positioned at shallow trench and second nitration case of bottom, and in the silicon substrate of shallow trench sidewall and bottom and second oxide layer between second nitration case.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (11)
1. method that effectively reduces dislocation comprises:
Provide the surface to be formed with first oxide layer successively, the silicon substrate of first nitration case;
Etching first nitration case, first oxide layer and silicon substrate form shallow trench;
In described shallow trench, fill full dielectric layer, form isolation structure;
Remove described first oxide layer, first nitration case;
It is characterized in that,
In described shallow trench, before the fill oxide, form second nitration case in the sidewall and the bottom of shallow trench.
2. the method for claim 1 is characterized in that, the material of described second nitration case is a silicon nitride, and thickness is 60～200 dusts.
3. method as claimed in claim 2 is characterized in that, the method that forms described second nitration case is a chemical vapour deposition technique.
4. the method for claim 1 is characterized in that, behind the formation isolation structure, also comprises:
On the surface of silicon between the isolation structure, form the first grid oxide layer;
Under hot conditions, on the first grid oxide layer, form the second grid oxide layer then by Low Pressure Chemical Vapor Deposition.
5. the method for claim 1 is characterized in that, forms before second nitration case, also comprises:
Form second oxide layer at shallow trench sidewall and bottom.
6. method as claimed in claim 5 is characterized in that, the material of described second oxide layer is a silica, and described formation technology is thermal oxidation technology or autoxidation technology.
7. method as claimed in claim 4 is characterized in that, described second grid thickness of oxide layer is 300～900 dusts, material oxidation silicon.
8. method as claimed in claim 7 is characterized in that, the formation technology of described second grid oxide layer is the low pressure gas phase deposition method.
9. method as claimed in claim 4 is characterized in that, described high temperature range is 600～900 ℃.
10. semiconductor device comprises: silicon substrate, be positioned at the shallow trench of silicon substrate, and fill the dielectric layer of full shallow trench; It is characterized in that, also comprise:
Be positioned at the sidewall of shallow trench and second nitration case of bottom.
11. method as claimed in claim 10 is characterized in that, also comprises: in the silicon substrate of shallow trench sidewall and bottom and second oxide layer between second nitration case.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010101366708A CN102201361A (en) | 2010-03-25 | 2010-03-25 | Method for reducing dislocation effectively and semiconductor device |
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| CN2010101366708A CN102201361A (en) | 2010-03-25 | 2010-03-25 | Method for reducing dislocation effectively and semiconductor device |
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| CN102201361A true CN102201361A (en) | 2011-09-28 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102923636A (en) * | 2012-10-30 | 2013-02-13 | 上海丽恒光微电子科技有限公司 | Semiconductor structure and manufacturing method thereof |
| CN106257672A (en) * | 2015-06-18 | 2016-12-28 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device, semiconductor device and electronic installation |
| CN111128854A (en) * | 2019-12-27 | 2020-05-08 | 华虹半导体(无锡)有限公司 | Shallow trench isolation structure and forming method thereof |
Citations (5)
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|---|---|---|---|---|
| US4631803A (en) * | 1985-02-14 | 1986-12-30 | Texas Instruments Incorporated | Method of fabricating defect free trench isolation devices |
| US4952524A (en) * | 1989-05-05 | 1990-08-28 | At&T Bell Laboratories | Semiconductor device manufacture including trench formation |
| US6717231B2 (en) * | 1999-01-11 | 2004-04-06 | Samsung Electronics Co., Ltd. | Trench isolation regions having recess-inhibiting layers therein that protect against overetching |
| CN1992274A (en) * | 2005-12-30 | 2007-07-04 | 国际商业机器公司 | High performance cmos circuits and methods for fabricating the same |
| CN100463143C (en) * | 2005-07-07 | 2009-02-18 | 中芯国际集成电路制造(上海)有限公司 | Strain source-drain CMOS integrating method with oxide separation layer |
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2010
- 2010-03-25 CN CN2010101366708A patent/CN102201361A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4631803A (en) * | 1985-02-14 | 1986-12-30 | Texas Instruments Incorporated | Method of fabricating defect free trench isolation devices |
| US4952524A (en) * | 1989-05-05 | 1990-08-28 | At&T Bell Laboratories | Semiconductor device manufacture including trench formation |
| US6717231B2 (en) * | 1999-01-11 | 2004-04-06 | Samsung Electronics Co., Ltd. | Trench isolation regions having recess-inhibiting layers therein that protect against overetching |
| CN100463143C (en) * | 2005-07-07 | 2009-02-18 | 中芯国际集成电路制造(上海)有限公司 | Strain source-drain CMOS integrating method with oxide separation layer |
| CN1992274A (en) * | 2005-12-30 | 2007-07-04 | 国际商业机器公司 | High performance cmos circuits and methods for fabricating the same |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102923636A (en) * | 2012-10-30 | 2013-02-13 | 上海丽恒光微电子科技有限公司 | Semiconductor structure and manufacturing method thereof |
| CN102923636B (en) * | 2012-10-30 | 2015-11-25 | 上海丽恒光微电子科技有限公司 | Semiconductor structure and preparation method thereof |
| CN106257672A (en) * | 2015-06-18 | 2016-12-28 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of semiconductor device, semiconductor device and electronic installation |
| CN111128854A (en) * | 2019-12-27 | 2020-05-08 | 华虹半导体(无锡)有限公司 | Shallow trench isolation structure and forming method thereof |
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Application publication date: 20110928 |